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Differential D151211

[RISCV] Add test for small vector copies
ClosedPublic

Authored by luke on May 23 2023, 7:16 AM.

Details

Reviewers
reames
craig.topper
asb
kito-cheng
Commits
rG552fc3928a80: [RISCV] Add test for small vector copies

Diff Detail

Event Timeline

luke created this revision.May 23 2023, 7:16 AM
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luke requested review of this revision.May 23 2023, 7:16 AM
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luke added a child revision: D151103: [RISCV] Scalarize small fixed vector copies < XLEN.May 23 2023, 7:16 AM
Harbormaster completed remote builds in B233861: Diff 524698.May 23 2023, 7:56 AM
reames accepted this revision.May 23 2023, 8:53 AM

LGTM, with the following additions:

  1. Add one test with volatile load
  2. Add one test with volatile store
  3. Add one test with atomic load or store
This revision is now accepted and ready to land.May 23 2023, 8:53 AM
luke added a comment.May 23 2023, 10:04 AM
In D151211#4364835, @reames wrote:

LGTM, with the following additions:

  1. Add one test with volatile load
  2. Add one test with volatile store
  3. Add one test with atomic load or store

Just to double check, it should be ok to perform scalarization on volatile/atomic stores right? That's what D150717 already does

This revision was landed with ongoing or failed builds.May 24 2023, 2:25 AM
Closed by commit rG552fc3928a80: [RISCV] Add test for small vector copies (authored by luke). · Explain Why
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG552fc3928a80: [RISCV] Add test for small vector copies.
luke added a comment.May 24 2023, 2:27 AM
In D151211#4365124, @luke wrote:
In D151211#4364835, @reames wrote:

LGTM, with the following additions:

  1. Add one test with volatile load
  2. Add one test with volatile store
  3. Add one test with atomic load or store

Just to double check, it should be ok to perform scalarization on volatile/atomic stores right? That's what D150717 already does

I was only able to add the volatile tests, since there atomic loads/stores don't seem to be permitted for vector types

reames added a comment.May 25 2023, 11:51 AM
In D151211#4365124, @luke wrote:
In D151211#4364835, @reames wrote:

LGTM, with the following additions:

  1. Add one test with volatile load
  2. Add one test with volatile store
  3. Add one test with atomic load or store

Just to double check, it should be ok to perform scalarization on volatile/atomic stores right? That's what D150717 already does

Generally, no. If this is triggering for volatile memory ops, we should probably disable it. There's no profit to be had here, and only risk.

luke mentioned this in D151500: [RISCV] Don't scalarize vector stores if volatile.May 25 2023, 2:18 PM
luke mentioned this in rG90c4db4a2ce6: [RISCV] Don't scalarize vector stores if volatile.May 26 2023, 1:34 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
283 lines

Diff 525075

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
define void @v2i8(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %p
store <2 x i8> %v, ptr %q
ret void
}
define void @v2i16(ptr %p, ptr %q) {
; CHECK-LABEL: v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i16>, ptr %p
store <2 x i16> %v, ptr %q
ret void
}
define void @v2i32(ptr %p, ptr %q) {
; CHECK-LABEL: v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i32>, ptr %p
store <2 x i32> %v, ptr %q
ret void
}
define void @v2i64(ptr %p, ptr %q) {
; CHECK-LABEL: v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i64>, ptr %p
store <2 x i64> %v, ptr %q
ret void
}
define void @v2f16(ptr %p, ptr %q) {
; CHECK-LABEL: v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x half>, ptr %p
store <2 x half> %v, ptr %q
ret void
}
define void @v2f32(ptr %p, ptr %q) {
; CHECK-LABEL: v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x float>, ptr %p
store <2 x float> %v, ptr %q
ret void
}
define void @v2f64(ptr %p, ptr %q) {
; CHECK-LABEL: v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x double>, ptr %p
store <2 x double> %v, ptr %q
ret void
}
define void @v4i8(ptr %p, ptr %q) {
; CHECK-LABEL: v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x i8>, ptr %p
store <4 x i8> %v, ptr %q
ret void
}
define void @v4i16(ptr %p, ptr %q) {
; CHECK-LABEL: v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x i16>, ptr %p
store <4 x i16> %v, ptr %q
ret void
}
define void @v4i32(ptr %p, ptr %q) {
; CHECK-LABEL: v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x i32>, ptr %p
store <4 x i32> %v, ptr %q
ret void
}
define void @v4i64(ptr %p, ptr %q) {
; CHECK-LABEL: v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x i64>, ptr %p
store <4 x i64> %v, ptr %q
ret void
}
define void @v4f16(ptr %p, ptr %q) {
; CHECK-LABEL: v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x half>, ptr %p
store <4 x half> %v, ptr %q
ret void
}
define void @v4f32(ptr %p, ptr %q) {
; CHECK-LABEL: v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x float>, ptr %p
store <4 x float> %v, ptr %q
ret void
}
define void @v4f64(ptr %p, ptr %q) {
; CHECK-LABEL: v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%v = load <4 x double>, ptr %p
store <4 x double> %v, ptr %q
ret void
}
define void @v8i8(ptr %p, ptr %q) {
; CHECK-LABEL: v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <8 x i8>, ptr %p
store <8 x i8> %v, ptr %q
ret void
}
define void @v8i16(ptr %p, ptr %q) {
; CHECK-LABEL: v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %p
store <8 x i16> %v, ptr %q
ret void
}
define void @v8i32(ptr %p, ptr %q) {
; CHECK-LABEL: v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%v = load <8 x i32>, ptr %p
store <8 x i32> %v, ptr %q
ret void
}
define void @v8i64(ptr %p, ptr %q) {
; CHECK-LABEL: v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%v = load <8 x i64>, ptr %p
store <8 x i64> %v, ptr %q
ret void
}
define void @v2i8_align1(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8_align1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %p, align 1
store <2 x i8> %v, ptr %q
ret void
}
define void @v2i8_align2(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8_align2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %p, align 2
store <2 x i8> %v, ptr %q
ret void
}
define void @v2i8_align4(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8_align4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %p, align 4
store <2 x i8> %v, ptr %q
ret void
}
define void @v2i8_volatile_load(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8_volatile_load:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load volatile <2 x i8>, ptr %p
store <2 x i8> %v, ptr %q
ret void
}
define void @v2i8_volatile_store(ptr %p, ptr %q) {
; CHECK-LABEL: v2i8_volatile_store:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%v = load <2 x i8>, ptr %p
store volatile <2 x i8> %v, ptr %q
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}