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Differential D151390

[RISCV] Don't reduce vslidedown's VL in rotations
ClosedPublic

Authored by luke on May 24 2023, 4:54 PM.

Details

Reviewers
craig.topper
reames
asb
kito-cheng
khchen
frasercrmck
Commits
rG6fdc77e4884b: [RISCV] Don't reduce vslidedown's VL in rotations
Summary

Even though we only need to write to the bottom NumElts - Rotation
elements for the vslidedown.vi, we can save an extra vsetivli toggle if
we just keep the wide VL.

(I may be missing something here: is there a reason why we want to explicitly keep the vslidedown narrow?)

Diff Detail

Event Timeline

luke created this revision.May 24 2023, 4:54 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 24 2023, 4:54 PM
Herald added subscribers: jobnoorman, pmatos, VincentWu and 26 others. · View Herald Transcript
luke requested review of this revision.May 24 2023, 4:54 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 24 2023, 4:54 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
luke edited the summary of this revision. (Show Details)May 24 2023, 4:56 PM
luke added reviewers: khchen, frasercrmck.
Harbormaster completed remote builds in B234353: Diff 525373.May 24 2023, 5:26 PM
craig.topper accepted this revision.EditedMay 24 2023, 7:42 PM

LGTM

SiFive's x280 does use VL to limit the number of ALU cycles. But that only makes a big difference with a small VL and a large LMUL.

This revision is now accepted and ready to land.May 24 2023, 7:42 PM
Closed by commit rG6fdc77e4884b: [RISCV] Don't reduce vslidedown's VL in rotations (authored by luke). · Explain WhyMay 25 2023, 1:28 AM
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG6fdc77e4884b: [RISCV] Don't reduce vslidedown's VL in rotations.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
12 lines
test/
CodeGen/
RISCV/
rvv/
21 lines
12 lines
12 lines
42 lines

Diff 525482

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,939 Lines • ▼ Show 20 Lines if (Rotation > 0) {
} }
// We found a rotation. We need to slide HiV down by Rotation. Then we need // We found a rotation. We need to slide HiV down by Rotation. Then we need
// to slide LoV up by (NumElts - Rotation). // to slide LoV up by (NumElts - Rotation).
unsigned InvRotate = NumElts - Rotation; unsigned InvRotate = NumElts - Rotation;
SDValue Res = DAG.getUNDEF(ContainerVT); SDValue Res = DAG.getUNDEF(ContainerVT);
if (HiV) { if (HiV) {
// If we are doing a SLIDEDOWN+SLIDEUP, reduce the VL for the SLIDEDOWN. // Even though we could use a smaller VL, don't to avoid a vsetivli
// FIXME: If we are only doing a SLIDEDOWN, don't reduce the VL as it // toggle.
// causes multiple vsetvlis in some test cases such as lowering
// reduce.mul
SDValue DownVL = VL;
if (LoV)
DownVL = DAG.getConstant(InvRotate, DL, XLenVT);
Res = getVSlidedown(DAG, Subtarget, DL, ContainerVT, Res, HiV, Res = getVSlidedown(DAG, Subtarget, DL, ContainerVT, Res, HiV,
DAG.getConstant(Rotation, DL, XLenVT), TrueMask, DAG.getConstant(Rotation, DL, XLenVT), TrueMask, VL);
DownVL);
} }
if (LoV) if (LoV)
Res = getVSlideup(DAG, Subtarget, DL, ContainerVT, Res, LoV, Res = getVSlideup(DAG, Subtarget, DL, ContainerVT, Res, LoV,
DAG.getConstant(InvRotate, DL, XLenVT), TrueMask, VL, DAG.getConstant(InvRotate, DL, XLenVT), TrueMask, VL,
RISCVII::TAIL_AGNOSTIC); RISCVII::TAIL_AGNOSTIC);
return convertFromScalableVector(VT, Res, DAG, Subtarget); return convertFromScalableVector(VT, Res, DAG, Subtarget);
} }
▲ Show 20 Lines • Show All 12,449 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x i8> @llvm.experimental.vector.reverse.v1i8(<1 x i8> %a) %res = call <1 x i8> @llvm.experimental.vector.reverse.v1i8(<1 x i8> %a)
ret <1 x i8> %res ret <1 x i8> %res
} }
define <2 x i8> @reverse_v2i8(<2 x i8> %a) { define <2 x i8> @reverse_v2i8(<2 x i8> %a) {
; CHECK-LABEL: reverse_v2i8: ; CHECK-LABEL: reverse_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a) %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a)
ret <2 x i8> %res ret <2 x i8> %res
} }
define <4 x i8> @reverse_v4i8(<4 x i8> %a) { define <4 x i8> @reverse_v4i8(<4 x i8> %a) {
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x i16> @llvm.experimental.vector.reverse.v1i16(<1 x i16> %a) %res = call <1 x i16> @llvm.experimental.vector.reverse.v1i16(<1 x i16> %a)
ret <1 x i16> %res ret <1 x i16> %res
} }
define <2 x i16> @reverse_v2i16(<2 x i16> %a) { define <2 x i16> @reverse_v2i16(<2 x i16> %a) {
; CHECK-LABEL: reverse_v2i16: ; CHECK-LABEL: reverse_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16> %a) %res = call <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16> %a)
ret <2 x i16> %res ret <2 x i16> %res
} }
define <4 x i16> @reverse_v4i16(<4 x i16> %a) { define <4 x i16> @reverse_v4i16(<4 x i16> %a) {
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x i32> @llvm.experimental.vector.reverse.v1i32(<1 x i32> %a) %res = call <1 x i32> @llvm.experimental.vector.reverse.v1i32(<1 x i32> %a)
ret <1 x i32> %res ret <1 x i32> %res
} }
define <2 x i32> @reverse_v2i32(<2 x i32> %a) { define <2 x i32> @reverse_v2i32(<2 x i32> %a) {
; CHECK-LABEL: reverse_v2i32: ; CHECK-LABEL: reverse_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %a) %res = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %a)
ret <2 x i32> %res ret <2 x i32> %res
} }
define <4 x i32> @reverse_v4i32(<4 x i32> %a) { define <4 x i32> @reverse_v4i32(<4 x i32> %a) {
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x i64> @llvm.experimental.vector.reverse.v1i64(<1 x i64> %a) %res = call <1 x i64> @llvm.experimental.vector.reverse.v1i64(<1 x i64> %a)
ret <1 x i64> %res ret <1 x i64> %res
} }
define <2 x i64> @reverse_v2i64(<2 x i64> %a) { define <2 x i64> @reverse_v2i64(<2 x i64> %a) {
; CHECK-LABEL: reverse_v2i64: ; CHECK-LABEL: reverse_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a) %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a)
ret <2 x i64> %res ret <2 x i64> %res
} }
define <4 x i64> @reverse_v4i64(<4 x i64> %a) { define <4 x i64> @reverse_v4i64(<4 x i64> %a) {
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x half> @llvm.experimental.vector.reverse.v1f16(<1 x half> %a) %res = call <1 x half> @llvm.experimental.vector.reverse.v1f16(<1 x half> %a)
ret <1 x half> %res ret <1 x half> %res
} }
define <2 x half> @reverse_v2f16(<2 x half> %a) { define <2 x half> @reverse_v2f16(<2 x half> %a) {
; CHECK-LABEL: reverse_v2f16: ; CHECK-LABEL: reverse_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x half> @llvm.experimental.vector.reverse.v2f16(<2 x half> %a) %res = call <2 x half> @llvm.experimental.vector.reverse.v2f16(<2 x half> %a)
ret <2 x half> %res ret <2 x half> %res
} }
define <4 x half> @reverse_v4f16(<4 x half> %a) { define <4 x half> @reverse_v4f16(<4 x half> %a) {
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x float> @llvm.experimental.vector.reverse.v1f32(<1 x float> %a) %res = call <1 x float> @llvm.experimental.vector.reverse.v1f32(<1 x float> %a)
ret <1 x float> %res ret <1 x float> %res
} }
define <2 x float> @reverse_v2f32(<2 x float> %a) { define <2 x float> @reverse_v2f32(<2 x float> %a) {
; CHECK-LABEL: reverse_v2f32: ; CHECK-LABEL: reverse_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float> %a) %res = call <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float> %a)
ret <2 x float> %res ret <2 x float> %res
} }
define <4 x float> @reverse_v4f32(<4 x float> %a) { define <4 x float> @reverse_v4f32(<4 x float> %a) {
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <1 x double> @llvm.experimental.vector.reverse.v1f64(<1 x double> %a) %res = call <1 x double> @llvm.experimental.vector.reverse.v1f64(<1 x double> %a)
ret <1 x double> %res ret <1 x double> %res
} }
define <2 x double> @reverse_v2f64(<2 x double> %a) { define <2 x double> @reverse_v2f64(<2 x double> %a) {
; CHECK-LABEL: reverse_v2f64: ; CHECK-LABEL: reverse_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a) %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a)
ret <2 x double> %res ret <2 x double> %res
} }
define <4 x double> @reverse_v4f64(<4 x double> %a) { define <4 x double> @reverse_v4f64(<4 x double> %a) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x float> @splice_unary(<8 x float> %x) { define <8 x float> @splice_unary(<8 x float> %x) {
; CHECK-LABEL: splice_unary: ; CHECK-LABEL: splice_unary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 7 ; CHECK-NEXT: vslideup.vi v10, v8, 7
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0> %s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x double> @splice_unary2(<8 x double> %x) { define <8 x double> @splice_unary2(<8 x double> %x) {
; CHECK-LABEL: splice_unary2: ; CHECK-LABEL: splice_unary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 6
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 6
; CHECK-NEXT: vslideup.vi v12, v8, 2 ; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x double> %x, <8 x double> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> %s = shufflevector <8 x double> %x, <8 x double> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
ret <8 x double> %s ret <8 x double> %s
} }
define <8 x float> @splice_binary(<8 x float> %x, <8 x float> %y) { define <8 x float> @splice_binary(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: splice_binary: ; CHECK-LABEL: splice_binary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vslideup.vi v8, v10, 6 ; CHECK-NEXT: vslideup.vi v8, v10, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9> %s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9>
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) { define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) {
; CHECK-LABEL: splice_binary2: ; CHECK-LABEL: splice_binary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e64, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v12, 5
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v12, 5
; CHECK-NEXT: vslideup.vi v12, v8, 3 ; CHECK-NEXT: vslideup.vi v12, v8, 3
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x double> %s ret <8 x double> %s
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
ret <8 x i32> %s ret <8 x i32> %s
} }
define <8 x i16> @splice_unary(<8 x i16> %x) { define <8 x i16> @splice_unary(<8 x i16> %x) {
; CHECK-LABEL: splice_unary: ; CHECK-LABEL: splice_unary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vslideup.vi v9, v8, 6 ; CHECK-NEXT: vslideup.vi v9, v8, 6
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1> %s = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
ret <8 x i16> %s ret <8 x i16> %s
} }
define <8 x i32> @splice_unary2(<8 x i32> %x) { define <8 x i32> @splice_unary2(<8 x i32> %x) {
; CHECK-LABEL: splice_unary2: ; CHECK-LABEL: splice_unary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 5
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 5
; CHECK-NEXT: vslideup.vi v10, v8, 3 ; CHECK-NEXT: vslideup.vi v10, v8, 3
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x i32> %s ret <8 x i32> %s
} }
define <8 x i16> @splice_binary(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @splice_binary(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: splice_binary: ; CHECK-LABEL: splice_binary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vslideup.vi v8, v9, 6 ; CHECK-NEXT: vslideup.vi v8, v9, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9> %s = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9>
ret <8 x i16> %s ret <8 x i16> %s
} }
define <8 x i32> @splice_binary2(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @splice_binary2(<8 x i32> %x, <8 x i32> %y) {
; CHECK-LABEL: splice_binary2: ; CHECK-LABEL: splice_binary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 5
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 5
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12> %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
ret <8 x i32> %s ret <8 x i32> %s
} }
define <4 x i16> @shuffle_shuffle_vslidedown(<16 x i16> %0) { define <4 x i16> @shuffle_shuffle_vslidedown(<16 x i16> %0) {
; CHECK-LABEL: shuffle_shuffle_vslidedown: ; CHECK-LABEL: shuffle_shuffle_vslidedown:
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llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+f,+zfh,+experimental-zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+f,+zfh,+experimental-zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+zfh,+experimental-zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+f,+zfh,+experimental-zvfh,+d -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
define <2 x i8> @v2i8(<2 x i8> %a) { define <2 x i8> @v2i8(<2 x i8> %a) {
; CHECK-LABEL: v2i8: ; CHECK-LABEL: v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2i8 = shufflevector <2 x i8> %a, <2 x i8> undef, <2 x i32> <i32 1, i32 0> %v2i8 = shufflevector <2 x i8> %a, <2 x i8> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i8> %v2i8 ret <2 x i8> %v2i8
} }
define <4 x i8> @v2i8_2(<2 x i8> %a, <2 x i8> %b) { define <4 x i8> @v2i8_2(<2 x i8> %a, <2 x i8> %b) {
; CHECK-LABEL: v2i8_2: ; CHECK-LABEL: v2i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4i8 = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4i8 = shufflevector <2 x i8> %a, <2 x i8> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i8> %v4i8 ret <4 x i8> %v4i8
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v32i8 = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v32i8 = shufflevector <16 x i8> %a, <16 x i8> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i8> %v32i8 ret <32 x i8> %v32i8
} }
define <2 x i16> @v2i16(<2 x i16> %a) { define <2 x i16> @v2i16(<2 x i16> %a) {
; CHECK-LABEL: v2i16: ; CHECK-LABEL: v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2i16 = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0> %v2i16 = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i16> %v2i16 ret <2 x i16> %v2i16
} }
define <4 x i16> @v2i16_2(<2 x i16> %a, <2 x i16> %b) { define <4 x i16> @v2i16_2(<2 x i16> %a, <2 x i16> %b) {
; CHECK-LABEL: v2i16_2: ; CHECK-LABEL: v2i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4i16 = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4i16 = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %v4i16 ret <4 x i16> %v4i16
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i16> %v32i16 ret <32 x i16> %v32i16
} }
define <2 x i32> @v2i32(<2 x i32> %a) { define <2 x i32> @v2i32(<2 x i32> %a) {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2i32 = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0> %v2i32 = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %v2i32 ret <2 x i32> %v2i32
} }
define <4 x i32> @v2i32_2(<2 x i32> %a, < 2 x i32> %b) { define <4 x i32> @v2i32_2(<2 x i32> %a, < 2 x i32> %b) {
; CHECK-LABEL: v2i32_2: ; CHECK-LABEL: v2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4i32 = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4i32 = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i32> %v4i32 ret <4 x i32> %v4i32
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v32i32 = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v32i32 = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i32> %v32i32 ret <32 x i32> %v32i32
} }
define <2 x i64> @v2i64(<2 x i64> %a) { define <2 x i64> @v2i64(<2 x i64> %a) {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2i64 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 0> %v2i64 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i64> %v2i64 ret <2 x i64> %v2i64
} }
define <4 x i64> @v2i64_2(<2 x i64> %a, < 2 x i64> %b) { define <4 x i64> @v2i64_2(<2 x i64> %a, < 2 x i64> %b) {
; CHECK-LABEL: v2i64_2: ; CHECK-LABEL: v2i64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4i64 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4i64 = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i64> %v4i64 ret <4 x i64> %v4i64
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v8i64 = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v8i64 = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i64> %v8i64 ret <8 x i64> %v8i64
} }
define <2 x half> @v2f16(<2 x half> %a) { define <2 x half> @v2f16(<2 x half> %a) {
; CHECK-LABEL: v2f16: ; CHECK-LABEL: v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2f16 = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0> %v2f16 = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0>
ret <2 x half> %v2f16 ret <2 x half> %v2f16
} }
define <4 x half> @v2f16_2(<2 x half> %a, <2 x half> %b) { define <4 x half> @v2f16_2(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: v2f16_2: ; CHECK-LABEL: v2f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4f16 = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4f16 = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x half> %v4f16 ret <4 x half> %v4f16
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v32f16 = shufflevector <16 x half> %a, <16 x half> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v32f16 = shufflevector <16 x half> %a, <16 x half> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x half> %v32f16 ret <32 x half> %v32f16
} }
define <2 x float> @v2f32(<2 x float> %a) { define <2 x float> @v2f32(<2 x float> %a) {
; CHECK-LABEL: v2f32: ; CHECK-LABEL: v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2f32 = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0> %v2f32 = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0>
ret <2 x float> %v2f32 ret <2 x float> %v2f32
} }
define <4 x float> @v2f32_2(<2 x float> %a, <2 x float> %b) { define <4 x float> @v2f32_2(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: v2f32_2: ; CHECK-LABEL: v2f32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4f32 = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4f32 = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %v4f32 ret <4 x float> %v4f32
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x float> %v16f32 ret <16 x float> %v16f32
} }
define <2 x double> @v2f64(<2 x double> %a) { define <2 x double> @v2f64(<2 x double> %a) {
; CHECK-LABEL: v2f64: ; CHECK-LABEL: v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v2f64 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0> %v2f64 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0>
ret <2 x double> %v2f64 ret <2 x double> %v2f64
} }
define <4 x double> @v2f64_2(<2 x double> %a, < 2 x double> %b) { define <4 x double> @v2f64_2(<2 x double> %a, < 2 x double> %b) {
; CHECK-LABEL: v2f64_2: ; CHECK-LABEL: v2f64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vslidedown.vi v8, v9, 1 ; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2 ; CHECK-NEXT: vslideup.vi v8, v10, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v4f64 = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %v4f64 = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x double> %v4f64 ret <4 x double> %v4f64
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