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Differential D149724

[RISCV] Promote i1 shuffles to i8 shuffles.
ClosedPublic

Authored by craig.topper on May 2 2023, 11:19 PM.

Details

Reviewers
reames
luke
kito-cheng
rogfer01
frasercrmck
Commits
rG38007dd394c7: [RISCV] Promote i1 shuffles to i8 shuffles.
Summary

Otherwise I think we extract and use a build_vector. There may be
some more improvements that can be made and there might be some
cases that we should do something different for, but this seemed like a
decent starting point.

Diff Detail

Event Timeline

craig.topper created this revision.May 2 2023, 11:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 2 2023, 11:19 PM
Herald added subscribers: jobnoorman, VincentWu, vkmr and 25 others. · View Herald Transcript
craig.topper requested review of this revision.May 2 2023, 11:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 2 2023, 11:19 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B229614: Diff 518978.May 3 2023, 12:04 AM
luke added inline comments.May 3 2023, 1:57 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
3841

Can widenVectorOpsToi8 be reused here? It uses truncates instead of setcc, I'm not sure if that changes the resulting code

craig.topper added inline comments.May 3 2023, 9:42 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
3841

Using SETCC avoids a vand.vi instruction from the truncate lowering that looked unnecessary to me. That probably applies to VECTOR_REVERSE, VECTOR_INTERLEAVE, and VECTOR_DEINTERLEAVE too.

The main issue preventing using widenVectorOpsToi8 is that we can't create a shuffle with getNode. We have to call getVectorShuffle because the Mask isn't part of the operand list.

luke accepted this revision.May 3 2023, 9:47 AM

LGTM

This revision is now accepted and ready to land.May 3 2023, 9:47 AM
This revision was landed with ongoing or failed builds.May 4 2023, 7:47 PM
Closed by commit rG38007dd394c7: [RISCV] Promote i1 shuffles to i8 shuffles. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG38007dd394c7: [RISCV] Promote i1 shuffles to i8 shuffles..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
15 lines
test/
CodeGen/
RISCV/
rvv/
18 lines
2448 lines
256 lines
247 lines

Diff 519728

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 929 Lines • ▼ Show 20 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
ISD::STRICT_UINT_TO_FP, ISD::STRICT_UINT_TO_FP,
ISD::STRICT_FP_TO_SINT, ISD::STRICT_FP_TO_SINT,
ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_UINT,
}, },
VT, Custom); VT, Custom);
setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT,
Custom); Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
// Operations below are different for between masks and other vectors. // Operations below are different for between masks and other vectors.
if (VT.getVectorElementType() == MVT::i1) { if (VT.getVectorElementType() == MVT::i1) {
setOperationAction({ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR, ISD::AND, setOperationAction({ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR, ISD::AND,
ISD::OR, ISD::XOR}, ISD::OR, ISD::XOR},
VT, Custom); VT, Custom);
setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT, setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
ISD::VP_SETCC, ISD::VP_TRUNCATE}, ISD::VP_SETCC, ISD::VP_TRUNCATE},
VT, Custom); VT, Custom);
continue; continue;
} }
// Make SPLAT_VECTOR Legal so DAGCombine will convert splat vectors to // Make SPLAT_VECTOR Legal so DAGCombine will convert splat vectors to
// it before type legalization for i64 vectors on RV32. It will then be // it before type legalization for i64 vectors on RV32. It will then be
// type legalized to SPLAT_VECTOR_PARTS which we need to Custom handle. // type legalized to SPLAT_VECTOR_PARTS which we need to Custom handle.
// FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs // FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs
// improvements first. // improvements first.
if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) { if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) {
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom); setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
} }
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction( setOperationAction(
{ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom); {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom);
setOperationAction({ISD::VP_LOAD, ISD::VP_STORE, setOperationAction({ISD::VP_LOAD, ISD::VP_STORE,
ISD::EXPERIMENTAL_VP_STRIDED_LOAD, ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
ISD::EXPERIMENTAL_VP_STRIDED_STORE, ISD::VP_GATHER, ISD::EXPERIMENTAL_VP_STRIDED_STORE, ISD::VP_GATHER,
ISD::VP_SCATTER}, ISD::VP_SCATTER},
VT, Custom); VT, Custom);
▲ Show 20 Lines • Show All 2,855 Lines • ▼ Show 20 Linesstatic SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1); SDValue V2 = Op.getOperand(1);
SDLoc DL(Op); SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
// Promote i1 shuffle to i8 shuffle.
if (VT.getVectorElementType() == MVT::i1) {
MVT WidenVT = MVT::getVectorVT(MVT::i8, VT.getVectorElementCount());
V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1);
V2 = V2.isUndef() ? DAG.getUNDEF(WidenVT)
: DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2);
SDValue Shuffled = DAG.getVectorShuffle(WidenVT, DL, V1, V2, SVN->getMask());
return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT),
ISD::SETNE);
lukeUnsubmitted
Not Done
ReplyInline Actions

Can widenVectorOpsToi8 be reused here? It uses truncates instead of setcc, I'm not sure if that changes the resulting code

luke: Can widenVectorOpsToi8 be reused here? It uses truncates instead of setcc, I'm not sure if that…
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

Using SETCC avoids a vand.vi instruction from the truncate lowering that looked unnecessary to me. That probably applies to VECTOR_REVERSE, VECTOR_INTERLEAVE, and VECTOR_DEINTERLEAVE too.

The main issue preventing using widenVectorOpsToi8 is that we can't create a shuffle with getNode. We have to call getVectorShuffle because the Mask isn't part of the operand list.

craig.topper: Using SETCC avoids a vand.vi instruction from the truncate lowering that looked unnecessary to…
}
MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
if (SVN->isSplat()) { if (SVN->isSplat()) {
const int Lane = SVN->getSplatIndex(); const int Lane = SVN->getSplatIndex();
if (Lane >= 0) { if (Lane >= 0) {
MVT SVT = VT.getVectorElementType(); MVT SVT = VT.getVectorElementType();
▲ Show 20 Lines • Show All 12,282 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll

Show All 22 Lines
; RV32-NEXT: andi a0, a0, 1 ; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: seqz a0, a0 ; RV32-NEXT: seqz a0, a0
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.x v11, a0 ; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vmsne.vi v0, v11, 0 ; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0 ; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vfirst.m a1, v10
; RV32-NEXT: snez a1, a1
; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV32-NEXT: vmv.v.x v8, a1 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vrgather.vi v9, v8, 0
; RV32-NEXT: vmsne.vi v0, v9, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v8, 10 ; RV32-NEXT: vmv.v.i v8, 10
; RV32-NEXT: vse32.v v8, (a0), v0.t ; RV32-NEXT: vse32.v v8, (a0), v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: constant_folding_crash: ; RV64-LABEL: constant_folding_crash:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a0, 8(a0) ; RV64-NEXT: ld a0, 8(a0)
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: andi a0, a0, 1 ; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: seqz a0, a0 ; RV64-NEXT: seqz a0, a0
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.x v13, a0 ; RV64-NEXT: vmv.v.x v13, a0
; RV64-NEXT: vmsne.vi v0, v13, 0 ; RV64-NEXT: vmsne.vi v0, v13, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0 ; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vfirst.m a1, v12
; RV64-NEXT: snez a1, a1
; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64-NEXT: vmv.v.x v8, a1 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vrgather.vi v9, v8, 0
; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 10 ; RV64-NEXT: vmv.v.i v8, 10
; RV64-NEXT: vse32.v v8, (a0), v0.t ; RV64-NEXT: vse32.v v8, (a0), v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%sunkaddr = getelementptr i8, ptr %v54, i64 8 %sunkaddr = getelementptr i8, ptr %v54, i64 8
%v56 = load i64, ptr %sunkaddr, align 8 %v56 = load i64, ptr %sunkaddr, align 8
%trunc = and i64 %v56, 1 %trunc = and i64 %v56, 1
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

Show All 10 Lines
; ;
define <2 x i1> @reverse_v2i1(<2 x i1> %a) { define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
; CHECK-LABEL: reverse_v2i1: ; CHECK-LABEL: reverse_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a) %res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a)
ret <2 x i1> %res ret <2 x i1> %res
} }
define <4 x i1> @reverse_v4i1(<4 x i1> %a) { define <4 x i1> @reverse_v4i1(<4 x i1> %a) {
; CHECK-LABEL: reverse_v4i1: ; CHECK-LABEL: reverse_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vslidedown.vi v9, v8, 3 ; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vmv.x.s a0, v9 ; CHECK-NEXT: vrsub.vi v9, v9, 3
; CHECK-NEXT: vslide1down.vx v9, v8, a0 ; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vslidedown.vi v10, v8, 2 ; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmv.x.s a0, v10
; CHECK-NEXT: vslide1down.vx v9, v9, a0
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: vslide1down.vx v8, v9, a0
; CHECK-NEXT: vfirst.m a0, v0
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1> %a) %res = call <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1> %a)
ret <4 x i1> %res ret <4 x i1> %res
} }
define <8 x i1> @reverse_v8i1(<8 x i1> %a) { define <8 x i1> @reverse_v8i1(<8 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_v8i1: ; CHECK-LABEL: reverse_v8i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; CHECK: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0 ; CHECK-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 24 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31 ; CHECK-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v9, v9, 7
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 25 ; CHECK-NEXT: vmsne.vi v0, v10, 0
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31 ; CHECK-NEXT: ret
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 26
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 27
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 28
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 29
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 30
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV32-BITS-UNKNOWN-NEXT: snez a0, a0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_v8i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetivli zero, 0, e8, mf8, ta, ma
; RV32-BITS-256-NEXT: vmv.x.s a0, v0
; RV32-BITS-256-NEXT: slli a1, a0, 24
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 25
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 26
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 27
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 28
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 29
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a0, a0, 30
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vfirst.m a0, v0
; RV32-BITS-256-NEXT: snez a0, a0
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_v8i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetivli zero, 0, e8, mf8, ta, ma
; RV32-BITS-512-NEXT: vmv.x.s a0, v0
; RV32-BITS-512-NEXT: slli a1, a0, 24
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 25
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 26
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 27
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 28
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 29
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a0, a0, 30
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vfirst.m a0, v0
; RV32-BITS-512-NEXT: snez a0, a0
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_v8i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e8, mf8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 56
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 57
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 58
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 59
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 60
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 61
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 62
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV64-BITS-UNKNOWN-NEXT: snez a0, a0
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_v8i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetivli zero, 0, e8, mf8, ta, ma
; RV64-BITS-256-NEXT: vmv.x.s a0, v0
; RV64-BITS-256-NEXT: slli a1, a0, 56
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 57
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 58
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 59
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 60
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 61
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a0, a0, 62
; RV64-BITS-256-NEXT: srli a0, a0, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vfirst.m a0, v0
; RV64-BITS-256-NEXT: snez a0, a0
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_v8i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetivli zero, 0, e8, mf8, ta, ma
; RV64-BITS-512-NEXT: vmv.x.s a0, v0
; RV64-BITS-512-NEXT: slli a1, a0, 56
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 57
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 58
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 59
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 60
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 61
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a0, a0, 62
; RV64-BITS-512-NEXT: srli a0, a0, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vfirst.m a0, v0
; RV64-BITS-512-NEXT: snez a0, a0
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1> %a) %res = call <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1> %a)
ret <8 x i1> %res ret <8 x i1> %res
} }
define <16 x i1> @reverse_v16i1(<16 x i1> %a) { define <16 x i1> @reverse_v16i1(<16 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_v16i1: ; CHECK-LABEL: reverse_v16i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; CHECK: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0 ; CHECK-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 16 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31 ; CHECK-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vrsub.vi v9, v9, 15
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 17 ; CHECK-NEXT: vmsne.vi v0, v10, 0
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31 ; CHECK-NEXT: ret
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 18
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 19
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 20
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 21
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 22
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 23
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 24
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 25
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 26
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 27
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 28
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 29
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 30
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV32-BITS-UNKNOWN-NEXT: snez a0, a0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_v16i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV32-BITS-256-NEXT: vmv.x.s a0, v0
; RV32-BITS-256-NEXT: slli a1, a0, 16
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 17
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 18
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 19
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 20
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 21
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 22
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 23
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 24
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 25
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 26
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 27
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 28
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 29
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a0, a0, 30
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vfirst.m a0, v0
; RV32-BITS-256-NEXT: snez a0, a0
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_v16i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV32-BITS-512-NEXT: vmv.x.s a0, v0
; RV32-BITS-512-NEXT: slli a1, a0, 16
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 17
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 18
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 19
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 20
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 21
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 22
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 23
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 24
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 25
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 26
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 27
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 28
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 29
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a0, a0, 30
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vfirst.m a0, v0
; RV32-BITS-512-NEXT: snez a0, a0
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_v16i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 48
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 49
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 50
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 51
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 52
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 53
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 54
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 55
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 56
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 57
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 58
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 59
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 60
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 61
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 62
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV64-BITS-UNKNOWN-NEXT: snez a0, a0
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_v16i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-BITS-256-NEXT: vmv.x.s a0, v0
; RV64-BITS-256-NEXT: slli a1, a0, 48
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 49
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 50
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 51
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 52
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 53
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 54
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 55
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 56
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 57
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 58
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 59
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 60
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 61
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a0, a0, 62
; RV64-BITS-256-NEXT: srli a0, a0, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vfirst.m a0, v0
; RV64-BITS-256-NEXT: snez a0, a0
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_v16i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-BITS-512-NEXT: vmv.x.s a0, v0
; RV64-BITS-512-NEXT: slli a1, a0, 48
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 49
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 50
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 51
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 52
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 53
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 54
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 55
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 56
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 57
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 58
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 59
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 60
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 61
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a0, a0, 62
; RV64-BITS-512-NEXT: srli a0, a0, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vfirst.m a0, v0
; RV64-BITS-512-NEXT: snez a0, a0
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a) %res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a)
ret <16 x i1> %res ret <16 x i1> %res
} }
define <32 x i1> @reverse_v32i1(<32 x i1> %a) { define <32 x i1> @reverse_v32i1(<32 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_v32i1: ; CHECK-LABEL: reverse_v32i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; CHECK: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-NEXT: li a0, 32
; RV32-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: srli a1, a0, 31 ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; RV32-BITS-UNKNOWN-NEXT: li a2, 32 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, a2, e8, m2, ta, ma ; CHECK-NEXT: vle8.v v8, (a0)
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vmv.v.i v10, 0
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 1 ; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31 ; CHECK-NEXT: vrgather.vv v12, v10, v8
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vmsne.vi v0, v12, 0
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 2 ; CHECK-NEXT: ret
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 3
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 4
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 5
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 6
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 7
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 8
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 9
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 10
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 11
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 12
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 13
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 14
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 15
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 16
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 17
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 18
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 19
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 20
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 21
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 22
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 23
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 24
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 25
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 26
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 27
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 28
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a1, a0, 29
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 30
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV32-BITS-UNKNOWN-NEXT: snez a0, a0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_v32i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV32-BITS-256-NEXT: vmv.x.s a0, v0
; RV32-BITS-256-NEXT: srli a1, a0, 31
; RV32-BITS-256-NEXT: li a2, 32
; RV32-BITS-256-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 1
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 2
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 3
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 4
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 5
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 6
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 7
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 8
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 9
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 10
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 11
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 12
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 13
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 14
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 15
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 16
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 17
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 18
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 19
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 20
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 21
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 22
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 23
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 24
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 25
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 26
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 27
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 28
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a1, a0, 29
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: slli a0, a0, 30
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vfirst.m a0, v0
; RV32-BITS-256-NEXT: snez a0, a0
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_v32i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV32-BITS-512-NEXT: vmv.x.s a0, v0
; RV32-BITS-512-NEXT: srli a1, a0, 31
; RV32-BITS-512-NEXT: li a2, 32
; RV32-BITS-512-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 1
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 2
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 3
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 4
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 5
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 6
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 7
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 8
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 9
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 10
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 11
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 12
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 13
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 14
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 15
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 16
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 17
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 18
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 19
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 20
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 21
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 22
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 23
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 24
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 25
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 26
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 27
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 28
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a1, a0, 29
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: slli a0, a0, 30
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vfirst.m a0, v0
; RV32-BITS-512-NEXT: snez a0, a0
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_v32i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0
; RV64-BITS-UNKNOWN-NEXT: srliw a1, a0, 31
; RV64-BITS-UNKNOWN-NEXT: li a2, 32
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 33
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 34
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 35
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 36
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 37
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 38
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 39
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 40
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 41
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 42
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 43
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 44
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 45
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 46
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 47
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 48
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 49
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 50
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 51
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 52
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 53
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 54
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 55
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 56
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 57
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 58
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 59
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 60
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 61
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 62
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV64-BITS-UNKNOWN-NEXT: snez a0, a0
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_v32i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV64-BITS-256-NEXT: vmv.x.s a0, v0
; RV64-BITS-256-NEXT: srliw a1, a0, 31
; RV64-BITS-256-NEXT: li a2, 32
; RV64-BITS-256-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 33
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 34
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 35
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 36
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 37
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 38
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 39
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 40
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 41
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 42
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 43
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 44
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 45
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 46
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 47
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 48
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 49
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 50
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 51
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 52
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 53
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 54
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 55
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 56
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 57
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 58
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 59
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 60
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 61
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a0, a0, 62
; RV64-BITS-256-NEXT: srli a0, a0, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vfirst.m a0, v0
; RV64-BITS-256-NEXT: snez a0, a0
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_v32i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV64-BITS-512-NEXT: vmv.x.s a0, v0
; RV64-BITS-512-NEXT: srliw a1, a0, 31
; RV64-BITS-512-NEXT: li a2, 32
; RV64-BITS-512-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 33
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 34
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 35
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 36
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 37
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 38
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 39
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 40
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 41
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 42
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 43
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 44
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 45
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 46
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 47
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 48
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 49
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 50
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 51
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 52
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 53
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 54
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 55
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 56
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 57
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 58
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 59
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 60
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 61
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a0, a0, 62
; RV64-BITS-512-NEXT: srli a0, a0, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vfirst.m a0, v0
; RV64-BITS-512-NEXT: snez a0, a0
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a) %res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a)
ret <32 x i1> %res ret <32 x i1> %res
} }
define <64 x i1> @reverse_v64i1(<64 x i1> %a) { define <64 x i1> @reverse_v64i1(<64 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_v64i1: ; CHECK-LABEL: reverse_v64i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; CHECK: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: li a0, 64
; RV32-BITS-UNKNOWN-NEXT: vslidedown.vi v8, v0, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-BITS-UNKNOWN-NEXT: srli a2, a1, 31 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-BITS-UNKNOWN-NEXT: li a0, 64 ; CHECK-NEXT: vle8.v v8, (a0)
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vmv.v.i v12, 0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 1 ; CHECK-NEXT: vrgather.vv v16, v12, v8
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31 ; CHECK-NEXT: vmsne.vi v0, v16, 0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2 ; CHECK-NEXT: ret
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 2
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 3
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 4
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 5
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 6
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 7
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 8
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 9
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 10
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 11
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 12
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 13
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 14
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 15
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 16
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 17
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 18
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 19
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 20
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 21
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 22
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 23
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 24
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 25
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 26
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 27
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 28
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 29
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a2, a1, 30
; RV32-BITS-UNKNOWN-NEXT: srli a2, a2, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: andi a1, a1, 1
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.x.s a1, v0
; RV32-BITS-UNKNOWN-NEXT: srli a2, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 1
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 2
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 3
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 4
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 5
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 6
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 7
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 8
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 9
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 10
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 11
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 12
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 13
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 14
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 15
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 16
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 17
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 18
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 19
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 20
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 21
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 22
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 23
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 24
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 25
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 26
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 27
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 28
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a0, a1, 29
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: slli a1, a1, 30
; RV32-BITS-UNKNOWN-NEXT: srli a1, a1, 31
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV32-BITS-UNKNOWN-NEXT: snez a0, a0
; RV32-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret
;
; RV32-BITS-256-LABEL: reverse_v64i1:
; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-BITS-256-NEXT: vslidedown.vi v8, v0, 1
; RV32-BITS-256-NEXT: vmv.x.s a1, v8
; RV32-BITS-256-NEXT: srli a2, a1, 31
; RV32-BITS-256-NEXT: li a0, 64
; RV32-BITS-256-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 1
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 2
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 3
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 4
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 5
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 6
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 7
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 8
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 9
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 10
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 11
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 12
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 13
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 14
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 15
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 16
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 17
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 18
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 19
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 20
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 21
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 22
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 23
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 24
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 25
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 26
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 27
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 28
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 29
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a2, a1, 30
; RV32-BITS-256-NEXT: srli a2, a2, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: andi a1, a1, 1
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV32-BITS-256-NEXT: vmv.x.s a1, v0
; RV32-BITS-256-NEXT: srli a2, a1, 31
; RV32-BITS-256-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-256-NEXT: slli a0, a1, 1
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 2
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 3
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 4
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 5
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 6
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 7
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 8
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 9
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 10
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 11
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 12
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 13
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 14
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 15
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 16
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 17
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 18
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 19
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 20
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 21
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 22
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 23
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 24
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 25
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 26
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 27
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 28
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a0, a1, 29
; RV32-BITS-256-NEXT: srli a0, a0, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: slli a1, a1, 30
; RV32-BITS-256-NEXT: srli a1, a1, 31
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-256-NEXT: vfirst.m a0, v0
; RV32-BITS-256-NEXT: snez a0, a0
; RV32-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret
;
; RV32-BITS-512-LABEL: reverse_v64i1:
; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-BITS-512-NEXT: vslidedown.vi v8, v0, 1
; RV32-BITS-512-NEXT: vmv.x.s a1, v8
; RV32-BITS-512-NEXT: srli a2, a1, 31
; RV32-BITS-512-NEXT: li a0, 64
; RV32-BITS-512-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 1
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 2
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 3
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 4
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 5
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 6
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 7
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 8
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 9
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 10
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 11
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 12
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 13
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 14
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 15
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 16
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 17
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 18
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 19
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 20
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 21
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 22
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 23
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 24
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 25
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 26
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 27
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 28
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 29
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a2, a1, 30
; RV32-BITS-512-NEXT: srli a2, a2, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: andi a1, a1, 1
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; RV32-BITS-512-NEXT: vmv.x.s a1, v0
; RV32-BITS-512-NEXT: srli a2, a1, 31
; RV32-BITS-512-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a2
; RV32-BITS-512-NEXT: slli a0, a1, 1
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 2
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 3
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 4
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 5
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 6
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 7
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 8
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 9
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 10
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 11
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 12
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 13
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 14
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 15
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 16
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 17
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 18
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 19
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 20
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 21
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 22
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 23
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 24
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 25
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 26
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 27
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 28
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a0, a1, 29
; RV32-BITS-512-NEXT: srli a0, a0, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: slli a1, a1, 30
; RV32-BITS-512-NEXT: srli a1, a1, 31
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV32-BITS-512-NEXT: vfirst.m a0, v0
; RV32-BITS-512-NEXT: snez a0, a0
; RV32-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret
;
; RV64-BITS-UNKNOWN-LABEL: reverse_v64i1:
; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.x.s a0, v0
; RV64-BITS-UNKNOWN-NEXT: srli a1, a0, 63
; RV64-BITS-UNKNOWN-NEXT: li a2, 64
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 1
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 2
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 3
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 4
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 5
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 6
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 7
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 8
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 9
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 10
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 11
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 12
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 13
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 14
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 15
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 16
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 17
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 18
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 19
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 20
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 21
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 22
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 23
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 24
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 25
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 26
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 27
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 28
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 29
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 30
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 31
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: srliw a1, a0, 31
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 33
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 34
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 35
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 36
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 37
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 38
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 39
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 40
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 41
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 42
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 43
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 44
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 45
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 46
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 47
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 48
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 49
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 50
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 51
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 52
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 53
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 54
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 55
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 56
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 57
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 58
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 59
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 60
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a1, a0, 61
; RV64-BITS-UNKNOWN-NEXT: srli a1, a1, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 62
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 63
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vfirst.m a0, v0
; RV64-BITS-UNKNOWN-NEXT: snez a0, a0
; RV64-BITS-UNKNOWN-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret
;
; RV64-BITS-256-LABEL: reverse_v64i1:
; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-BITS-256-NEXT: vmv.x.s a0, v0
; RV64-BITS-256-NEXT: srli a1, a0, 63
; RV64-BITS-256-NEXT: li a2, 64
; RV64-BITS-256-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 1
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 2
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 3
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 4
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 5
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 6
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 7
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 8
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 9
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 10
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 11
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 12
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 13
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 14
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 15
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 16
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 17
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 18
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 19
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 20
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 21
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 22
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 23
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 24
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 25
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 26
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 27
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 28
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 29
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 30
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 31
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: srliw a1, a0, 31
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 33
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 34
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 35
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 36
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 37
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 38
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 39
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 40
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 41
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 42
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 43
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 44
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 45
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 46
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 47
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 48
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 49
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 50
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 51
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 52
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 53
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 54
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 55
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 56
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 57
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 58
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 59
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 60
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a1, a0, 61
; RV64-BITS-256-NEXT: srli a1, a1, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-256-NEXT: slli a0, a0, 62
; RV64-BITS-256-NEXT: srli a0, a0, 63
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vfirst.m a0, v0
; RV64-BITS-256-NEXT: snez a0, a0
; RV64-BITS-256-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret
;
; RV64-BITS-512-LABEL: reverse_v64i1:
; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-BITS-512-NEXT: vmv.x.s a0, v0
; RV64-BITS-512-NEXT: srli a1, a0, 63
; RV64-BITS-512-NEXT: li a2, 64
; RV64-BITS-512-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 1
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 2
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 3
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 4
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 5
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 6
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 7
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 8
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 9
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 10
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 11
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 12
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 13
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 14
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 15
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 16
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 17
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 18
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 19
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 20
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 21
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 22
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 23
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 24
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 25
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 26
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 27
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 28
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 29
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 30
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 31
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: srliw a1, a0, 31
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 33
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 34
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 35
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 36
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 37
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 38
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 39
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 40
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 41
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 42
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 43
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 44
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 45
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 46
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 47
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 48
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 49
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 50
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 51
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 52
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 53
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 54
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 55
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 56
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 57
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 58
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 59
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 60
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a1, a0, 61
; RV64-BITS-512-NEXT: srli a1, a1, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a1
; RV64-BITS-512-NEXT: slli a0, a0, 62
; RV64-BITS-512-NEXT: srli a0, a0, 63
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vfirst.m a0, v0
; RV64-BITS-512-NEXT: snez a0, a0
; RV64-BITS-512-NEXT: vslide1down.vx v8, v8, a0
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret
%res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a) %res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a)
ret <64 x i1> %res ret <64 x i1> %res
} }
define <1 x i8> @reverse_v1i8(<1 x i8> %a) { define <1 x i8> @reverse_v1i8(<1 x i8> %a) {
; CHECK-LABEL: reverse_v1i8: ; CHECK-LABEL: reverse_v1i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 877 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV32 %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV64 %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck --check-prefixes=CHECK,RV64 %s
; Integers ; Integers
define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) { define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; RV32-LABEL: vector_deinterleave_v16i1_v32i1: ; RV32-LABEL: vector_deinterleave_v16i1_v32i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vfirst.m a0, v0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vslide1down.vx v8, v8, a0 ; RV32-NEXT: vid.v v9
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma ; RV32-NEXT: vadd.vv v11, v9, v9
; RV32-NEXT: vmv.x.s a0, v0 ; RV32-NEXT: vrgather.vv v9, v10, v11
; RV32-NEXT: slli a1, a0, 29
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 27
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 25
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 23
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 21
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 19
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: slli a1, a0, 17
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v9, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vfirst.m a1, v9
; RV32-NEXT: snez a1, a1
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: slli a2, a1, 29
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vslide1down.vx v8, v8, a2 ; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: slli a2, a1, 27 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vslide1down.vx v8, v8, a2 ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: slli a2, a1, 25 ; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vslide1down.vx v8, v8, a2 ; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: slli a2, a1, 23 ; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vslide1down.vx v8, v8, a2 ; RV32-NEXT: vadd.vi v12, v11, 1
; RV32-NEXT: slli a2, a1, 21 ; RV32-NEXT: vrgather.vv v13, v10, v12
; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: vadd.vi v10, v11, -15
; RV32-NEXT: vslide1down.vx v8, v8, a2 ; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV32-NEXT: slli a2, a1, 19 ; RV32-NEXT: vmsne.vi v8, v13, 0
; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: vmv.v.v v0, v9
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 17
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: vand.vi v8, v8, 1
; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: slli a2, a0, 30
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 28
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 26
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 24
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 22
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 20
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 18
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a0, a0, 16
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 30
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 28
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 26
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 24
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 22
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 20
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a0, a1, 18
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a1, a1, 16
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vand.vi v8, v8, 1
; RV32-NEXT: vmsne.vi v8, v8, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vector_deinterleave_v16i1_v32i1: ; RV64-LABEL: vector_deinterleave_v16i1_v32i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a0, v0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: snez a0, a0 ; RV64-NEXT: vmerge.vim v10, v8, 1, v0
; RV64-NEXT: vslide1down.vx v8, v8, a0 ; RV64-NEXT: vid.v v9
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma ; RV64-NEXT: vadd.vv v11, v9, v9
; RV64-NEXT: vmv.x.s a0, v0 ; RV64-NEXT: vrgather.vv v9, v10, v11
; RV64-NEXT: slli a1, a0, 61
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 59
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 57
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 55
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 53
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 51
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: slli a1, a0, 49
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v9, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a1, v9
; RV64-NEXT: snez a1, a1
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-NEXT: vmv.x.s a1, v9
; RV64-NEXT: slli a2, a1, 61
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a2 ; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: slli a2, a1, 59 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vslide1down.vx v8, v8, a2 ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: slli a2, a1, 57 ; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vslide1down.vx v8, v8, a2 ; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: slli a2, a1, 55 ; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vslide1down.vx v8, v8, a2 ; RV64-NEXT: vadd.vi v12, v11, 1
; RV64-NEXT: slli a2, a1, 53 ; RV64-NEXT: vrgather.vv v13, v10, v12
; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: vadd.vi v10, v11, -15
; RV64-NEXT: vslide1down.vx v8, v8, a2 ; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV64-NEXT: slli a2, a1, 51 ; RV64-NEXT: vmsne.vi v8, v13, 0
; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: vmv.v.v v0, v9
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 49
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: vand.vi v8, v8, 1
; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: slli a2, a0, 62
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 60
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 58
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 56
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 54
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 52
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 50
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a0, a0, 48
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 62
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 60
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 58
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 56
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 54
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 52
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a0, a1, 50
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a1, a1, 48
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vand.vi v8, v8, 1
; RV64-NEXT: vmsne.vi v8, v8, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec) %retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
ret {<16 x i1>, <16 x i1>} %retval ret {<16 x i1>, <16 x i1>} %retval
} }
define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) { define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_v16i8_v32i8: ; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV32 %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV64 %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
; Integers ; Integers
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) { define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; RV32-LABEL: vector_interleave_v32i1_v16i1: ; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: li a0, 32
; RV32-NEXT: vfirst.m a0, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV32-NEXT: snez a0, a0 ; CHECK-NEXT: vmclr.m v9
; RV32-NEXT: li a2, 32 ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vi v9, v0, 0
; RV32-NEXT: vslide1down.vx v10, v8, a0 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vi v9, v8, 2
; RV32-NEXT: vfirst.m a0, v8 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV32-NEXT: snez a0, a0 ; CHECK-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vslide1down.vx v10, v10, a0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV32-NEXT: vmv.x.s a0, v0 ; CHECK-NEXT: vslidedown.vi v10, v8, 16
; RV32-NEXT: slli a1, a0, 30 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: srli a1, a1, 31 ; CHECK-NEXT: vwaddu.vv v12, v8, v10
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma ; CHECK-NEXT: li a1, -1
; RV32-NEXT: vslide1down.vx v10, v10, a1 ; CHECK-NEXT: vwmaccu.vx v12, a1, v10
; RV32-NEXT: vsetivli zero, 0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV32-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: vmsne.vi v0, v12, 0
; RV32-NEXT: slli a3, a1, 30 ; CHECK-NEXT: ret
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV32-NEXT: vslide1down.vx v8, v10, a3
; RV32-NEXT: slli a2, a0, 29
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 29
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 28
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 28
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 27
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 27
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 26
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 26
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 25
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 25
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 24
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 24
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 23
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 23
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 22
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 22
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 21
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 21
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 20
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 20
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 19
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 19
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 18
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 18
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a0, 17
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a2, a1, 17
; RV32-NEXT: srli a2, a2, 31
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: slli a0, a0, 16
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: slli a1, a1, 16
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vand.vi v8, v8, 1
; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret
;
; RV64-LABEL: vector_interleave_v32i1_v16i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a0, v0
; RV64-NEXT: snez a0, a0
; RV64-NEXT: li a2, 32
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vslide1down.vx v10, v8, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vfirst.m a0, v8
; RV64-NEXT: snez a0, a0
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vslide1down.vx v10, v10, a0
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-NEXT: vmv.x.s a0, v0
; RV64-NEXT: slli a1, a0, 62
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vsetivli zero, 0, e16, mf4, ta, ma
; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: slli a3, a1, 62
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; RV64-NEXT: vslide1down.vx v8, v10, a3
; RV64-NEXT: slli a2, a0, 61
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 61
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 60
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 60
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 59
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 59
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 58
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 58
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 57
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 57
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 56
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 56
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 55
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 55
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 54
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 54
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 53
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 53
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 52
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 52
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 51
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 51
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 50
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 50
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a0, 49
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a2, a1, 49
; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: slli a0, a0, 48
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: slli a1, a1, 48
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vand.vi v8, v8, 1
; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret
%res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b) %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
ret <32 x i1> %res ret <32 x i1> %res
} }
define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: vector_interleave_v16i16_v8i16: ; CHECK-LABEL: vector_interleave_v16i16_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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