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[RISCV] Support vector strict_fsetcc/fsetccs.
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Authored by fakepaper56 on Apr 11 2023, 1:39 AM.

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Summary

The patch supports vector strict_fsetcc/fsetccs. Instead of revserving fflags,
the method to implement scalar quiet compares, the patch implement quiet
compares by masking the signaling compares when either input is NaN [0].

[0]: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-floating-point-compare-instructions

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fakepaper56 created this revision.Apr 11 2023, 1:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 11 2023, 1:39 AM
fakepaper56 requested review of this revision.Apr 11 2023, 1:39 AM

We shouldn't need to touch fflags for the quiet comparisons for vector. We can do what the vector spec shows for isgreater. isgreater is the same as quiet ogt.

# Example of implementing isgreater()
vmfeq.vv v0, va, va
vmfeq.vv v1, vb, vb
vmand.mm v0, v0, v1
vmfgt.vv v0, va, vb, v0.t  #  so only set flags on ordered values.

Address Craig's comment and also support fixed vector type.

fakepaper56 retitled this revision from [RISCV] Support scalable vector strict_fsetcc/fsetccs. to [RISCV] Support vector strict_fsetcc/fsetccs..Apr 12 2023, 8:02 PM
fakepaper56 edited the summary of this revision. (Show Details)
fakepaper56 edited the summary of this revision. (Show Details)

Refine commit message.

fakepaper56 edited the summary of this revision. (Show Details)Apr 13 2023, 12:09 AM
craig.topper added inline comments.Apr 13 2023, 12:41 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
7580

conditon -> condition

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
50

I think maybe this vmflt.vv needs to use mask undisturbed?

craig.topper added inline comments.Apr 13 2023, 12:43 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
7637

I think you can do

auto [Mask, VL] = getDefaultVLOps(InVT, ContainerInVT, DL, DAG, Subtarget);

before the if. Then you don't need this else. The mask will have already been set to all ones by getDefaultVLOps.

craig.topper added inline comments.Apr 13 2023, 12:46 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
7600

Don't we need to signal for qnan? strict_fsetcc oeq won't do that.

fakepaper56 added inline comments.Apr 13 2023, 1:44 AM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
50

Yeah, you are right.

Address Craig's comment.

fakepaper56 marked 4 inline comments as done.Apr 13 2023, 3:03 AM
This revision is now accepted and ready to land.Apr 13 2023, 10:01 AM
This revision was automatically updated to reflect the committed changes.
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll