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[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.
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Authored by craig.topper on Mar 29 2023, 12:47 AM.

Details

Summary

This constructs a proper memory operand for these intrinsics.

Segment load/store will be added in a separate patch.

Diff Detail

Event Timeline

craig.topper created this revision.Mar 29 2023, 12:47 AM
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craig.topper requested review of this revision.Mar 29 2023, 12:47 AM
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kito-cheng added inline comments.Mar 29 2023, 4:00 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1234

I am confused by the argument name? vle and vleff is Unit-Stride Instructions but IsUnitStrided is false?

Fix polarity of IsUnitStrided flags.

This revision is now accepted and ready to land.Apr 5 2023, 6:36 PM
This revision was landed with ongoing or failed builds.Apr 5 2023, 7:28 PM
This revision was automatically updated to reflect the committed changes.