This constructs a proper memory operand for these intrinsics.
Segment load/store will be added in a separate patch.
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| Differential D147119
[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic. ClosedPublic Authored by craig.topper on Mar 29 2023, 12:47 AM.
Details Summary This constructs a proper memory operand for these intrinsics. Segment load/store will be added in a separate patch.
Diff Detail
Event Timeline
This revision is now accepted and ready to land.Apr 5 2023, 6:36 PM This revision was landed with ongoing or failed builds.Apr 5 2023, 7:28 PM Closed by commit rG2c57868e2e87: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic. (authored by craig.topper). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 511256 llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
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I am confused by the argument name? vle and vleff is Unit-Stride Instructions but IsUnitStrided is false?