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Differential D147119

[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.
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Authored by craig.topper on Mar 29 2023, 12:47 AM.

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reames
asb
kito-cheng
Commits
rG2c57868e2e87: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.
Summary

This constructs a proper memory operand for these intrinsics.

Segment load/store will be added in a separate patch.

Diff Detail

Event Timeline

craig.topper created this revision.Mar 29 2023, 12:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2023, 12:47 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 27 others. · View Herald Transcript
craig.topper requested review of this revision.Mar 29 2023, 12:47 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2023, 12:47 AM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added a parent revision: D147004: [RISCV] Add helper function for RVV intrinsics in getTgtMemIntrinsic. NFC.Mar 29 2023, 12:48 AM
Harbormaster completed remote builds in B222425: Diff 509235.Mar 29 2023, 12:48 AM
kito-cheng added inline comments.Mar 29 2023, 4:00 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1234

I am confused by the argument name? vle and vleff is Unit-Stride Instructions but IsUnitStrided is false?

craig.topper updated this revision to Diff 509388.Mar 29 2023, 8:51 AM

Fix polarity of IsUnitStrided flags.

Harbormaster completed remote builds in B222537: Diff 509388.Mar 29 2023, 11:42 AM
kito-cheng accepted this revision.Apr 5 2023, 6:36 PM

LGTM

This revision is now accepted and ready to land.Apr 5 2023, 6:36 PM
This revision was landed with ongoing or failed builds.Apr 5 2023, 7:28 PM
Closed by commit rG2c57868e2e87: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG2c57868e2e87: [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic..
fakepaper56 mentioned this in D154694: [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic..Jul 7 2023, 2:09 AM
fakepaper56 mentioned this in rG74eac85dae01: [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic..Jul 7 2023, 2:52 AM

Revision Contents
Changeset List

PathSize
llvm/
lib/
Target/
RISCV/
28 lines
test/
CodeGen/
RISCV/
15 lines
rvv/
15 lines

Diff 511256

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

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