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Differential D154694

[RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic.
ClosedPublic

Authored by fakepaper56 on Jul 7 2023, 2:09 AM.

Details

Reviewers
asb
reames
craig.topper
kito-cheng
Commits
rG74eac85dae01: [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic.
Summary

This constructs a proper memory operand for riscv_vsoxei_mask and riscv_vsuxei_mask.
I think they are missed in D147119.

Diff Detail

Event Timeline

fakepaper56 created this revision.Jul 7 2023, 2:09 AM
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fakepaper56 requested review of this revision.Jul 7 2023, 2:09 AM
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kito-cheng accepted this revision.Jul 7 2023, 2:10 AM

LGTM

This revision is now accepted and ready to land.Jul 7 2023, 2:10 AM
This revision was landed with ongoing or failed builds.Jul 7 2023, 2:52 AM
Closed by commit rG74eac85dae01: [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic. (authored by fakepaper56). · Explain Why
This revision was automatically updated to reflect the committed changes.
fakepaper56 added a commit: rG74eac85dae01: [RISCV] Add riscv_vsoxei_mask/riscv_vsuxei_mask to getTgtMemIntrinsic..
Harbormaster completed remote builds in B243702: Diff 538034.Jul 7 2023, 3:13 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines

Diff 538048

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,325 Lines • ▼ Show 20 Linesbool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
case Intrinsic::riscv_vluxei: case Intrinsic::riscv_vluxei:
case Intrinsic::riscv_vluxei_mask: case Intrinsic::riscv_vluxei_mask:
return SetRVVLoadStoreInfo(/*PtrOp*/ 1, return SetRVVLoadStoreInfo(/*PtrOp*/ 1,
/*IsStore*/ false, /*IsStore*/ false,
/*IsUnitStrided*/ false); /*IsUnitStrided*/ false);
case Intrinsic::riscv_vsse: case Intrinsic::riscv_vsse:
case Intrinsic::riscv_vsse_mask: case Intrinsic::riscv_vsse_mask:
case Intrinsic::riscv_vsoxei: case Intrinsic::riscv_vsoxei:
case Intrinsic::riscv_vsoxei_mask:
case Intrinsic::riscv_vsuxei: case Intrinsic::riscv_vsuxei:
case Intrinsic::riscv_vsuxei_mask:
return SetRVVLoadStoreInfo(/*PtrOp*/ 1, return SetRVVLoadStoreInfo(/*PtrOp*/ 1,
/*IsStore*/ true, /*IsStore*/ true,
/*IsUnitStrided*/ false); /*IsUnitStrided*/ false);
case Intrinsic::riscv_vlseg2: case Intrinsic::riscv_vlseg2:
case Intrinsic::riscv_vlseg3: case Intrinsic::riscv_vlseg3:
case Intrinsic::riscv_vlseg4: case Intrinsic::riscv_vlseg4:
case Intrinsic::riscv_vlseg5: case Intrinsic::riscv_vlseg5:
case Intrinsic::riscv_vlseg6: case Intrinsic::riscv_vlseg6:
▲ Show 20 Lines • Show All 15,691 Lines • Show Last 20 Lines