[RISCV] Combine (vrgather src, vid) -> vmerge

[luke]

Summary

If a vrgather is using vid as its index, and they both have the same
mask and VL, then it can be replaced with a vmerge of the source and
passthru vectors.

[luke]

llvm/test/CodeGen/RISCV/rvv/combine-gather.ll

11

The vmerge gets folded away at the pseudo instruction stage: https://reviews.llvm.org/D133255#inline-1283170

Perhaps the easiest thing to do here is just check for an all ones mask in this combine

[luke]

Update comment

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

11055

I'm not sure you want VP_MERGE_VL here. VP_MERGE_VL is supposed to be tail undisturbed. I think you want RISCVISD::VSELECT_VL.

llvm/test/CodeGen/RISCV/rvv/combine-gather.ll

18

Shouldn't we be able to implement this shuffle with vslideup/down?

[luke]

llvm/test/CodeGen/RISCV/rvv/combine-gather.ll

18

Yes, I think so. I was working on a patch for this, I’ll put it up later today.
It might actually supersede this patch since it prevents the vrgather vid from being generated when lowering vector_shuffle. And I’m not sure if there’s anywhere else where that sequence of nodes is emitted.

[luke]

Rather than optimise this case, I've uploaded D146711 to try and avoid the gathers in the first place

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (const auto *MGN = dyn_cast<MaskedGatherSDNode>(N))
           MGN->getMemOperand(), NewIndexTy, MGN->getExtensionType());
     const auto *MSN = cast<MaskedScatterSDNode>(N);
     return DAG.getMaskedScatter(
         N->getVTList(), MSN->getMemoryVT(), DL,
         {MSN->getChain(), MSN->getValue(), MSN->getMask(), MSN->getBasePtr(),
          Index, ScaleOp},
         MSN->getMemOperand(), NewIndexTy, MSN->isTruncatingStore());
   }
+  case RISCVISD::VRGATHER_VV_VL: {
+    // (vrgather src, (vid mask, vl), passthru, mask, vl)
+    // ->
+    // (vmerge src, passthru, mask, vl)
+    SDValue Idx = N->getOperand(1);
+    SDValue Mask = N->getOperand(3);
+    SDValue VL = N->getOperand(4);
+    if (Idx.getOpcode() != RISCVISD::VID_VL)
+      break;
+    if (Idx.getOperand(0) != Mask || Idx.getOperand(1) != VL)
+      break;
+    return DAG.getNode(RISCVISD::VP_MERGE_VL, SDLoc(N), N->getValueType(0),
+                       Mask, N->getOperand(0), N->getOperand(2), VL);
+  }
   case RISCVISD::SRA_VL:
   case RISCVISD::SRL_VL:
   case RISCVISD::SHL_VL: {
     SDValue ShAmt = N->getOperand(1);
     if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) {
       // We don't need the upper 32 bits of a 64-bit element for a shift amount.
       SDLoc DL(N);
       SDValue VL = N->getOperand(3);

llvm/test/CodeGen/RISCV/rvv/combine-gather.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s
 
-; FIXME: There should only be one vrgather here
+; FIXME: The vadd.vi should be folded away here
 
 define <8 x i8> @gather_i8(<8 x i8> %v, <8 x i8> %w) {
 ; CHECK-LABEL: gather_i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vid.v v11
-; CHECK-NEXT:    vrgather.vv v10, v8, v11
+; CHECK-NEXT:    vadd.vi v8, v8, 0
 ; CHECK-NEXT:    li a0, 240
 ; CHECK-NEXT:    vmv.s.x v0, a0
-; CHECK-NEXT:    vadd.vi v8, v11, -4
-; CHECK-NEXT:    vrgather.vv v10, v9, v8, v0.t
-; CHECK-NEXT:    vmv1r.v v8, v10
+; CHECK-NEXT:    vid.v v10
+; CHECK-NEXT:    vadd.vi v10, v10, -4
+; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
 ; CHECK-NEXT:    ret
   %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i8> %res
 }