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[RISCV] Model vlseg/vsseg in interleaved memory ops

Authored by luke on Mar 21 2023, 6:06 AM.



If the legalized type is a legal interleaved access type (i.e. there's a
supported vlseg/vsseg instruction for it), the interleaved access pass
will pick any interleaved memory op (wide load + shuffles) and lower it
into a vlseg/vsseg intrinsic.

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luke created this revision.Mar 21 2023, 6:06 AM
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luke requested review of this revision.Mar 21 2023, 6:06 AM
luke added inline comments.Mar 21 2023, 6:09 AM

If we just use the un-legalized type to cost model, then interleaves of <6 x i8> etc. which are common with Factor=3 are reported as really expensive, when in fact they can be selected as vlseg/vsseg.
Perhaps there's a better way to account for this though: I was surprised that getMemoryOpCost reported such a high cost (num elements + 1) for these types.

reames accepted this revision.Apr 3 2023, 8:23 AM

LGTM, though please add a FIXME with a short description of the illegal memory op cost bit. i.e. explain why the if is needed in the code since it's non-obvious.

Your observation about the memory op cost for <6 x i8> is something we should follow up on. That does sound surprising, and I affect it is negatively impacting e.g. SLP vectorization of short vectors. Once you've done that, we can resimplify this code.

This revision is now accepted and ready to land.Apr 3 2023, 8:23 AM
This revision was automatically updated to reflect the committed changes.