Emit CFI directives in epilogue and enable CFIFixup pass for RISC-V.

[varunkumare99]

Summary

This patch tries to add cfi directives in the epilogue which were disabled in D69723
Also enables CFIFixup pass which was added in D114545, to emit cfi_remember_state and cfi_restore_state when reordering is done.
And emits cfi_same_value directives when the unwind table needs to be reset to the initial one.
By default emission unwind tables is disabled for RISC-V.
Need to pass -fasynchronous-unwind-tables to emit unwind tables.

[asb]

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

[varunkumare99]

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

[jrtc27]

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

If that's the case it sounds like we have a lot of test cases that are emitting CFI directives that really should have nounwind.

[shiva0217]

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

[varunkumare99]

This patch emits cfi_same_value directives when the unwind table needs to be reset to the initial one.
By default emission unwind tables is disabled for RISC-V.
Need to pass -fasynchronous-unwind-tables to emit unwind tables.

[varunkumare99]

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

[asb]

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

Sorry for not getting back on this. I was thinking more about real-world testing rather than just test case changes.

[varunkumare99]

In D143248#4199929, @asb wrote:

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

Sorry for not getting back on this. I was thinking more about real-world testing rather than just test case changes.

Hi Alex,
I have tested it with Eigen and RangeV3 test-suite. They have passed with no failures.

[asb]

@kito-cheng, @MaskRay is this something you might be able to help review?

[kito-cheng]

@asb ack, I think I can help review this from the functionality layer and compare to GCC, queue to my TODO :P

[MaskRay]

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

[shiva0217]

In D143248#4177761, @varunkumare99 wrote:

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

Hi Varun,

Could you add the case as a unit test?
Shouldn't all the epilogue CFI guard by EmitCFI?

The content of epilogue looks good to me.
Please wait for Maskray and Kito's comments.

[varunkumare99]

Added testcase to verify emission of cfi_remember_state and cfi_restore_state.

[varunkumare99]

added EmitCFI guard for emission of .cfi_def_cfa_offset in epilogue

[varunkumare99]

In D143248#4238207, @shiva0217 wrote:

In D143248#4177761, @varunkumare99 wrote:

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

Hi Varun,

Could you add the case as a unit test?
Shouldn't all the epilogue CFI guard by EmitCFI?

The content of epilogue looks good to me.
Please wait for Maskray and Kito's comments.

Hi Shiva,
I have updated that changes.

[varunkumare99]

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Could you please have a look at this.
Thanks

[asb]

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Hi @MaskRay - is this a patch you might still be able to help review? Thanks.

[varunkumare99]

In D143248#4359841, @asb wrote:

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Hi @MaskRay - is this a patch you might still be able to help review? Thanks.

is there anyone else maybe I can add as a reviewer?
thanks

[asb]

I dropped MaskRay a quick email in case they're not seeing pings on this thread, but otherwise additional reviewer help very greatly appreciated.

[varunkumare99]

ping @MaskRay

llvm/lib/Target/RISCV/RISCV.h

 class MCOperand;
 class MachineInstr;
 class MachineOperand;
 class PassRegistry;
 class RISCVRegisterBankInfo;
 class RISCVSubtarget;
 class RISCVTargetMachine;
 
+void initializeRISCVCFIFixupPass(PassRegistry &);
+
 FunctionPass *createRISCVCodeGenPreparePass();
 void initializeRISCVCodeGenPreparePass(PassRegistry &);
 
 bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP);
 bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
                                          MCOperand &MCOp, const AsmPrinter &AP);
 

llvm/lib/Target/RISCV/RISCVFrameLowering.h

 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
 
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/Support/TypeSize.h"
 
 namespace llvm {
+
+class MCCFIInstruction;
 class RISCVSubtarget;
 
 class RISCVFrameLowering : public TargetFrameLowering {
 public:
   explicit RISCVFrameLowering(const RISCVSubtarget &STI)
       : TargetFrameLowering(StackGrowsDown,
                             /*StackAlignment=*/Align(16),
                             /*LocalAreaOffset=*/0,

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 }
 
 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
if (FirstSPAdjustAmount) {
     uint64_t SecondSPAdjustAmount =
         getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
     assert(SecondSPAdjustAmount > 0 &&
            "SecondSPAdjustAmount should be greater than zero");
 
     RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
                   StackOffset::getFixed(SecondSPAdjustAmount),
                   MachineInstr::FrameDestroy, getStackAlign());
+
+    // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
+    if (!hasFP(MF)) {
+      unsigned CFIIndex = MF.addFrameInst(
+          MCCFIInstruction::cfiDefCfaOffset(nullptr, -FirstSPAdjustAmount));
+      BuildMI(MBB, LastFrameDestroy, DL,
+              TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndex);
+    }
+  }
+
+  if (hasFP(MF)) {
+    // To find the instruction restoring FP from stack.
+    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
+      if (I->mayLoad() && I->getOperand(0).isReg()) {
+        Register DestReg = I->getOperand(0).getReg();
+        if (DestReg == FPReg) {
+          // If there is frame pointer, after restoring $fp registers, we
+          // need adjust CFA back to the correct sp-based offset.
+          // Emit ".cfi_def_cfa $sp, CFAOffset"
+          uint64_t CFAOffset =
+              FirstSPAdjustAmount
+                  ? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
+                  : -FPOffset;
+          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
+              nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
+          BuildMI(MBB, std::next(I), DL,
+                  TII->get(TargetOpcode::CFI_INSTRUCTION))
+              .addCFIIndex(CFIIndex);
+          break;
+        }
+      }
+    }
+  }
+
+  // Add CFI directives for callee-saved registers.
+  // Iterate over list of callee-saved registers and emit .cfi_restore
+  // directives.
+  for (const auto &Entry : CSI) {
+    Register Reg = Entry.getReg();
+    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
+        nullptr, RI->getDwarfRegNum(Reg, true)));
+    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex)
+        .setMIFlag(MachineInstr::FrameDestroy);
   }
 
   if (FirstSPAdjustAmount)
     StackSize = FirstSPAdjustAmount;
 
   // Deallocate stack
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
                 MachineInstr::FrameDestroy, getStackAlign());
 
   // Emit epilogue for shadow call stack.
   emitSCSEpilogue(MF, MBB, MBBI, DL);
+
+  // After restoring $sp, we need to adjust CFA to $(sp + 0)
+  // Emit ".cfi_def_cfa_offset 0"
+  unsigned CFIIndex =
+      MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
+  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 StackOffset
 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
                                            Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 #include "RISCV.h"
 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVMacroFusion.h"
 #include "RISCVTargetObjectFile.h"
 #include "RISCVTargetTransformInfo.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/CFIFixup.h"
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/MIRParser/MIParser.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/InitializePasses.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/IPO.h"
 #include <optional>
 using namespace llvm;
 
 static cl::opt<bool> EnableRedundantCopyElimination(
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
   initAsmInfo();
 
   // RISC-V supports the MachineOutliner.
   setMachineOutliner(true);
   setSupportsDefaultOutlining(true);
+
+  // RISC-V supports fixing up the DWARF unwind information.
+  if (!getMCAsmInfo()->usesWindowsCFI())
+    setCFIFixup(true);
 }
 
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 

llvm/test/CodeGen/RISCV/try_catch.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -enable-shrink-wrap=true < %s \
+; RUN:   | FileCheck %s -check-prefix=ENABLE
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-unknown-elf"
+
+@_ZTIi = external dso_local constant ptr
+
+; Function Attrs: mustprogress
+define weak dso_local void @_Z5threev() local_unnamed_addr #0 {
+; ENABLE-LABEL: _Z5threev:
+; ENABLE:       # %bb.0:
+; ENABLE-NEXT:    addi sp, sp, -16
+; ENABLE-NEXT:    .cfi_def_cfa_offset 16
+; ENABLE-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; ENABLE-NEXT:    .cfi_offset ra, -8
+; ENABLE-NEXT:    li a0, 4
+; ENABLE-NEXT:    call __cxa_allocate_exception
+; ENABLE-NEXT:    li a1, 7
+; ENABLE-NEXT:    sw a1, 0(a0)
+; ENABLE-NEXT:    lui a1, %hi(_ZTIi)
+; ENABLE-NEXT:    addi a1, a1, %lo(_ZTIi)
+; ENABLE-NEXT:    li a2, 0
+; ENABLE-NEXT:    call __cxa_throw
+  %1 = tail call ptr @__cxa_allocate_exception(i64 4) #3
+  store i32 7, ptr %1, align 16, !tbaa !4
+  tail call void @__cxa_throw(ptr nonnull %1, ptr nonnull @_ZTIi, ptr null) #4
+  unreachable
+}
+
+declare dso_local ptr @__cxa_allocate_exception(i64) local_unnamed_addr
+
+declare dso_local void @__cxa_throw(ptr, ptr, ptr) local_unnamed_addr
+
+; Function Attrs: mustprogress
+define weak dso_local void @_Z3twov() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 {
+; CHECK:    .cfi_offset ra, -8
+; CHECK-NEXT:   .cfi_offset s0, -16
+; CHECK-NEXT:   addi    s0, sp, 48
+; CHECK-NEXT:   .cfi_def_cfa s0, 0
+; CHECK-NEXT:     .cfi_remember_state
+; ENABLE-LABEL: _Z3twov:
+; ENABLE:       # %bb.0:
+; ENABLE-NEXT:    addi sp, sp, -16
+; ENABLE-NEXT:    .cfi_def_cfa_offset 16
+; ENABLE-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; ENABLE-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
+; ENABLE-NEXT:    .cfi_offset ra, -8
+; ENABLE-NEXT:    .cfi_offset s0, -16
+; ENABLE-NEXT:    .cfi_remember_state
+; ENABLE-NEXT:  .Ltmp0:
+; ENABLE-NEXT:    call _Z5threev
+; ENABLE-NEXT:  .Ltmp1:
+; ENABLE-NEXT:  # %bb.1:
+; ENABLE-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; ENABLE-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; ENABLE-NEXT:    .cfi_restore ra
+; ENABLE-NEXT:    .cfi_restore s0
+; ENABLE-NEXT:    addi sp, sp, 16
+; ENABLE-NEXT:    .cfi_def_cfa_offset 0
+; ENABLE-NEXT:    ret
+; ENABLE-NEXT:  .LBB1_2:
+; ENABLE-NEXT:    .cfi_restore_state
+; ENABLE-NEXT:  .Ltmp2:
+; ENABLE-NEXT:    sext.w a1, a1
+; ENABLE-NEXT:    li a2, 1
+; ENABLE-NEXT:    mv s0, a0
+; ENABLE-NEXT:    bne a1, a2, .LBB1_6
+; ENABLE-NEXT:  # %bb.3:
+; ENABLE-NEXT:    mv a0, s0
+; ENABLE-NEXT:    call __cxa_begin_catch
+; ENABLE-NEXT:    li a0, 4
+; ENABLE-NEXT:    call __cxa_allocate_exception
+; ENABLE-NEXT:    li a1, 42
+; ENABLE-NEXT:    sw a1, 0(a0)
+; ENABLE-NEXT:  .Ltmp3:
+; ENABLE-NEXT:    lui a1, %hi(_ZTIi)
+; ENABLE-NEXT:    addi a1, a1, %lo(_ZTIi)
+; ENABLE-NEXT:    li a2, 0
+; ENABLE-NEXT:    call __cxa_throw
+; ENABLE-NEXT:  .Ltmp4:
+; ENABLE-NEXT:  # %bb.4:
+; ENABLE-NEXT:  .LBB1_5:
+; ENABLE-NEXT:  .Ltmp5:
+; ENABLE-NEXT:    mv s0, a0
+; ENABLE-NEXT:    call __cxa_end_catch
+; ENABLE-NEXT:  .LBB1_6:
+; ENABLE-NEXT:    mv a0, s0
+; ENABLE-NEXT:    call _Unwind_Resume@plt
+  invoke void @_Z5threev()
+          to label %12 unwind label %1
+
+1:                                                ; preds = %0
+  %2 = landingpad { ptr, i32 }
+          catch ptr @_ZTIi
+  %3 = extractvalue { ptr, i32 } %2, 1
+  %4 = tail call i32 @llvm.eh.typeid.for(ptr nonnull @_ZTIi) #3
+  %5 = icmp eq i32 %3, %4
+  br i1 %5, label %6, label %13
+
+6:                                                ; preds = %1
+  ; .cfi_restore_state
+  %7 = extractvalue { ptr, i32 } %2, 0
+  %8 = tail call ptr @__cxa_begin_catch(ptr %7) #3
+  %9 = tail call ptr @__cxa_allocate_exception(i64 4) #3
+  store i32 42, ptr %9, align 16, !tbaa !4
+  invoke void @__cxa_throw(ptr nonnull %9, ptr nonnull @_ZTIi, ptr null) #4
+          to label %15 unwind label %10
+
+10:                                               ; preds = %6
+  %11 = landingpad { ptr, i32 }
+          cleanup
+  tail call void @__cxa_end_catch() #3
+  br label %13
+
+12:                                               ; preds = %0
+; .cfi_def_cfa sp, -48
+; .cfi_restore ra
+; .cfi_restore s0
+; add sp, sp, 48
+; .cfi_def_cfa_offset
+  ret void
+
+13:                                               ; preds = %10, %1
+  %14 = phi { ptr, i32 } [ %11, %10 ], [ %2, %1 ]
+  resume { ptr, i32 } %14
+
+15:                                               ; preds = %6
+  unreachable
+}
+
+declare dso_local i32 @__gxx_personality_v0(...)
+
+; Function Attrs: nofree nosync nounwind memory(none)
+declare i32 @llvm.eh.typeid.for(ptr) #1
+
+declare dso_local ptr @__cxa_begin_catch(ptr) local_unnamed_addr
+
+declare dso_local void @__cxa_end_catch() local_unnamed_addr
+
+; Function Attrs: mustprogress norecurse
+define dso_local noundef signext i32 @main() local_unnamed_addr #2 personality ptr @__gxx_personality_v0 {
+; ENABLE-LABEL: main:
+; ENABLE:       # %bb.0:
+; ENABLE-NEXT:    addi sp, sp, -16
+; ENABLE-NEXT:    .cfi_def_cfa_offset 16
+; ENABLE-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; ENABLE-NEXT:    .cfi_offset ra, -8
+; ENABLE-NEXT:    .cfi_remember_state
+; ENABLE-NEXT:  .Ltmp6:
+; ENABLE-NEXT:    call _Z3twov
+; ENABLE-NEXT:  .Ltmp7:
+; ENABLE-NEXT:  # %bb.1:
+; ENABLE-NEXT:    li a0, 0
+; ENABLE-NEXT:  .LBB2_2:
+; ENABLE-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; ENABLE-NEXT:    .cfi_restore ra
+; ENABLE-NEXT:    addi sp, sp, 16
+; ENABLE-NEXT:    .cfi_def_cfa_offset 0
+; ENABLE-NEXT:    ret
+; ENABLE-NEXT:  .LBB2_3:
+; ENABLE-NEXT:    .cfi_restore_state
+; ENABLE-NEXT:  .Ltmp8:
+; ENABLE-NEXT:    call __cxa_begin_catch
+; ENABLE-NEXT:    call __cxa_end_catch
+; ENABLE-NEXT:    li a0, -1
+; ENABLE-NEXT:    j .LBB2_2
+  invoke void @_Z3twov()
+          to label %5 unwind label %1
+
+1:                                                ; preds = %0
+  %2 = landingpad { ptr, i32 }
+          catch ptr null
+  %3 = extractvalue { ptr, i32 } %2, 0
+  %4 = tail call ptr @__cxa_begin_catch(ptr %3) #3
+  tail call void @__cxa_end_catch()
+  br label %5
+
+5:                                                ; preds = %0, %1
+  %6 = phi i32 [ -1, %1 ], [ 0, %0 ]
+  ret i32 %6
+}
+
+attributes #0 = { mustprogress "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-zawrs,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zihintntl,-experimental-ztso,-experimental-zvfh,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xtheadvdot,-xventanacondops,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zihintpause,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #1 = { nofree nosync nounwind memory(none) }
+attributes #2 = { mustprogress norecurse "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-zawrs,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zihintntl,-experimental-ztso,-experimental-zvfh,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xtheadvdot,-xventanacondops,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zihintpause,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #3 = { nounwind }
+attributes #4 = { noreturn }
+
+!llvm.module.flags = !{!0, !1, !2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"target-abi", !"lp64"}
+!2 = !{i32 1, !"SmallDataLimit", i32 8}
+!3 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git f559e781b2bd918d8cac8a878639870a8f26196d)"}
+!4 = !{!5, !5, i64 0}
+!5 = !{!"int", !6, i64 0}
+!6 = !{!"omnipotent char", !7, i64 0}
+!7 = !{!"Simple C++ TBAA"}