Emit CFI directives in epilogue and enable CFIFixup pass for RISC-V.

[varunkumare99]

Summary

This patch tries to add cfi directives in the epilogue which were disabled in D69723
Also enables CFIFixup pass which was added in D114545, to emit cfi_remember_state and cfi_restore_state when reordering is done.
And emits cfi_same_value directives when the unwind table needs to be reset to the initial one.
By default emission unwind tables is disabled for RISC-V.
Need to pass -fasynchronous-unwind-tables to emit unwind tables.

[asb]

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

[varunkumare99]

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

[jrtc27]

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

If that's the case it sounds like we have a lot of test cases that are emitting CFI directives that really should have nounwind.

[shiva0217]

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

[varunkumare99]

This patch emits cfi_same_value directives when the unwind table needs to be reset to the initial one.
By default emission unwind tables is disabled for RISC-V.
Need to pass -fasynchronous-unwind-tables to emit unwind tables.

[varunkumare99]

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

[asb]

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

Sorry for not getting back on this. I was thinking more about real-world testing rather than just test case changes.

[varunkumare99]

In D143248#4199929, @asb wrote:

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

In D143248#4128698, @varunkumare99 wrote:

In D143248#4122933, @asb wrote:

Hi Varun - thanks for filing bug #60698 to help track this issue, and for noticing that there should now be some upstream support for cfi_remember_state and cfi_restore_state.

The first question that comes to my mind is what degree of testing you've done with this?

Hi Alex,
the patch updates over 500 testcases for RISCV(as it adds cfi info the epilogue), which results in a patch of over 30M. Due to which I'm not able to upload.

Sorry for not getting back on this. I was thinking more about real-world testing rather than just test case changes.

Hi Alex,
I have tested it with Eigen and RangeV3 test-suite. They have passed with no failures.

[asb]

@kito-cheng, @MaskRay is this something you might be able to help review?

[kito-cheng]

@asb ack, I think I can help review this from the functionality layer and compare to GCC, queue to my TODO :P

[MaskRay]

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

[shiva0217]

In D143248#4177761, @varunkumare99 wrote:

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

Hi Varun,

Could you add the case as a unit test?
Shouldn't all the epilogue CFI guard by EmitCFI?

The content of epilogue looks good to me.
Please wait for Maskray and Kito's comments.

[varunkumare99]

Added testcase to verify emission of cfi_remember_state and cfi_restore_state.

[varunkumare99]

added EmitCFI guard for emission of .cfi_def_cfa_offset in epilogue

[varunkumare99]

In D143248#4238207, @shiva0217 wrote:

In D143248#4177761, @varunkumare99 wrote:

In D143248#4131555, @shiva0217 wrote:

Hi Varun,

It might be good to have a simple case to illustrate that cfi_remember_state and cfi_restore_state can be generated properly with epilogue CFI.
For examle, could the following case generated with cfi_remember_state and cfi_restore_state as GCC?

extern void foo(void);
void f(int *i) {
  if (*i == 0) {
    *i = 1;
    foo();
    return;
  } else {
    __builtin_printf("Hi");
    *i=0;
  }
}

Hi Shiva, the following is the assembly emitted.

f:
.Lfunc_begin0:
	.loc	0 2 0
	.cfi_startproc
	addi	sp, sp, -16
	.cfi_def_cfa_offset 16
	sd	ra, 8(sp)
	sd	s0, 0(sp)
	.cfi_offset ra, -8
	.cfi_offset s0, -16
	.cfi_remember_state
	mv	s0, a0
.Ltmp0:
	.loc	0 3 6 prologue_end
	lw	a0, 0(a0)
.Ltmp1:
	.loc	0 3 6 is_stmt 0
	beqz	a0, .LBB0_2
.Ltmp2:
	.loc	0 8 3 is_stmt 1
	lui	a0, %hi(.L.str)
	addi	a0, a0, %lo(.L.str)
	call	printf
.Ltmp3:
	.loc	0 9 5
	sw	zero, 0(s0)
.Ltmp4:
	.loc	0 11 1
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp5:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 11 1 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
	ret
.LBB0_2:
	.cfi_restore_state
.Ltmp6:
	.loc	0 0 1
	li	a0, 1
.Ltmp7:
	.loc	0 4 6 is_stmt 1
	sw	a0, 0(s0)
	.loc	0 5 3
	ld	ra, 8(sp)
	ld	s0, 0(sp)
.Ltmp8:
	.cfi_restore ra
	.cfi_restore s0
	.loc	0 5 3 epilogue_begin is_stmt 0
	addi	sp, sp, 16
	.cfi_def_cfa_offset 0
.Ltmp9:
	tail	foo
.Ltmp10:
.Lfunc_end0:
	.size	f, .Lfunc_end0-f
	.cfi_endproc

Hi Varun,

Could you add the case as a unit test?
Shouldn't all the epilogue CFI guard by EmitCFI?

The content of epilogue looks good to me.
Please wait for Maskray and Kito's comments.

Hi Shiva,
I have updated that changes.

[varunkumare99]

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Could you please have a look at this.
Thanks

[asb]

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Hi @MaskRay - is this a patch you might still be able to help review? Thanks.

[varunkumare99]

In D143248#4359841, @asb wrote:

In D143248#4235638, @MaskRay wrote:

In D143248#4233169, @asb wrote:

@kito-cheng, @MaskRay is this something you might be able to help review?

Yes, this is in my queue. I am mostly on trips between March 10 and April 10, so I haven't had enough time to read the issue in depth.

Hi @MaskRay - is this a patch you might still be able to help review? Thanks.

is there anyone else maybe I can add as a reviewer?
thanks

[asb]

I dropped MaskRay a quick email in case they're not seeing pings on this thread, but otherwise additional reviewer help very greatly appreciated.

[varunkumare99]

ping @MaskRay

llvm/lib/Target/RISCV/RISCV.h

 class MCOperand;
 class MachineInstr;
 class MachineOperand;
 class PassRegistry;
 class RISCVRegisterBankInfo;
 class RISCVSubtarget;
 class RISCVTargetMachine;
 
+void initializeRISCVCFIFixupPass(PassRegistry &);
+
 FunctionPass *createRISCVCodeGenPreparePass();
 void initializeRISCVCodeGenPreparePass(PassRegistry &);
 
 bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                     AsmPrinter &AP);
 bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
                                          MCOperand &MCOp, const AsmPrinter &AP);
 

llvm/lib/Target/RISCV/RISCVFrameLowering.h

 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
 
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/Support/TypeSize.h"
 
 namespace llvm {
+
+class MCCFIInstruction;
 class RISCVSubtarget;
 
 class RISCVFrameLowering : public TargetFrameLowering {
 public:
   explicit RISCVFrameLowering(const RISCVSubtarget &STI)
       : TargetFrameLowering(StackGrowsDown,
                             /*StackAlignment=*/Align(16),
                             /*LocalAreaOffset=*/0,
                             /*TransientStackAlignment=*/Align(16)),
         STI(STI) {}
 
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+  void resetCFIToInitialState(MachineBasicBlock &MBB) const override;
 
   uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const;
 
   StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
                                      Register &FrameReg) const override;
 
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 }
 
 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
+  bool EmitCFI = MF.getInfo<RISCVMachineFunctionInfo>()->needsAsyncDwarfUnwindInfo(MF);
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
if (FirstSPAdjustAmount) {
     uint64_t SecondSPAdjustAmount =
         getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
     assert(SecondSPAdjustAmount > 0 &&
            "SecondSPAdjustAmount should be greater than zero");
 
     RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
                   StackOffset::getFixed(SecondSPAdjustAmount),
                   MachineInstr::FrameDestroy, getStackAlign());
+
+    // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
+    if (!hasFP(MF)) {
+      unsigned CFIIndex = MF.addFrameInst(
+          MCCFIInstruction::cfiDefCfaOffset(nullptr, -FirstSPAdjustAmount));
+      BuildMI(MBB, LastFrameDestroy, DL,
+              TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndex);
+    }
+  }
+
+  if (hasFP(MF)) {
+    // To find the instruction restoring FP from stack.
+    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
+      if (I->mayLoad() && I->getOperand(0).isReg()) {
+        Register DestReg = I->getOperand(0).getReg();
+        if (DestReg == FPReg) {
+          // If there is frame pointer, after restoring $fp registers, we
+          // need adjust CFA back to the correct sp-based offset.
+          // Emit ".cfi_def_cfa $sp, CFAOffset"
+          uint64_t CFAOffset =
+              FirstSPAdjustAmount
+                  ? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
+                  : -FPOffset;
+          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
+              nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
+          BuildMI(MBB, std::next(I), DL,
+                  TII->get(TargetOpcode::CFI_INSTRUCTION))
+              .addCFIIndex(CFIIndex);
+          break;
+        }
+      }
+    }
+  }
+
+  // Add CFI directives for callee-saved registers.
+  // Iterate over list of callee-saved registers and emit .cfi_restore
+  // directives.
+  if (EmitCFI) {
+    for (const auto &Entry : CSI) {
+      Register Reg = Entry.getReg();
+      unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
+          nullptr, RI->getDwarfRegNum(Reg, true)));
+      BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndex)
+          .setMIFlag(MachineInstr::FrameDestroy);
+    }
   }
 
   if (FirstSPAdjustAmount)
     StackSize = FirstSPAdjustAmount;
 
   // Deallocate stack
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
                 MachineInstr::FrameDestroy, getStackAlign());
 
   // Emit epilogue for shadow call stack.
   emitSCSEpilogue(MF, MBB, MBBI, DL);
+
+  // After restoring $sp, we need to adjust CFA to $(sp + 0)
+  // Emit ".cfi_def_cfa_offset 0"
+  if (EmitCFI) {
+    unsigned CFIIndex =
+        MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
+    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
+  }
 }
 
 StackOffset
 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
                                            Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
case TargetStackID::WasmLocal:
     return false;
   }
   llvm_unreachable("Invalid TargetStackID::Value");
 }
 
 TargetStackID::Value RISCVFrameLowering::getStackIDForScalableVectors() const {
   return TargetStackID::ScalableVector;
 }
+
+static void insertCFISameValue(const MCInstrDesc &Desc, MachineFunction &MF,
+                               MachineBasicBlock &MBB,
+                               MachineBasicBlock::iterator InsertPt,
+                               unsigned DwarfReg) {
+  unsigned CFIIndex =
+      MF.addFrameInst(MCCFIInstruction::createSameValue(nullptr, DwarfReg));
+  BuildMI(MBB, InsertPt, DebugLoc(), Desc).addCFIIndex(CFIIndex);
+}
+
+void RISCVFrameLowering::resetCFIToInitialState(MachineBasicBlock &MBB) const {
+
+  MachineFunction &MF = *MBB.getParent();
+  const auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  const auto &TRI =
+      static_cast<const RISCVRegisterInfo &>(*Subtarget.getRegisterInfo());
+  const auto &MFI = *MF.getInfo<RISCVMachineFunctionInfo>();
+
+  const MCInstrDesc &CFIDesc = TII.get(TargetOpcode::CFI_INSTRUCTION);
+  DebugLoc DL;
+  // Reset the CFA to `SP + 0`.
+  MachineBasicBlock::iterator InsertPt = MBB.begin();
+  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
+      nullptr, TRI.getDwarfRegNum(RISCV::X2, true), 0));
+  BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
+
+  // Emit .cfi_same_value for callee-saved registers.
+  const std::vector<CalleeSavedInfo> &CSI =
+      MF.getFrameInfo().getCalleeSavedInfo();
+  for (const auto &Info : CSI) {
+    unsigned Reg = Info.getReg();
+    insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
+                       TRI.getDwarfRegNum(Reg, true));
+  }
+}

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

public:
 
   void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
 
   void addSExt32Register(Register Reg);
   bool isSExt32Register(Register Reg) const;
 
   bool isVectorCall() const { return IsVectorCall; }
   void setIsVectorCall() { IsVectorCall = true; }
+  bool needsAsyncDwarfUnwindInfo(const MachineFunction &MF) const;
+  bool needsDwarfUnwindInfo(const MachineFunction &MF) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp

 //=- RISCVMachineFunctionInfo.cpp - RISCV machine function info ---*- C++ -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares RISCV-specific per-machine-function information.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMachineFunctionInfo.h"
+#include "llvm/MC/MCAsmInfo.h"
 
 using namespace llvm;
 
 yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
     const llvm::RISCVMachineFunctionInfo &MFI)
     : VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
       VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
 

 
 void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) {
   SExt32Registers.push_back(Reg);
 }
 
 bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {
   return is_contained(SExt32Registers, Reg);
 }
+
+bool RISCVMachineFunctionInfo::needsDwarfUnwindInfo(
+    const MachineFunction &MF) const {
+  return MF.needsFrameMoves();
+}
+
+bool RISCVMachineFunctionInfo::needsAsyncDwarfUnwindInfo(
+    const MachineFunction &MF) const {
+
+  const Function &F = MF.getFunction();
+  return needsDwarfUnwindInfo(MF) && F.getUWTableKind() == UWTableKind::Async &&
+         !F.hasMinSize();
+}

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 #include "RISCV.h"
 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVMacroFusion.h"
 #include "RISCVTargetObjectFile.h"
 #include "RISCVTargetTransformInfo.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/CFIFixup.h"
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
 #include "llvm/CodeGen/MIRParser/MIParser.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LegacyPassManager.h"
 #include "llvm/InitializePasses.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/IPO.h"
 #include <optional>
 using namespace llvm;
 
 static cl::opt<bool> EnableRedundantCopyElimination(
RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
   initAsmInfo();
 
   // RISC-V supports the MachineOutliner.
   setMachineOutliner(true);
   setSupportsDefaultOutlining(true);
 
   if (TT.isOSFuchsia() && !TT.isArch64Bit())
     report_fatal_error("Fuchsia is only supported for 64-bit");
+
+  // RISC-V supports fixing up the DWARF unwind information.
+  if (!getMCAsmInfo()->usesWindowsCFI())
+    setCFIFixup(true);
 }
 
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 

llvm/test/CodeGen/RISCV/cfiemit-remember-restore.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -o - | FileCheck %s
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-unknown-elf"
+
+@.str = private unnamed_addr constant [3 x i8] c"Hi\00", align 1
+
+; Function Attrs: nounwind uwtable
+define dso_local void @f(ptr nocapture noundef %0) local_unnamed_addr #0 {
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK:         .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_remember_state
+; CHECK:       # %bb.1:
+; CHECK:         .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    .cfi_restore_state
+; CHECK:         .cfi_restore ra
+; CHECK-NEXT:    .cfi_restore s0
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    .cfi_def_cfa_offset 0
+; CHECK-NEXT:    tail foo
+  %2 = load i32, ptr %0, align 4, !tbaa !5
+  %3 = icmp eq i32 %2, 0
+  br i1 %3, label %4, label %5
+
+4:                                                ; preds = %1
+  store i32 1, ptr %0, align 4, !tbaa !5
+  tail call void @foo() #3
+  br label %7
+
+5:                                                ; preds = %1
+  %6 = tail call signext i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(1) @.str)
+  store i32 0, ptr %0, align 4, !tbaa !5
+  br label %7
+
+7:                                                ; preds = %4, %5
+  ret void
+}
+
+declare dso_local void @foo() local_unnamed_addr #1
+
+; Function Attrs: nofree nounwind
+declare dso_local noundef signext i32 @printf(ptr nocapture noundef readonly, ...) local_unnamed_addr #2
+
+attributes #0 = { nounwind uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zfa,-experimental-zihintntl,-experimental-ztso,-experimental-zvfh,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicsr,-zifencei,-zihintpause,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #1 = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zfa,-experimental-zihintntl,-experimental-ztso,-experimental-zvfh,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicsr,-zifencei,-zihintpause,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #2 = { nofree nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zfa,-experimental-zihintntl,-experimental-ztso,-experimental-zvfh,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicsr,-zifencei,-zihintpause,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, !"target-abi", !"lp64"}
+!2 = !{i32 7, !"uwtable", i32 2}
+!3 = !{i32 8, !"SmallDataLimit", i32 8}
+!4 = !{!"clang version 17.0.0 (https://github.com/llvm/llvm-project.git a999669982d0cedacbb7371c96fce95682d582e1)"}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"int", !7, i64 0}
+!7 = !{!"omnipotent char", !8, i64 0}
+!8 = !{!"Simple C/C++ TBAA"}