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Differential D142356

[MC] Use MCRI instead of MRI for MCRegisterInfo. NFC.
AcceptedPublic

Authored by foad on Jan 23 2023, 6:18 AM.

Details

Reviewers
arsenm
andreadb
jhenderson
MaskRay
zuban32
mpaszkowski
Summary

This is to avoid confusion with MachineRegisterInfo.

Diff Detail

Event Timeline

foad created this revision.Jan 23 2023, 6:18 AM
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foad mentioned this in D142215: [MC] Define and use MCInstrDesc implicit_uses and implicit_defs. NFC..Jan 23 2023, 6:19 AM
MaskRay accepted this revision.Jan 23 2023, 6:28 AM

LGTM.

This revision is now accepted and ready to land.Jan 23 2023, 6:28 AM
barannikov88 added a subscriber: barannikov88.Jan 23 2023, 6:57 AM

I don't think this is an improvement. People got used to MRI (which is consistent with MII, MAI, etc.) and will continue to use it, which will introduce more inconsistencies.

This is to avoid confusion with MachineRegisterInfo.

IMHO there is no confusion. MachineRegisterInfo is only used in CodeGen, while MCRegisterInfo is primarily used in MC layer.
Just note that almost all affected files are in MCTargetDesc/AsmParser/Disassembler directories.

foad added a comment.Jan 23 2023, 7:18 AM
In D142356#4073505, @barannikov88 wrote:

IMHO there is no confusion. MachineRegisterInfo is only used in CodeGen, while MCRegisterInfo is primarily used in MC layer.
Just note that almost all affected files are in MCTargetDesc/AsmParser/Disassembler directories.

I don't feel too strongly about it, but there are a bunch of files that use both, like lib/Target/*/*FrameLowering.cpp.

Harbormaster completed remote builds in B209353: Diff 491339.Jan 23 2023, 7:34 AM
barannikov88 added a comment.Jan 23 2023, 7:42 AM
In D142356#4073605, @foad wrote:
In D142356#4073505, @barannikov88 wrote:

IMHO there is no confusion. MachineRegisterInfo is only used in CodeGen, while MCRegisterInfo is primarily used in MC layer.
Just note that almost all affected files are in MCTargetDesc/AsmParser/Disassembler directories.

I don't feel too strongly about it, but there are a bunch of files that use both, like lib/Target/*/*FrameLowering.cpp.

I believe they could be refactored to use TargetRegisterInfo instead. This is at least true for getDwarfRegNum.

Revision Contents

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llvm/
include/
llvm/
DWARFLinker/
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DebugInfo/
LogicalView/
Readers/
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MC/
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MCA/
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HardwareUnits/
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Target/
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lib/
CodeGen/
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DWARFLinker/
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DebugInfo/
LogicalView/
Readers/
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MC/
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MCDisassembler/
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MCA/
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HardwareUnits/
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Object/
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Target/
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MCTargetDesc/
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AMDGPU/
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AsmParser/
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Disassembler/
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MCTargetDesc/
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Utils/
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AsmParser/
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M68k/
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tools/
llvm-dwp/
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llvm-jitlink/
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llvm-mc-assemble-fuzzer/
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llvm-mc/
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llvm-mca/
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llvm-ml/
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Diff 491339

llvm/include/llvm/DWARFLinker/DWARFStreamer.h

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Linesprivate:
void emitMacroTableImpl(const DWARFDebugMacro *MacroTable, void emitMacroTableImpl(const DWARFDebugMacro *MacroTable,
const Offset2UnitMap &UnitMacroMap, const Offset2UnitMap &UnitMacroMap,
OffsetsStringPool &StringPool, uint64_t &OutOffset); OffsetsStringPool &StringPool, uint64_t &OutOffset);
void emitDwarfDebugArangesTable(const CompileUnit &Unit, void emitDwarfDebugArangesTable(const CompileUnit &Unit,
const AddressRanges &LinkedRanges); const AddressRanges &LinkedRanges);
/// \defgroup MCObjects MC layer objects constructed by the streamer /// \defgroup MCObjects MC layer objects constructed by the streamer
/// @{ /// @{
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCObjectFileInfo> MOFI; std::unique_ptr<MCObjectFileInfo> MOFI;
std::unique_ptr<MCContext> MC; std::unique_ptr<MCContext> MC;
MCAsmBackend *MAB; // Owned by MCStreamer MCAsmBackend *MAB; // Owned by MCStreamer
std::unique_ptr<MCInstrInfo> MII; std::unique_ptr<MCInstrInfo> MII;
std::unique_ptr<MCSubtargetInfo> MSTI; std::unique_ptr<MCSubtargetInfo> MSTI;
MCInstPrinter *MIP; // Owned by AsmPrinter MCInstPrinter *MIP; // Owned by AsmPrinter
MCCodeEmitter *MCE; // Owned by MCStreamer MCCodeEmitter *MCE; // Owned by MCStreamer
Show All 38 Lines

llvm/include/llvm/DebugInfo/LogicalView/Readers/LVBinaryReader.h

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Linesclass LVBinaryReader : public LVReader {
using LVSections = std::map<LVSectionIndex, object::SectionRef>; using LVSections = std::map<LVSectionIndex, object::SectionRef>;
LVSections Sections; LVSections Sections;
protected: protected:
// It contains the LVLineDebug elements representing the logical lines for // It contains the LVLineDebug elements representing the logical lines for
// the current compile unit, created by parsing the debug line section. // the current compile unit, created by parsing the debug line section.
LVLines CULines; LVLines CULines;
std::unique_ptr<const MCRegisterInfo> MRI; std::unique_ptr<const MCRegisterInfo> MCRI;
std::unique_ptr<const MCAsmInfo> MAI; std::unique_ptr<const MCAsmInfo> MAI;
std::unique_ptr<const MCSubtargetInfo> STI; std::unique_ptr<const MCSubtargetInfo> STI;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<const MCDisassembler> MD; std::unique_ptr<const MCDisassembler> MD;
std::unique_ptr<MCContext> MC; std::unique_ptr<MCContext> MC;
std::unique_ptr<MCInstPrinter> MIP; std::unique_ptr<MCInstPrinter> MIP;
// Loads all info for the architecture of the provided object file. // Loads all info for the architecture of the provided object file.
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/include/llvm/MC/MCContext.h

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Linesprivate:
std::vector<const MDNode *> LocInfos; std::vector<const MDNode *> LocInfos;
DiagHandlerTy DiagHandler; DiagHandlerTy DiagHandler;
/// The MCAsmInfo for this target. /// The MCAsmInfo for this target.
const MCAsmInfo *MAI; const MCAsmInfo *MAI;
/// The MCRegisterInfo for this target. /// The MCRegisterInfo for this target.
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
/// The MCObjectFileInfo for this target. /// The MCObjectFileInfo for this target.
const MCObjectFileInfo *MOFI; const MCObjectFileInfo *MOFI;
/// The MCSubtargetInfo for this target. /// The MCSubtargetInfo for this target.
const MCSubtargetInfo *MSTI; const MCSubtargetInfo *MSTI;
std::unique_ptr<CodeViewContext> CVContext; std::unique_ptr<CodeViewContext> CVContext;
▲ Show 20 Lines • Show All 287 Lines • ▼ Show 20 Linesprivate:
// These are sections that are created as mergeable e.g. .debug_str. We need // These are sections that are created as mergeable e.g. .debug_str. We need
// to avoid assigning non-mergeable symbols to these sections. It is used // to avoid assigning non-mergeable symbols to these sections. It is used
// to prevent non-mergeable symbols being explicitly assigned to mergeable // to prevent non-mergeable symbols being explicitly assigned to mergeable
// sections (e.g. via _attribute_((section("myname")))). // sections (e.g. via _attribute_((section("myname")))).
DenseSet<StringRef> ELFSeenGenericMergeableSections; DenseSet<StringRef> ELFSeenGenericMergeableSections;
public: public:
explicit MCContext(const Triple &TheTriple, const MCAsmInfo *MAI, explicit MCContext(const Triple &TheTriple, const MCAsmInfo *MAI,
const MCRegisterInfo *MRI, const MCSubtargetInfo *MSTI, const MCRegisterInfo *MCRI, const MCSubtargetInfo *MSTI,
const SourceMgr *Mgr = nullptr, const SourceMgr *Mgr = nullptr,
MCTargetOptions const *TargetOpts = nullptr, MCTargetOptions const *TargetOpts = nullptr,
bool DoAutoReset = true, bool DoAutoReset = true,
StringRef Swift5ReflSegmentName = {}); StringRef Swift5ReflSegmentName = {});
MCContext(const MCContext &) = delete; MCContext(const MCContext &) = delete;
MCContext &operator=(const MCContext &) = delete; MCContext &operator=(const MCContext &) = delete;
~MCContext(); ~MCContext();
Show All 11 Linespublic:
void setDiagnosticHandler(DiagHandlerTy DiagHandler) { void setDiagnosticHandler(DiagHandlerTy DiagHandler) {
this->DiagHandler = DiagHandler; this->DiagHandler = DiagHandler;
} }
void setObjectFileInfo(const MCObjectFileInfo *Mofi) { MOFI = Mofi; } void setObjectFileInfo(const MCObjectFileInfo *Mofi) { MOFI = Mofi; }
const MCAsmInfo *getAsmInfo() const { return MAI; } const MCAsmInfo *getAsmInfo() const { return MAI; }
const MCRegisterInfo *getRegisterInfo() const { return MRI; } const MCRegisterInfo *getRegisterInfo() const { return MCRI; }
const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; } const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }
const MCSubtargetInfo *getSubtargetInfo() const { return MSTI; } const MCSubtargetInfo *getSubtargetInfo() const { return MSTI; }
CodeViewContext &getCVContext(); CodeViewContext &getCVContext();
void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; } void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; }
▲ Show 20 Lines • Show All 485 Lines • Show Last 20 Lines

llvm/include/llvm/MC/MCInstPrinter.h

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
class MCInstPrinter { class MCInstPrinter {
protected: protected:
/// A stream that comments can be emitted to if desired. Each comment /// A stream that comments can be emitted to if desired. Each comment
/// must end with a newline. This will be null if verbose assembly emission /// must end with a newline. This will be null if verbose assembly emission
/// is disabled. /// is disabled.
raw_ostream *CommentStream = nullptr; raw_ostream *CommentStream = nullptr;
const MCAsmInfo &MAI; const MCAsmInfo &MAI;
const MCInstrInfo &MII; const MCInstrInfo &MII;
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const MCInstrAnalysis *MIA = nullptr; const MCInstrAnalysis *MIA = nullptr;
/// True if we are printing marked up assembly. /// True if we are printing marked up assembly.
bool UseMarkup = false; bool UseMarkup = false;
/// True if we prefer aliases (e.g. nop) to raw mnemonics. /// True if we prefer aliases (e.g. nop) to raw mnemonics.
bool PrintAliases = true; bool PrintAliases = true;
Show All 15 Linesprotected:
void printAnnotation(raw_ostream &OS, StringRef Annot); void printAnnotation(raw_ostream &OS, StringRef Annot);
/// Helper for matching MCInsts to alias patterns when printing instructions. /// Helper for matching MCInsts to alias patterns when printing instructions.
const char *matchAliasPatterns(const MCInst *MI, const MCSubtargetInfo *STI, const char *matchAliasPatterns(const MCInst *MI, const MCSubtargetInfo *STI,
const AliasMatchingData &M); const AliasMatchingData &M);
public: public:
MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
const MCRegisterInfo &mri) : MAI(mai), MII(mii), MRI(mri) {} const MCRegisterInfo &mri)
: MAI(mai), MII(mii), MCRI(mri) {}
virtual ~MCInstPrinter(); virtual ~MCInstPrinter();
/// Customize the printer according to a command line option. /// Customize the printer according to a command line option.
/// @return true if the option is recognized and applied. /// @return true if the option is recognized and applied.
virtual bool applyTargetSpecificCLOption(StringRef Opt) { return false; } virtual bool applyTargetSpecificCLOption(StringRef Opt) { return false; }
/// Specify a stream to emit comments to. /// Specify a stream to emit comments to.
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/include/llvm/MC/MCInstrAnalysis.h

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linespublic:
/// The first bits in the APint are related to explicit writes. The remaining /// The first bits in the APint are related to explicit writes. The remaining
/// bits are related to implicit writes. The sequence of writes follows the /// bits are related to implicit writes. The sequence of writes follows the
/// machine operand sequence. For implicit writes, the sequence is defined by /// machine operand sequence. For implicit writes, the sequence is defined by
/// the MCInstrDesc. /// the MCInstrDesc.
/// ///
/// The assumption is that the bit-width of the APInt is correctly set by /// The assumption is that the bit-width of the APInt is correctly set by
/// the caller. The default implementation conservatively assumes that none of /// the caller. The default implementation conservatively assumes that none of
/// the writes clears the upper portion of a super-register. /// the writes clears the upper portion of a super-register.
virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI, virtual bool clearsSuperRegisters(const MCRegisterInfo &MCRI,
const MCInst &Inst, const MCInst &Inst, APInt &Writes) const;
APInt &Writes) const;
/// Returns true if MI is a dependency breaking zero-idiom for the given /// Returns true if MI is a dependency breaking zero-idiom for the given
/// subtarget. /// subtarget.
/// ///
/// Mask is used to identify input operands that have their dependency /// Mask is used to identify input operands that have their dependency
/// broken. Each bit of the mask is associated with a specific input operand. /// broken. Each bit of the mask is associated with a specific input operand.
/// Bits associated with explicit input operands are laid out first in the /// Bits associated with explicit input operands are laid out first in the
/// mask; implicit operands come after explicit operands. /// mask; implicit operands come after explicit operands.
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/include/llvm/MC/MCInstrDesc.h

Show First 20 Lines • Show All 612 Lines • ▼ Show 20 Lines if (const MCPhysReg *ImpUses = getImplicitUses())
if (*ImpUses == Reg) if (*ImpUses == Reg)
return true; return true;
return false; return false;
} }
/// Return true if this instruction implicitly /// Return true if this instruction implicitly
/// defines the specified physical register. /// defines the specified physical register.
bool hasImplicitDefOfPhysReg(unsigned Reg, bool hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI = nullptr) const; const MCRegisterInfo *MCRI = nullptr) const;
/// Return the scheduling class for this instruction. The /// Return the scheduling class for this instruction. The
/// scheduling class is an index into the InstrItineraryData table. This /// scheduling class is an index into the InstrItineraryData table. This
/// returns zero if there is no known scheduling information for the /// returns zero if there is no known scheduling information for the
/// instruction. /// instruction.
unsigned getSchedClass() const { return SchedClass; } unsigned getSchedClass() const { return SchedClass; }
/// Return the number of bytes in the encoding of this instruction, /// Return the number of bytes in the encoding of this instruction,
Show All 24 Lines

llvm/include/llvm/MC/TargetRegistry.h

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
/// will be zero initialized), and pass that instance to the TargetRegistry as /// will be zero initialized), and pass that instance to the TargetRegistry as
/// part of their initialization. /// part of their initialization.
class Target { class Target {
public: public:
friend struct TargetRegistry; friend struct TargetRegistry;
using ArchMatchFnTy = bool (*)(Triple::ArchType Arch); using ArchMatchFnTy = bool (*)(Triple::ArchType Arch);
using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI, using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options); const MCTargetOptions &Options);
using MCObjectFileInfoCtorFnTy = MCObjectFileInfo *(*)(MCContext &Ctx, using MCObjectFileInfoCtorFnTy = MCObjectFileInfo *(*)(MCContext &Ctx,
bool PIC, bool PIC,
bool LargeCodeModel); bool LargeCodeModel);
using MCInstrInfoCtorFnTy = MCInstrInfo *(*)(); using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info); using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT); using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT, using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
StringRef CPU, StringRef CPU,
StringRef Features); StringRef Features);
using TargetMachineCtorTy = TargetMachine using TargetMachineCtorTy = TargetMachine
*(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features, *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
const TargetOptions &Options, std::optional<Reloc::Model> RM, const TargetOptions &Options, std::optional<Reloc::Model> RM,
std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT); std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
// If it weren't for layering issues (this header is in llvm/Support, but // If it weren't for layering issues (this header is in llvm/Support, but
// depends on MC?) this should take the Streamer by value rather than rvalue // depends on MC?) this should take the Streamer by value rather than rvalue
// reference. // reference.
using AsmPrinterCtorTy = AsmPrinter *(*)( using AsmPrinterCtorTy = AsmPrinter *(*)(
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer); TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T, using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
using MCAsmParserCtorTy = MCTargetAsmParser *(*)( using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
const MCTargetOptions &Options); const MCTargetOptions &Options);
using MCDisassemblerCtorTy = MCDisassembler *(*)(const Target &T, using MCDisassemblerCtorTy = MCDisassembler *(*)(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCContext &Ctx); MCContext &Ctx);
using MCInstPrinterCtorTy = MCInstPrinter *(*)(const Triple &T, using MCInstPrinterCtorTy = MCInstPrinter *(*)(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II, using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II,
MCContext &Ctx); MCContext &Ctx);
using ELFStreamerCtorTy = using ELFStreamerCtorTy =
MCStreamer *(*)(const Triple &T, MCContext &Ctx, MCStreamer *(*)(const Triple &T, MCContext &Ctx,
std::unique_ptr<MCAsmBackend> &&TAB, std::unique_ptr<MCAsmBackend> &&TAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll); std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
using MachOStreamerCtorTy = using MachOStreamerCtorTy =
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Linespublic:
/// createMCAsmInfo - Create a MCAsmInfo implementation for the specified /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
/// target triple. /// target triple.
/// ///
/// \param TheTriple This argument is used to determine the target machine /// \param TheTriple This argument is used to determine the target machine
/// feature set; it should always be provided. Generally this should be /// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the /// either the target triple from the module, or the target triple of the
/// host if that does not exist. /// host if that does not exist.
MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MCRI, StringRef TheTriple,
const MCTargetOptions &Options) const { const MCTargetOptions &Options) const {
if (!MCAsmInfoCtorFn) if (!MCAsmInfoCtorFn)
return nullptr; return nullptr;
return MCAsmInfoCtorFn(MRI, Triple(TheTriple), Options); return MCAsmInfoCtorFn(MCRI, Triple(TheTriple), Options);
} }
/// Create a MCObjectFileInfo implementation for the specified target /// Create a MCObjectFileInfo implementation for the specified target
/// triple. /// triple.
/// ///
MCObjectFileInfo *createMCObjectFileInfo(MCContext &Ctx, bool PIC, MCObjectFileInfo *createMCObjectFileInfo(MCContext &Ctx, bool PIC,
bool LargeCodeModel = false) const { bool LargeCodeModel = false) const {
if (!MCObjectFileInfoCtorFn) { if (!MCObjectFileInfoCtorFn) {
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines TargetMachine *createTargetMachine(
if (!TargetMachineCtorFn) if (!TargetMachineCtorFn)
return nullptr; return nullptr;
return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM, return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
CM, OL, JIT); CM, OL, JIT);
} }
/// createMCAsmBackend - Create a target specific assembly parser. /// createMCAsmBackend - Create a target specific assembly parser.
MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI, MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) const { const MCTargetOptions &Options) const {
if (!MCAsmBackendCtorFn) if (!MCAsmBackendCtorFn)
return nullptr; return nullptr;
return MCAsmBackendCtorFn(*this, STI, MRI, Options); return MCAsmBackendCtorFn(*this, STI, MCRI, Options);
} }
/// createMCAsmParser - Create a target specific assembly parser. /// createMCAsmParser - Create a target specific assembly parser.
/// ///
/// \param Parser The target independent parser implementation to use for /// \param Parser The target independent parser implementation to use for
/// parsing and lexing. /// parsing and lexing.
MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI, MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
MCAsmParser &Parser, MCAsmParser &Parser,
Show All 18 Lines MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
if (!MCDisassemblerCtorFn) if (!MCDisassemblerCtorFn)
return nullptr; return nullptr;
return MCDisassemblerCtorFn(*this, STI, Ctx); return MCDisassemblerCtorFn(*this, STI, Ctx);
} }
MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const { const MCRegisterInfo &MCRI) const {
if (!MCInstPrinterCtorFn) if (!MCInstPrinterCtorFn)
return nullptr; return nullptr;
return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI); return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MCRI);
} }
/// createMCCodeEmitter - Create a target specific code emitter. /// createMCCodeEmitter - Create a target specific code emitter.
MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II, MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
MCContext &Ctx) const { MCContext &Ctx) const {
if (!MCCodeEmitterCtorFn) if (!MCCodeEmitterCtorFn)
return nullptr; return nullptr;
return MCCodeEmitterCtorFn(II, Ctx); return MCCodeEmitterCtorFn(II, Ctx);
▲ Show 20 Lines • Show All 609 Lines • ▼ Show 20 Lines
/// RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget); /// RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
/// } /// }
template <class MCAsmInfoImpl> struct RegisterMCAsmInfo { template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
RegisterMCAsmInfo(Target &T) { RegisterMCAsmInfo(Target &T) {
TargetRegistry::RegisterMCAsmInfo(T, &Allocator); TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
} }
private: private:
static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/, const Triple &TT, static MCAsmInfo *Allocator(const MCRegisterInfo & /*MCRI*/, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new MCAsmInfoImpl(TT, Options); return new MCAsmInfoImpl(TT, Options);
} }
}; };
/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
/// implementation. This invokes the specified function to do the /// implementation. This invokes the specified function to do the
/// construction. Usage: /// construction. Usage:
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/// } /// }
template <class MCAsmBackendImpl> struct RegisterMCAsmBackend { template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
RegisterMCAsmBackend(Target &T) { RegisterMCAsmBackend(Target &T) {
TargetRegistry::RegisterMCAsmBackend(T, &Allocator); TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
} }
private: private:
static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI, static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new MCAsmBackendImpl(T, STI, MRI); return new MCAsmBackendImpl(T, STI, MCRI);
} }
}; };
/// RegisterMCAsmParser - Helper template for registering a target specific /// RegisterMCAsmParser - Helper template for registering a target specific
/// assembly parser, for use in the target machine initialization /// assembly parser, for use in the target machine initialization
/// function. Usage: /// function. Usage:
/// ///
/// extern "C" void LLVMInitializeFooMCAsmParser() { /// extern "C" void LLVMInitializeFooMCAsmParser() {
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llvm/include/llvm/MCA/Context.h

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesstruct PipelineOptions {
unsigned LoadQueueSize; unsigned LoadQueueSize;
unsigned StoreQueueSize; unsigned StoreQueueSize;
bool AssumeNoAlias; bool AssumeNoAlias;
bool EnableBottleneckAnalysis; bool EnableBottleneckAnalysis;
}; };
class Context { class Context {
SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware; SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
public: public:
Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {} Context(const MCRegisterInfo &R, const MCSubtargetInfo &S)
: MCRI(R), STI(S) {}
Context(const Context &C) = delete; Context(const Context &C) = delete;
Context &operator=(const Context &C) = delete; Context &operator=(const Context &C) = delete;
const MCRegisterInfo &getMCRegisterInfo() const { return MRI; } const MCRegisterInfo &getMCRegisterInfo() const { return MCRI; }
const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; } const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
void addHardwareUnit(std::unique_ptr<HardwareUnit> H) { void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
Hardware.push_back(std::move(H)); Hardware.push_back(std::move(H));
} }
/// Construct a basic pipeline for simulating an out-of-order pipeline. /// Construct a basic pipeline for simulating an out-of-order pipeline.
/// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages. /// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
Show All 14 Lines

llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
#ifndef NDEBUG #ifndef NDEBUG
void dump() const; void dump() const;
#endif #endif
}; };
/// Manages hardware register files, and tracks register definitions for /// Manages hardware register files, and tracks register definitions for
/// register renaming purposes. /// register renaming purposes.
class RegisterFile : public HardwareUnit { class RegisterFile : public HardwareUnit {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
// class RegisterMappingTracker is a physical register file (PRF) descriptor. // class RegisterMappingTracker is a physical register file (PRF) descriptor.
// There is one RegisterMappingTracker for every PRF definition in the // There is one RegisterMappingTracker for every PRF definition in the
// scheduling model. // scheduling model.
// //
// An instance of RegisterMappingTracker tracks the number of physical // An instance of RegisterMappingTracker tracks the number of physical
// registers available for renaming. It also tracks the number of register // registers available for renaming. It also tracks the number of register
// moves eliminated per cycle. // moves eliminated per cycle.
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llvm/include/llvm/MCA/InstrBuilder.h

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
/// ///
/// This class is used by the tool to construct Instructions and instruction /// This class is used by the tool to construct Instructions and instruction
/// descriptors (i.e. InstrDesc objects). /// descriptors (i.e. InstrDesc objects).
/// Information from the machine scheduling model is used to identify processor /// Information from the machine scheduling model is used to identify processor
/// resources that are consumed by an instruction. /// resources that are consumed by an instruction.
class InstrBuilder { class InstrBuilder {
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
const MCInstrInfo &MCII; const MCInstrInfo &MCII;
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const MCInstrAnalysis *MCIA; const MCInstrAnalysis *MCIA;
const InstrumentManager &IM; const InstrumentManager &IM;
SmallVector<uint64_t, 8> ProcResourceMasks; SmallVector<uint64_t, 8> ProcResourceMasks;
// Key is the MCI.Opcode and SchedClassID the describe the value InstrDesc // Key is the MCI.Opcode and SchedClassID the describe the value InstrDesc
DenseMap<std::pair<unsigned short, unsigned>, DenseMap<std::pair<unsigned short, unsigned>,
std::unique_ptr<const InstrDesc>> std::unique_ptr<const InstrDesc>>
Descriptors; Descriptors;
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llvm/include/llvm/MCA/Stages/DispatchStage.h

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Linesclass DispatchStage final : public Stage {
bool canDispatch(const InstRef &IR) const; bool canDispatch(const InstRef &IR) const;
Error dispatch(InstRef IR); Error dispatch(InstRef IR);
void notifyInstructionDispatched(const InstRef &IR, void notifyInstructionDispatched(const InstRef &IR,
ArrayRef<unsigned> UsedPhysRegs, ArrayRef<unsigned> UsedPhysRegs,
unsigned uOps) const; unsigned uOps) const;
public: public:
DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MCRI,
unsigned MaxDispatchWidth, RetireControlUnit &R, unsigned MaxDispatchWidth, RetireControlUnit &R,
RegisterFile &F); RegisterFile &F);
bool isAvailable(const InstRef &IR) const override; bool isAvailable(const InstRef &IR) const override;
// The dispatch logic internally doesn't buffer instructions. So there is // The dispatch logic internally doesn't buffer instructions. So there is
// never work to do at the beginning of every cycle. // never work to do at the beginning of every cycle.
bool hasWorkToComplete() const override { return false; } bool hasWorkToComplete() const override { return false; }
Show All 11 Lines

llvm/include/llvm/Target/TargetMachine.h

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Linesprotected: // Can only create subclasses.
std::string TargetFS; std::string TargetFS;
Reloc::Model RM = Reloc::Static; Reloc::Model RM = Reloc::Static;
CodeModel::Model CMModel = CodeModel::Small; CodeModel::Model CMModel = CodeModel::Small;
CodeGenOpt::Level OptLevel = CodeGenOpt::Default; CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
/// Contains target specific asm information. /// Contains target specific asm information.
std::unique_ptr<const MCAsmInfo> AsmInfo; std::unique_ptr<const MCAsmInfo> AsmInfo;
std::unique_ptr<const MCRegisterInfo> MRI; std::unique_ptr<const MCRegisterInfo> MCRI;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<const MCSubtargetInfo> STI; std::unique_ptr<const MCSubtargetInfo> STI;
unsigned RequireStructuredCFG : 1; unsigned RequireStructuredCFG : 1;
unsigned O0WantsFastISel : 1; unsigned O0WantsFastISel : 1;
// PGO related tunables. // PGO related tunables.
std::optional<PGOOptions> PGOOption; std::optional<PGOOptions> PGOOption;
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Linespublic:
/// Reset the target options based on the function's attributes. /// Reset the target options based on the function's attributes.
// FIXME: Remove TargetOptions that affect per-function code generation // FIXME: Remove TargetOptions that affect per-function code generation
// from TargetMachine. // from TargetMachine.
void resetTargetOptions(const Function &F) const; void resetTargetOptions(const Function &F) const;
/// Return target specific asm information. /// Return target specific asm information.
const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); } const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); }
const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); } const MCRegisterInfo *getMCRegisterInfo() const { return MCRI.get(); }
const MCInstrInfo *getMCInstrInfo() const { return MII.get(); } const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); } const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
/// If intrinsic information is available, return it. If not, return null. /// If intrinsic information is available, return it. If not, return null.
virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
return nullptr; return nullptr;
} }
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llvm/lib/CodeGen/LLVMTargetMachine.cpp

Show All 32 Lines
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
using namespace llvm; using namespace llvm;
static cl::opt<bool> static cl::opt<bool>
EnableTrapUnreachable("trap-unreachable", cl::Hidden, EnableTrapUnreachable("trap-unreachable", cl::Hidden,
cl::desc("Enable generating trap for unreachable")); cl::desc("Enable generating trap for unreachable"));
void LLVMTargetMachine::initAsmInfo() { void LLVMTargetMachine::initAsmInfo() {
MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); MCRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str()));
assert(MRI && "Unable to create reg info"); assert(MCRI && "Unable to create reg info");
MII.reset(TheTarget.createMCInstrInfo()); MII.reset(TheTarget.createMCInstrInfo());
assert(MII && "Unable to create instruction info"); assert(MII && "Unable to create instruction info");
// FIXME: Having an MCSubtargetInfo on the target machine is a hack due // FIXME: Having an MCSubtargetInfo on the target machine is a hack due
// to some backends having subtarget feature dependent module level // to some backends having subtarget feature dependent module level
// code generation. This is similar to the hack in the AsmPrinter for // code generation. This is similar to the hack in the AsmPrinter for
// module level assembly etc. // module level assembly etc.
STI.reset(TheTarget.createMCSubtargetInfo( STI.reset(TheTarget.createMCSubtargetInfo(
getTargetTriple().str(), getTargetCPU(), getTargetFeatureString())); getTargetTriple().str(), getTargetCPU(), getTargetFeatureString()));
assert(STI && "Unable to create subtarget info"); assert(STI && "Unable to create subtarget info");
MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo( MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(
*MRI, getTargetTriple().str(), Options.MCOptions); *MCRI, getTargetTriple().str(), Options.MCOptions);
// TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
// and if the old one gets included then MCAsmInfo will be NULL and // and if the old one gets included then MCAsmInfo will be NULL and
// we'll crash later. // we'll crash later.
// Provide the user with a useful error message about what's wrong. // Provide the user with a useful error message about what's wrong.
assert(TmpAsmInfo && "MCAsmInfo not initialized. " assert(TmpAsmInfo && "MCAsmInfo not initialized. "
"Make sure you include the correct TargetSelect.h" "Make sure you include the correct TargetSelect.h"
"and that InitializeAllTargetMCs() is being invoked!"); "and that InitializeAllTargetMCs() is being invoked!");
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer( Expected<std::unique_ptr<MCStreamer>> LLVMTargetMachine::createMCStreamer(
raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
MCContext &Context) { MCContext &Context) {
if (Options.MCOptions.MCSaveTempLabels) if (Options.MCOptions.MCSaveTempLabels)
Context.setAllowTemporaryLabels(false); Context.setAllowTemporaryLabels(false);
const MCSubtargetInfo &STI = *getMCSubtargetInfo(); const MCSubtargetInfo &STI = *getMCSubtargetInfo();
const MCAsmInfo &MAI = *getMCAsmInfo(); const MCAsmInfo &MAI = *getMCAsmInfo();
const MCRegisterInfo &MRI = *getMCRegisterInfo(); const MCRegisterInfo &MCRI = *getMCRegisterInfo();
const MCInstrInfo &MII = *getMCInstrInfo(); const MCInstrInfo &MII = *getMCInstrInfo();
std::unique_ptr<MCStreamer> AsmStreamer; std::unique_ptr<MCStreamer> AsmStreamer;
switch (FileType) { switch (FileType) {
case CGFT_AssemblyFile: { case CGFT_AssemblyFile: {
MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter( MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter(
getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MCRI);
// Create a code emitter if asked to show the encoding. // Create a code emitter if asked to show the encoding.
std::unique_ptr<MCCodeEmitter> MCE; std::unique_ptr<MCCodeEmitter> MCE;
if (Options.MCOptions.ShowMCEncoding) if (Options.MCOptions.ShowMCEncoding)
MCE.reset(getTarget().createMCCodeEmitter(MII, Context)); MCE.reset(getTarget().createMCCodeEmitter(MII, Context));
bool UseDwarfDirectory = false; bool UseDwarfDirectory = false;
switch (Options.MCOptions.MCUseDwarfDirectory) { switch (Options.MCOptions.MCUseDwarfDirectory) {
case MCTargetOptions::DisableDwarfDirectory: case MCTargetOptions::DisableDwarfDirectory:
UseDwarfDirectory = false; UseDwarfDirectory = false;
break; break;
case MCTargetOptions::EnableDwarfDirectory: case MCTargetOptions::EnableDwarfDirectory:
UseDwarfDirectory = true; UseDwarfDirectory = true;
break; break;
case MCTargetOptions::DefaultDwarfDirectory: case MCTargetOptions::DefaultDwarfDirectory:
UseDwarfDirectory = MAI.enableDwarfFileDirectoryDefault(); UseDwarfDirectory = MAI.enableDwarfFileDirectoryDefault();
break; break;
} }
std::unique_ptr<MCAsmBackend> MAB( std::unique_ptr<MCAsmBackend> MAB(
getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions)); getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions));
auto FOut = std::make_unique<formatted_raw_ostream>(Out); auto FOut = std::make_unique<formatted_raw_ostream>(Out);
MCStreamer *S = getTarget().createAsmStreamer( MCStreamer *S = getTarget().createAsmStreamer(
Context, std::move(FOut), Options.MCOptions.AsmVerbose, Context, std::move(FOut), Options.MCOptions.AsmVerbose,
UseDwarfDirectory, InstPrinter, std::move(MCE), std::move(MAB), UseDwarfDirectory, InstPrinter, std::move(MCE), std::move(MAB),
Options.MCOptions.ShowMCInst); Options.MCOptions.ShowMCInst);
AsmStreamer.reset(S); AsmStreamer.reset(S);
break; break;
} }
case CGFT_ObjectFile: { case CGFT_ObjectFile: {
// Create the code emitter for the target if it exists. If not, .o file // Create the code emitter for the target if it exists. If not, .o file
// emission fails. // emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, Context); MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, Context);
if (!MCE) if (!MCE)
return make_error<StringError>("createMCCodeEmitter failed", return make_error<StringError>("createMCCodeEmitter failed",
inconvertibleErrorCode()); inconvertibleErrorCode());
MCAsmBackend *MAB = MCAsmBackend *MAB =
getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions); getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions);
if (!MAB) if (!MAB)
return make_error<StringError>("createMCAsmBackend failed", return make_error<StringError>("createMCAsmBackend failed",
inconvertibleErrorCode()); inconvertibleErrorCode());
Triple T(getTargetTriple().str()); Triple T(getTargetTriple().str());
AsmStreamer.reset(getTarget().createMCObjectStreamer( AsmStreamer.reset(getTarget().createMCObjectStreamer(
T, Context, std::unique_ptr<MCAsmBackend>(MAB), T, Context, std::unique_ptr<MCAsmBackend>(MAB),
DwoOut ? MAB->createDwoObjectWriter(Out, *DwoOut) DwoOut ? MAB->createDwoObjectWriter(Out, *DwoOut)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Linesbool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
// DWARF unwind info for the JIT. // DWARF unwind info for the JIT.
Options.MCOptions.EmitDwarfUnwind = EmitDwarfUnwindType::Always; Options.MCOptions.EmitDwarfUnwind = EmitDwarfUnwindType::Always;
if (Options.MCOptions.MCSaveTempLabels) if (Options.MCOptions.MCSaveTempLabels)
Ctx->setAllowTemporaryLabels(false); Ctx->setAllowTemporaryLabels(false);
// Create the code emitter for the target if it exists. If not, .o file // Create the code emitter for the target if it exists. If not, .o file
// emission fails. // emission fails.
const MCSubtargetInfo &STI = *getMCSubtargetInfo(); const MCSubtargetInfo &STI = *getMCSubtargetInfo();
const MCRegisterInfo &MRI = *getMCRegisterInfo(); const MCRegisterInfo &MCRI = *getMCRegisterInfo();
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getMCInstrInfo(), *Ctx); MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getMCInstrInfo(), *Ctx);
MCAsmBackend *MAB = MCAsmBackend *MAB =
getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions); getTarget().createMCAsmBackend(STI, MCRI, Options.MCOptions);
if (!MCE || !MAB) if (!MCE || !MAB)
return true; return true;
const Triple &T = getTargetTriple(); const Triple &T = getTargetTriple();
std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer( std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), MAB->createObjectWriter(Out), T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), MAB->createObjectWriter(Out),
std::unique_ptr<MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll, std::unique_ptr<MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll,
Options.MCOptions.MCIncrementalLinkerCompatible, Options.MCOptions.MCIncrementalLinkerCompatible,
Show All 13 Lines

llvm/lib/DWARFLinker/DWARFStreamer.cpp

Show All 36 Linesbool DwarfStreamer::init(Triple TheTriple,
// Get the target. // Get the target.
const Target *TheTarget = const Target *TheTarget =
TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr); TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr);
if (!TheTarget) if (!TheTarget)
return error(ErrorStr, Context), false; return error(ErrorStr, Context), false;
TripleName = TheTriple.getTriple(); TripleName = TheTriple.getTriple();
// Create all the MC Objects. // Create all the MC Objects.
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
return error(Twine("no register info for target ") + TripleName, Context), return error(Twine("no register info for target ") + TripleName, Context),
false; false;
MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) if (!MAI)
return error("no asm info for target " + TripleName, Context), false; return error("no asm info for target " + TripleName, Context), false;
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI) if (!MSTI)
return error("no subtarget info for target " + TripleName, Context), false; return error("no subtarget info for target " + TripleName, Context), false;
MC.reset(new MCContext(TheTriple, MAI.get(), MRI.get(), MSTI.get(), nullptr, MC.reset(new MCContext(TheTriple, MAI.get(), MCRI.get(), MSTI.get(), nullptr,
nullptr, true, Swift5ReflectionSegmentName)); nullptr, true, Swift5ReflectionSegmentName));
MOFI.reset(TheTarget->createMCObjectFileInfo(*MC, /*PIC=*/false, false)); MOFI.reset(TheTarget->createMCObjectFileInfo(*MC, /*PIC=*/false, false));
MC->setObjectFileInfo(MOFI.get()); MC->setObjectFileInfo(MOFI.get());
MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions); MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, MCOptions);
if (!MAB) if (!MAB)
return error("no asm backend for target " + TripleName, Context), false; return error("no asm backend for target " + TripleName, Context), false;
MII.reset(TheTarget->createMCInstrInfo()); MII.reset(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
return error("no instr info info for target " + TripleName, Context), false; return error("no instr info info for target " + TripleName, Context), false;
MCE = TheTarget->createMCCodeEmitter(*MII, *MC); MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
if (!MCE) if (!MCE)
return error("no code emitter for target " + TripleName, Context), false; return error("no code emitter for target " + TripleName, Context), false;
switch (OutFileType) { switch (OutFileType) {
case OutputFileType::Assembly: { case OutputFileType::Assembly: {
MIP = TheTarget->createMCInstPrinter(TheTriple, MAI->getAssemblerDialect(), MIP = TheTarget->createMCInstPrinter(TheTriple, MAI->getAssemblerDialect(),
*MAI, *MII, *MRI); *MAI, *MII, *MCRI);
MS = TheTarget->createAsmStreamer( MS = TheTarget->createAsmStreamer(
*MC, std::make_unique<formatted_raw_ostream>(OutFile), true, true, MIP, *MC, std::make_unique<formatted_raw_ostream>(OutFile), true, true, MIP,
std::unique_ptr<MCCodeEmitter>(MCE), std::unique_ptr<MCAsmBackend>(MAB), std::unique_ptr<MCCodeEmitter>(MCE), std::unique_ptr<MCAsmBackend>(MAB),
true); true);
break; break;
} }
case OutputFileType::Object: { case OutputFileType::Object: {
MS = TheTarget->createMCObjectStreamer( MS = TheTarget->createMCObjectStreamer(
▲ Show 20 Lines • Show All 920 Lines • Show Last 20 Lines

llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 LinesError LVBinaryReader::loadGenericTargetInfo(StringRef TheTriple,
if (!TheTarget) if (!TheTarget)
return createStringError(errc::invalid_argument, TargetLookupError.c_str()); return createStringError(errc::invalid_argument, TargetLookupError.c_str());
// Register information. // Register information.
MCRegisterInfo *RegisterInfo = TheTarget->createMCRegInfo(TheTriple); MCRegisterInfo *RegisterInfo = TheTarget->createMCRegInfo(TheTriple);
if (!RegisterInfo) if (!RegisterInfo)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no register info for target " + TheTriple); "no register info for target " + TheTriple);
MRI.reset(RegisterInfo); MCRI.reset(RegisterInfo);
// Assembler properties and features. // Assembler properties and features.
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
MCAsmInfo *AsmInfo(TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); MCAsmInfo *AsmInfo(TheTarget->createMCAsmInfo(*MCRI, TheTriple, MCOptions));
if (!AsmInfo) if (!AsmInfo)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no assembly info for target " + TheTriple); "no assembly info for target " + TheTriple);
MAI.reset(AsmInfo); MAI.reset(AsmInfo);
// Target subtargets. // Target subtargets.
StringRef CPU; StringRef CPU;
MCSubtargetInfo *SubtargetInfo( MCSubtargetInfo *SubtargetInfo(
TheTarget->createMCSubtargetInfo(TheTriple, CPU, TheFeatures)); TheTarget->createMCSubtargetInfo(TheTriple, CPU, TheFeatures));
if (!SubtargetInfo) if (!SubtargetInfo)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no subtarget info for target " + TheTriple); "no subtarget info for target " + TheTriple);
STI.reset(SubtargetInfo); STI.reset(SubtargetInfo);
// Instructions Info. // Instructions Info.
MCInstrInfo *InstructionInfo(TheTarget->createMCInstrInfo()); MCInstrInfo *InstructionInfo(TheTarget->createMCInstrInfo());
if (!InstructionInfo) if (!InstructionInfo)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no instruction info for target " + TheTriple); "no instruction info for target " + TheTriple);
MII.reset(InstructionInfo); MII.reset(InstructionInfo);
MC = std::make_unique<MCContext>(Triple(TheTriple), MAI.get(), MRI.get(), MC = std::make_unique<MCContext>(Triple(TheTriple), MAI.get(), MCRI.get(),
STI.get()); STI.get());
// Assembler. // Assembler.
MCDisassembler *DisAsm(TheTarget->createMCDisassembler(*STI, *MC)); MCDisassembler *DisAsm(TheTarget->createMCDisassembler(*STI, *MC));
if (!DisAsm) if (!DisAsm)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no disassembler for target " + TheTriple); "no disassembler for target " + TheTriple);
MD.reset(DisAsm); MD.reset(DisAsm);
MCInstPrinter *InstructionPrinter(TheTarget->createMCInstPrinter( MCInstPrinter *InstructionPrinter(TheTarget->createMCInstPrinter(
Triple(TheTriple), AsmInfo->getAssemblerDialect(), *MAI, *MII, *MRI)); Triple(TheTriple), AsmInfo->getAssemblerDialect(), *MAI, *MII, *MCRI));
if (!InstructionPrinter) if (!InstructionPrinter)
return createStringError(errc::invalid_argument, return createStringError(errc::invalid_argument,
"no target assembly language printer for target " + "no target assembly language printer for target " +
TheTriple); TheTriple);
MIP.reset(InstructionPrinter); MIP.reset(InstructionPrinter);
InstructionPrinter->setPrintImmHex(true); InstructionPrinter->setPrintImmHex(true);
return Error::success(); return Error::success();
▲ Show 20 Lines • Show All 570 Lines • Show Last 20 Lines

llvm/lib/DebugInfo/LogicalView/Readers/LVELFReader.cpp

Show First 20 Lines • Show All 764 Lines • ▼ Show 20 Linesstd::string LVELFReader::getRegisterName(LVSmall Opcode, uint64_t Operands[2]) {
// item, with no access to the underlying DWARF data used by LLVM. // item, with no access to the underlying DWARF data used by LLVM.
// We do not support DW_OP_regval_type here. // We do not support DW_OP_regval_type here.
if (Opcode == dwarf::DW_OP_regval_type) if (Opcode == dwarf::DW_OP_regval_type)
return {}; return {};
std::string string; std::string string;
raw_string_ostream Stream(string); raw_string_ostream Stream(string);
DIDumpOptions DumpOpts; DIDumpOptions DumpOpts;
auto *MCRegInfo = MRI.get(); auto *MCRegInfo = MCRI.get();
auto GetRegName = [&MCRegInfo](uint64_t DwarfRegNum, bool IsEH) -> StringRef { auto GetRegName = [&MCRegInfo](uint64_t DwarfRegNum, bool IsEH) -> StringRef {
if (!MCRegInfo) if (!MCRegInfo)
return {}; return {};
if (std::optional<unsigned> LLVMRegNum = if (std::optional<unsigned> LLVMRegNum =
MCRegInfo->getLLVMRegNum(DwarfRegNum, IsEH)) MCRegInfo->getLLVMRegNum(DwarfRegNum, IsEH))
if (const char *RegName = MCRegInfo->getName(*LLVMRegNum)) if (const char *RegName = MCRegInfo->getName(*LLVMRegNum))
return StringRef(RegName); return StringRef(RegName);
return {}; return {};
▲ Show 20 Lines • Show All 468 Lines • Show Last 20 Lines

llvm/lib/MC/MCAsmStreamer.cpp

Show First 20 Lines • Show All 1,876 Lines • ▼ Show 20 Linesvoid MCAsmStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) {
EmitEOL(); EmitEOL();
} }
void MCAsmStreamer::EmitRegisterName(int64_t Register) { void MCAsmStreamer::EmitRegisterName(int64_t Register) {
if (!MAI->useDwarfRegNumForCFI()) { if (!MAI->useDwarfRegNumForCFI()) {
// User .cfi_* directives can use arbitrary DWARF register numbers, not // User .cfi_* directives can use arbitrary DWARF register numbers, not
// just ones that map to LLVM register numbers and have known names. // just ones that map to LLVM register numbers and have known names.
// Fall back to using the original number directly if no name is known. // Fall back to using the original number directly if no name is known.
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
if (std::optional<unsigned> LLVMRegister = if (std::optional<unsigned> LLVMRegister =
MRI->getLLVMRegNum(Register, true)) { MCRI->getLLVMRegNum(Register, true)) {
InstPrinter->printRegName(OS, *LLVMRegister); InstPrinter->printRegName(OS, *LLVMRegister);
return; return;
} }
} }
OS << Register; OS << Register;
} }
void MCAsmStreamer::emitCFIDefCfa(int64_t Register, int64_t Offset) { void MCAsmStreamer::emitCFIDefCfa(int64_t Register, int64_t Offset) {
▲ Show 20 Lines • Show All 676 Lines • Show Last 20 Lines

llvm/lib/MC/MCContext.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
} }
MCContext::MCContext(const Triple &TheTriple, const MCAsmInfo *mai, MCContext::MCContext(const Triple &TheTriple, const MCAsmInfo *mai,
const MCRegisterInfo *mri, const MCSubtargetInfo *msti, const MCRegisterInfo *mri, const MCSubtargetInfo *msti,
const SourceMgr *mgr, MCTargetOptions const *TargetOpts, const SourceMgr *mgr, MCTargetOptions const *TargetOpts,
bool DoAutoReset, StringRef Swift5ReflSegmentName) bool DoAutoReset, StringRef Swift5ReflSegmentName)
: Swift5ReflectionSegmentName(Swift5ReflSegmentName), TT(TheTriple), : Swift5ReflectionSegmentName(Swift5ReflSegmentName), TT(TheTriple),
SrcMgr(mgr), InlineSrcMgr(nullptr), DiagHandler(defaultDiagHandler), SrcMgr(mgr), InlineSrcMgr(nullptr), DiagHandler(defaultDiagHandler),
MAI(mai), MRI(mri), MSTI(msti), Symbols(Allocator), UsedNames(Allocator), MAI(mai), MCRI(mri), MSTI(msti), Symbols(Allocator), UsedNames(Allocator),
InlineAsmUsedLabelNames(Allocator), InlineAsmUsedLabelNames(Allocator),
CurrentDwarfLoc(0, 0, 0, DWARF2_FLAG_IS_STMT, 0, 0), CurrentDwarfLoc(0, 0, 0, DWARF2_FLAG_IS_STMT, 0, 0),
AutoReset(DoAutoReset), TargetOptions(TargetOpts) { AutoReset(DoAutoReset), TargetOptions(TargetOpts) {
SecureLogFile = TargetOptions ? TargetOptions->AsSecureLogFile : ""; SecureLogFile = TargetOptions ? TargetOptions->AsSecureLogFile : "";
if (SrcMgr && SrcMgr->getNumBuffers()) if (SrcMgr && SrcMgr->getNumBuffers())
MainFileName = std::string(SrcMgr->getMemoryBuffer(SrcMgr->getMainFileID()) MainFileName = std::string(SrcMgr->getMemoryBuffer(SrcMgr->getMainFileID())
->getBufferIdentifier()); ->getBufferIdentifier());
▲ Show 20 Lines • Show All 991 Lines • Show Last 20 Lines

llvm/lib/MC/MCDisassembler/Disassembler.h

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesprivate:
// //
// The LLVM target corresponding to the disassembler. // The LLVM target corresponding to the disassembler.
// FIXME: using std::unique_ptr<const llvm::Target> causes a malloc error // FIXME: using std::unique_ptr<const llvm::Target> causes a malloc error
// when this LLVMDisasmContext is deleted. // when this LLVMDisasmContext is deleted.
const Target *TheTarget; const Target *TheTarget;
// The assembly information for the target architecture. // The assembly information for the target architecture.
std::unique_ptr<const llvm::MCAsmInfo> MAI; std::unique_ptr<const llvm::MCAsmInfo> MAI;
// The register information for the target architecture. // The register information for the target architecture.
std::unique_ptr<const llvm::MCRegisterInfo> MRI; std::unique_ptr<const llvm::MCRegisterInfo> MCRI;
// The subtarget information for the target architecture. // The subtarget information for the target architecture.
std::unique_ptr<const llvm::MCSubtargetInfo> MSI; std::unique_ptr<const llvm::MCSubtargetInfo> MSI;
// The instruction information for the target architecture. // The instruction information for the target architecture.
std::unique_ptr<const llvm::MCInstrInfo> MII; std::unique_ptr<const llvm::MCInstrInfo> MII;
// The assembly context for creating symbols and MCExprs. // The assembly context for creating symbols and MCExprs.
std::unique_ptr<const llvm::MCContext> Ctx; std::unique_ptr<const llvm::MCContext> Ctx;
// The disassembler for the target architecture. // The disassembler for the target architecture.
std::unique_ptr<const llvm::MCDisassembler> DisAsm; std::unique_ptr<const llvm::MCDisassembler> DisAsm;
Show All 9 Linespublic:
SmallString<128> CommentsToEmit; SmallString<128> CommentsToEmit;
raw_svector_ostream CommentStream; raw_svector_ostream CommentStream;
LLVMDisasmContext(std::string TripleName, void *DisInfo, int TagType, LLVMDisasmContext(std::string TripleName, void *DisInfo, int TagType,
LLVMOpInfoCallback GetOpInfo, LLVMOpInfoCallback GetOpInfo,
LLVMSymbolLookupCallback SymbolLookUp, LLVMSymbolLookupCallback SymbolLookUp,
const Target *TheTarget, const Target *TheTarget,
std::unique_ptr<const MCAsmInfo> &&MAI, std::unique_ptr<const MCAsmInfo> &&MAI,
std::unique_ptr<const MCRegisterInfo> &&MRI, std::unique_ptr<const MCRegisterInfo> &&MCRI,
std::unique_ptr<const MCSubtargetInfo> &&MSI, std::unique_ptr<const MCSubtargetInfo> &&MSI,
std::unique_ptr<const MCInstrInfo> &&MII, std::unique_ptr<const MCInstrInfo> &&MII,
std::unique_ptr<const llvm::MCContext> &&Ctx, std::unique_ptr<const llvm::MCContext> &&Ctx,
std::unique_ptr<const MCDisassembler> &&DisAsm, std::unique_ptr<const MCDisassembler> &&DisAsm,
std::unique_ptr<MCInstPrinter> &&IP) std::unique_ptr<MCInstPrinter> &&IP)
: TripleName(std::move(TripleName)), DisInfo(DisInfo), TagType(TagType), : TripleName(std::move(TripleName)), DisInfo(DisInfo), TagType(TagType),
GetOpInfo(GetOpInfo), SymbolLookUp(SymbolLookUp), TheTarget(TheTarget), GetOpInfo(GetOpInfo), SymbolLookUp(SymbolLookUp), TheTarget(TheTarget),
MAI(std::move(MAI)), MRI(std::move(MRI)), MSI(std::move(MSI)), MAI(std::move(MAI)), MCRI(std::move(MCRI)), MSI(std::move(MSI)),
MII(std::move(MII)), Ctx(std::move(Ctx)), DisAsm(std::move(DisAsm)), MII(std::move(MII)), Ctx(std::move(Ctx)), DisAsm(std::move(DisAsm)),
IP(std::move(IP)), Options(0), CommentStream(CommentsToEmit) {} IP(std::move(IP)), Options(0), CommentStream(CommentsToEmit) {}
const std::string &getTripleName() const { return TripleName; } const std::string &getTripleName() const { return TripleName; }
void *getDisInfo() const { return DisInfo; } void *getDisInfo() const { return DisInfo; }
int getTagType() const { return TagType; } int getTagType() const { return TagType; }
LLVMOpInfoCallback getGetOpInfo() const { return GetOpInfo; } LLVMOpInfoCallback getGetOpInfo() const { return GetOpInfo; }
LLVMSymbolLookupCallback getSymbolLookupCallback() const { LLVMSymbolLookupCallback getSymbolLookupCallback() const {
return SymbolLookUp; return SymbolLookUp;
} }
const Target *getTarget() const { return TheTarget; } const Target *getTarget() const { return TheTarget; }
const MCDisassembler *getDisAsm() const { return DisAsm.get(); } const MCDisassembler *getDisAsm() const { return DisAsm.get(); }
const MCAsmInfo *getAsmInfo() const { return MAI.get(); } const MCAsmInfo *getAsmInfo() const { return MAI.get(); }
const MCInstrInfo *getInstrInfo() const { return MII.get(); } const MCInstrInfo *getInstrInfo() const { return MII.get(); }
const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); } const MCRegisterInfo *getRegisterInfo() const { return MCRI.get(); }
const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); } const MCSubtargetInfo *getSubtargetInfo() const { return MSI.get(); }
MCInstPrinter *getIP() { return IP.get(); } MCInstPrinter *getIP() { return IP.get(); }
void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); } void setIP(MCInstPrinter *NewIP) { IP.reset(NewIP); }
uint64_t getOptions() const { return Options; } uint64_t getOptions() const { return Options; }
void addOptions(uint64_t Options) { this->Options |= Options; } void addOptions(uint64_t Options) { this->Options |= Options; }
StringRef getCPU() const { return CPU; } StringRef getCPU() const { return CPU; }
void setCPU(const char *CPU) { this->CPU = CPU; } void setCPU(const char *CPU) { this->CPU = CPU; }
}; };
} // namespace llvm } // namespace llvm
#endif #endif

llvm/lib/MC/MCDisassembler/Disassembler.cpp

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 LinesLLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
LLVMOpInfoCallback GetOpInfo, LLVMOpInfoCallback GetOpInfo,
LLVMSymbolLookupCallback SymbolLookUp) { LLVMSymbolLookupCallback SymbolLookUp) {
// Get the target. // Get the target.
std::string Error; std::string Error;
const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
if (!TheTarget) if (!TheTarget)
return nullptr; return nullptr;
std::unique_ptr<const MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TT)); std::unique_ptr<const MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TT));
if (!MRI) if (!MCRI)
return nullptr; return nullptr;
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
// Get the assembler info needed to setup the MCContext. // Get the assembler info needed to setup the MCContext.
std::unique_ptr<const MCAsmInfo> MAI( std::unique_ptr<const MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TT, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TT, MCOptions));
if (!MAI) if (!MAI)
return nullptr; return nullptr;
std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
return nullptr; return nullptr;
std::unique_ptr<const MCSubtargetInfo> STI( std::unique_ptr<const MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TT, CPU, Features)); TheTarget->createMCSubtargetInfo(TT, CPU, Features));
if (!STI) if (!STI)
return nullptr; return nullptr;
// Set up the MCContext for creating symbols and MCExpr's. // Set up the MCContext for creating symbols and MCExpr's.
std::unique_ptr<MCContext> Ctx( std::unique_ptr<MCContext> Ctx(
new MCContext(Triple(TT), MAI.get(), MRI.get(), STI.get())); new MCContext(Triple(TT), MAI.get(), MCRI.get(), STI.get()));
if (!Ctx) if (!Ctx)
return nullptr; return nullptr;
// Set up disassembler. // Set up disassembler.
std::unique_ptr<MCDisassembler> DisAsm( std::unique_ptr<MCDisassembler> DisAsm(
TheTarget->createMCDisassembler(*STI, *Ctx)); TheTarget->createMCDisassembler(*STI, *Ctx));
if (!DisAsm) if (!DisAsm)
return nullptr; return nullptr;
std::unique_ptr<MCRelocationInfo> RelInfo( std::unique_ptr<MCRelocationInfo> RelInfo(
TheTarget->createMCRelocationInfo(TT, *Ctx)); TheTarget->createMCRelocationInfo(TT, *Ctx));
if (!RelInfo) if (!RelInfo)
return nullptr; return nullptr;
std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer( std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(), std::move(RelInfo))); TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx.get(), std::move(RelInfo)));
DisAsm->setSymbolizer(std::move(Symbolizer)); DisAsm->setSymbolizer(std::move(Symbolizer));
// Set up the instruction printer. // Set up the instruction printer.
int AsmPrinterVariant = MAI->getAssemblerDialect(); int AsmPrinterVariant = MAI->getAssemblerDialect();
std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter( std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI)); Triple(TT), AsmPrinterVariant, *MAI, *MII, *MCRI));
if (!IP) if (!IP)
return nullptr; return nullptr;
LLVMDisasmContext *DC = new LLVMDisasmContext( LLVMDisasmContext *DC = new LLVMDisasmContext(
TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI), TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, TheTarget, std::move(MAI),
std::move(MRI), std::move(STI), std::move(MII), std::move(Ctx), std::move(MCRI), std::move(STI), std::move(MII), std::move(Ctx),
std::move(DisAsm), std::move(IP)); std::move(DisAsm), std::move(IP));
if (!DC) if (!DC)
return nullptr; return nullptr;
DC->setCPU(CPU); DC->setCPU(CPU);
return DC; return DC;
} }
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines if (Options & LLVMDisassembler_Option_PrintImmHex){
DC->addOptions(LLVMDisassembler_Option_PrintImmHex); DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
Options &= ~LLVMDisassembler_Option_PrintImmHex; Options &= ~LLVMDisassembler_Option_PrintImmHex;
} }
if (Options & LLVMDisassembler_Option_AsmPrinterVariant){ if (Options & LLVMDisassembler_Option_AsmPrinterVariant){
LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR); LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
// Try to set up the new instruction printer. // Try to set up the new instruction printer.
const MCAsmInfo *MAI = DC->getAsmInfo(); const MCAsmInfo *MAI = DC->getAsmInfo();
const MCInstrInfo *MII = DC->getInstrInfo(); const MCInstrInfo *MII = DC->getInstrInfo();
const MCRegisterInfo *MRI = DC->getRegisterInfo(); const MCRegisterInfo *MCRI = DC->getRegisterInfo();
int AsmPrinterVariant = MAI->getAssemblerDialect(); int AsmPrinterVariant = MAI->getAssemblerDialect();
AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0; AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter( MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter(
Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI); Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MCRI);
if (IP) { if (IP) {
DC->setIP(IP); DC->setIP(IP);
DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant); DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
Options &= ~LLVMDisassembler_Option_AsmPrinterVariant; Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
} }
} }
if (Options & LLVMDisassembler_Option_SetInstrComments) { if (Options & LLVMDisassembler_Option_SetInstrComments) {
LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR); LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
Show All 12 Lines

llvm/lib/MC/MCDwarf.cpp

Show First 20 Lines • Show All 1,313 Lines • ▼ Show 20 Lines
} // end anonymous namespace } // end anonymous namespace
static void emitEncodingByte(MCObjectStreamer &Streamer, unsigned Encoding) { static void emitEncodingByte(MCObjectStreamer &Streamer, unsigned Encoding) {
Streamer.emitInt8(Encoding); Streamer.emitInt8(Encoding);
} }
void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) {
int dataAlignmentFactor = getDataAlignmentFactor(Streamer); int dataAlignmentFactor = getDataAlignmentFactor(Streamer);
auto *MRI = Streamer.getContext().getRegisterInfo(); auto *MCRI = Streamer.getContext().getRegisterInfo();
switch (Instr.getOperation()) { switch (Instr.getOperation()) {
case MCCFIInstruction::OpRegister: { case MCCFIInstruction::OpRegister: {
unsigned Reg1 = Instr.getRegister(); unsigned Reg1 = Instr.getRegister();
unsigned Reg2 = Instr.getRegister2(); unsigned Reg2 = Instr.getRegister2();
if (!IsEH) { if (!IsEH) {
Reg1 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg1); Reg1 = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg1);
Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); Reg2 = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg2);
} }
Streamer.emitInt8(dwarf::DW_CFA_register); Streamer.emitInt8(dwarf::DW_CFA_register);
Streamer.emitULEB128IntValue(Reg1); Streamer.emitULEB128IntValue(Reg1);
Streamer.emitULEB128IntValue(Reg2); Streamer.emitULEB128IntValue(Reg2);
return; return;
} }
case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpWindowSave:
Streamer.emitInt8(dwarf::DW_CFA_GNU_window_save); Streamer.emitInt8(dwarf::DW_CFA_GNU_window_save);
Show All 23 Lines case MCCFIInstruction::OpDefCfaOffset: {
Streamer.emitULEB128IntValue(CFAOffset); Streamer.emitULEB128IntValue(CFAOffset);
return; return;
} }
case MCCFIInstruction::OpDefCfa: { case MCCFIInstruction::OpDefCfa: {
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
if (!IsEH) if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
Streamer.emitInt8(dwarf::DW_CFA_def_cfa); Streamer.emitInt8(dwarf::DW_CFA_def_cfa);
Streamer.emitULEB128IntValue(Reg); Streamer.emitULEB128IntValue(Reg);
CFAOffset = Instr.getOffset(); CFAOffset = Instr.getOffset();
Streamer.emitULEB128IntValue(CFAOffset); Streamer.emitULEB128IntValue(CFAOffset);
return; return;
} }
case MCCFIInstruction::OpDefCfaRegister: { case MCCFIInstruction::OpDefCfaRegister: {
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
if (!IsEH) if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
Streamer.emitInt8(dwarf::DW_CFA_def_cfa_register); Streamer.emitInt8(dwarf::DW_CFA_def_cfa_register);
Streamer.emitULEB128IntValue(Reg); Streamer.emitULEB128IntValue(Reg);
return; return;
} }
// TODO: Implement `_sf` variants if/when they need to be emitted. // TODO: Implement `_sf` variants if/when they need to be emitted.
case MCCFIInstruction::OpLLVMDefAspaceCfa: { case MCCFIInstruction::OpLLVMDefAspaceCfa: {
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
if (!IsEH) if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
Streamer.emitIntValue(dwarf::DW_CFA_LLVM_def_aspace_cfa, 1); Streamer.emitIntValue(dwarf::DW_CFA_LLVM_def_aspace_cfa, 1);
Streamer.emitULEB128IntValue(Reg); Streamer.emitULEB128IntValue(Reg);
CFAOffset = Instr.getOffset(); CFAOffset = Instr.getOffset();
Streamer.emitULEB128IntValue(CFAOffset); Streamer.emitULEB128IntValue(CFAOffset);
Streamer.emitULEB128IntValue(Instr.getAddressSpace()); Streamer.emitULEB128IntValue(Instr.getAddressSpace());
return; return;
} }
case MCCFIInstruction::OpOffset: case MCCFIInstruction::OpOffset:
case MCCFIInstruction::OpRelOffset: { case MCCFIInstruction::OpRelOffset: {
const bool IsRelative = const bool IsRelative =
Instr.getOperation() == MCCFIInstruction::OpRelOffset; Instr.getOperation() == MCCFIInstruction::OpRelOffset;
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
if (!IsEH) if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
int Offset = Instr.getOffset(); int Offset = Instr.getOffset();
if (IsRelative) if (IsRelative)
Offset -= CFAOffset; Offset -= CFAOffset;
Offset = Offset / dataAlignmentFactor; Offset = Offset / dataAlignmentFactor;
if (Offset < 0) { if (Offset < 0) {
Streamer.emitInt8(dwarf::DW_CFA_offset_extended_sf); Streamer.emitInt8(dwarf::DW_CFA_offset_extended_sf);
Show All 19 Lines case MCCFIInstruction::OpSameValue: {
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
Streamer.emitInt8(dwarf::DW_CFA_same_value); Streamer.emitInt8(dwarf::DW_CFA_same_value);
Streamer.emitULEB128IntValue(Reg); Streamer.emitULEB128IntValue(Reg);
return; return;
} }
case MCCFIInstruction::OpRestore: { case MCCFIInstruction::OpRestore: {
unsigned Reg = Instr.getRegister(); unsigned Reg = Instr.getRegister();
if (!IsEH) if (!IsEH)
Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Reg = MCRI->getDwarfRegNumFromDwarfEHRegNum(Reg);
if (Reg < 64) { if (Reg < 64) {
Streamer.emitInt8(dwarf::DW_CFA_restore | Reg); Streamer.emitInt8(dwarf::DW_CFA_restore | Reg);
} else { } else {
Streamer.emitInt8(dwarf::DW_CFA_restore_extended); Streamer.emitInt8(dwarf::DW_CFA_restore_extended);
Streamer.emitULEB128IntValue(Reg); Streamer.emitULEB128IntValue(Reg);
} }
return; return;
} }
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Linesstatic unsigned getCIEVersion(bool IsEH, unsigned DwarfVersion) {
case 5: case 5:
return 4; return 4;
} }
llvm_unreachable("Unknown version"); llvm_unreachable("Unknown version");
} }
const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) {
MCContext &context = Streamer.getContext(); MCContext &context = Streamer.getContext();
const MCRegisterInfo *MRI = context.getRegisterInfo(); const MCRegisterInfo *MCRI = context.getRegisterInfo();
const MCObjectFileInfo *MOFI = context.getObjectFileInfo(); const MCObjectFileInfo *MOFI = context.getObjectFileInfo();
MCSymbol *sectionStart = context.createTempSymbol(); MCSymbol *sectionStart = context.createTempSymbol();
Streamer.emitLabel(sectionStart); Streamer.emitLabel(sectionStart);
MCSymbol *sectionEnd = context.createTempSymbol(); MCSymbol *sectionEnd = context.createTempSymbol();
dwarf::DwarfFormat Format = IsEH ? dwarf::DWARF32 : context.getDwarfFormat(); dwarf::DwarfFormat Format = IsEH ? dwarf::DWARF32 : context.getDwarfFormat();
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesconst MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) {
Streamer.emitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment()); Streamer.emitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment());
// Data Alignment Factor // Data Alignment Factor
Streamer.emitSLEB128IntValue(getDataAlignmentFactor(Streamer)); Streamer.emitSLEB128IntValue(getDataAlignmentFactor(Streamer));
// Return Address Register // Return Address Register
unsigned RAReg = Frame.RAReg; unsigned RAReg = Frame.RAReg;
if (RAReg == static_cast<unsigned>(INT_MAX)) if (RAReg == static_cast<unsigned>(INT_MAX))
RAReg = MRI->getDwarfRegNum(MRI->getRARegister(), IsEH); RAReg = MCRI->getDwarfRegNum(MCRI->getRARegister(), IsEH);
if (CIEVersion == 1) { if (CIEVersion == 1) {
assert(RAReg <= 255 && assert(RAReg <= 255 &&
"DWARF 2 encodes return_address_register in one byte"); "DWARF 2 encodes return_address_register in one byte");
Streamer.emitInt8(RAReg); Streamer.emitInt8(RAReg);
} else { } else {
Streamer.emitULEB128IntValue(RAReg); Streamer.emitULEB128IntValue(RAReg);
} }
▲ Show 20 Lines • Show All 314 Lines • Show Last 20 Lines

llvm/lib/MC/MCInstPrinter.cpp

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines if (CommentStream) {
if (Annot.back() != '\n') if (Annot.back() != '\n')
(*CommentStream) << '\n'; (*CommentStream) << '\n';
} else } else
OS << " " << MAI.getCommentString() << " " << Annot; OS << " " << MAI.getCommentString() << " " << Annot;
} }
} }
static bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI, static bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI,
const MCRegisterInfo &MRI, unsigned &OpIdx, const MCRegisterInfo &MCRI, unsigned &OpIdx,
const AliasMatchingData &M, const AliasMatchingData &M,
const AliasPatternCond &C, const AliasPatternCond &C,
bool &OrPredicateResult) { bool &OrPredicateResult) {
// Feature tests are special, they don't consume operands. // Feature tests are special, they don't consume operands.
if (C.Kind == AliasPatternCond::K_Feature) if (C.Kind == AliasPatternCond::K_Feature)
return STI->getFeatureBits().test(C.Value); return STI->getFeatureBits().test(C.Value);
if (C.Kind == AliasPatternCond::K_NegFeature) if (C.Kind == AliasPatternCond::K_NegFeature)
return !STI->getFeatureBits().test(C.Value); return !STI->getFeatureBits().test(C.Value);
Show All 26 Linesstatic bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI,
case AliasPatternCond::K_Reg: case AliasPatternCond::K_Reg:
// Operand must be a specific register. // Operand must be a specific register.
return Opnd.isReg() && Opnd.getReg() == C.Value; return Opnd.isReg() && Opnd.getReg() == C.Value;
case AliasPatternCond::K_TiedReg: case AliasPatternCond::K_TiedReg:
// Operand must match the register of another operand. // Operand must match the register of another operand.
return Opnd.isReg() && Opnd.getReg() == MI.getOperand(C.Value).getReg(); return Opnd.isReg() && Opnd.getReg() == MI.getOperand(C.Value).getReg();
case AliasPatternCond::K_RegClass: case AliasPatternCond::K_RegClass:
// Operand must be a register in this class. Value is a register class id. // Operand must be a register in this class. Value is a register class id.
return Opnd.isReg() && MRI.getRegClass(C.Value).contains(Opnd.getReg()); return Opnd.isReg() && MCRI.getRegClass(C.Value).contains(Opnd.getReg());
case AliasPatternCond::K_Custom: case AliasPatternCond::K_Custom:
// Operand must match some custom criteria. // Operand must match some custom criteria.
return M.ValidateMCOperand(Opnd, *STI, C.Value); return M.ValidateMCOperand(Opnd, *STI, C.Value);
case AliasPatternCond::K_Ignore: case AliasPatternCond::K_Ignore:
// Operand can be anything. // Operand can be anything.
return true; return true;
case AliasPatternCond::K_Feature: case AliasPatternCond::K_Feature:
case AliasPatternCond::K_NegFeature: case AliasPatternCond::K_NegFeature:
Show All 27 Lines if (MI->getNumOperands() != P.NumOperands)
return nullptr; return nullptr;
// Test all conditions for this pattern. // Test all conditions for this pattern.
ArrayRef<AliasPatternCond> Conds = ArrayRef<AliasPatternCond> Conds =
M.PatternConds.slice(P.AliasCondStart, P.NumConds); M.PatternConds.slice(P.AliasCondStart, P.NumConds);
unsigned OpIdx = 0; unsigned OpIdx = 0;
bool OrPredicateResult = false; bool OrPredicateResult = false;
if (llvm::all_of(Conds, [&](const AliasPatternCond &C) { if (llvm::all_of(Conds, [&](const AliasPatternCond &C) {
return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C, return matchAliasCondition(*MI, STI, MCRI, OpIdx, M, C,
OrPredicateResult); OrPredicateResult);
})) { })) {
// If all conditions matched, use this asm string. // If all conditions matched, use this asm string.
AsmStrOffset = P.AsmStrOffset; AsmStrOffset = P.AsmStrOffset;
break; break;
} }
} }
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/lib/MC/MCInstrAnalysis.cpp

Show All 11 Lines
#include <cstdint> #include <cstdint>
namespace llvm { namespace llvm {
class MCSubtargetInfo; class MCSubtargetInfo;
} }
using namespace llvm; using namespace llvm;
bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MCRI,
const MCInst &Inst, const MCInst &Inst,
APInt &Writes) const { APInt &Writes) const {
Writes.clearAllBits(); Writes.clearAllBits();
return false; return false;
} }
bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/, bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
uint64_t /*Size*/, uint64_t /*Size*/,
Show All 15 Lines

llvm/lib/MC/MCInstrDesc.cpp

Show All 24 Linesbool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
if (PC == 0) if (PC == 0)
return false; return false;
if (hasDefOfPhysReg(MI, PC, RI)) if (hasDefOfPhysReg(MI, PC, RI))
return true; return true;
return false; return false;
} }
bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI) const { const MCRegisterInfo *MCRI) const {
if (const MCPhysReg *ImpDefs = getImplicitDefs()) if (const MCPhysReg *ImpDefs = getImplicitDefs())
for (; *ImpDefs; ++ImpDefs) for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) if (*ImpDefs == Reg || (MCRI && MCRI->isSubRegister(Reg, *ImpDefs)))
return true; return true;
return false; return false;
} }
bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
const MCRegisterInfo &RI) const { const MCRegisterInfo &RI) const {
for (int i = 0, e = NumDefs; i != e; ++i) for (int i = 0, e = NumDefs; i != e; ++i)
if (MI.getOperand(i).isReg() && if (MI.getOperand(i).isReg() &&
Show All 9 Lines

llvm/lib/MCA/Context.cpp

Show All 32 LinesContext::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
CustomBehaviour &CB) { CustomBehaviour &CB) {
const MCSchedModel &SM = STI.getSchedModel(); const MCSchedModel &SM = STI.getSchedModel();
if (!SM.isOutOfOrder()) if (!SM.isOutOfOrder())
return createInOrderPipeline(Opts, SrcMgr, CB); return createInOrderPipeline(Opts, SrcMgr, CB);
// Create the hardware units defining the backend. // Create the hardware units defining the backend.
auto RCU = std::make_unique<RetireControlUnit>(SM); auto RCU = std::make_unique<RetireControlUnit>(SM);
auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); auto PRF = std::make_unique<RegisterFile>(SM, MCRI, Opts.RegisterFileSize);
auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
Opts.StoreQueueSize, Opts.AssumeNoAlias); Opts.StoreQueueSize, Opts.AssumeNoAlias);
auto HWS = std::make_unique<Scheduler>(SM, *LSU); auto HWS = std::make_unique<Scheduler>(SM, *LSU);
// Create the pipeline stages. // Create the pipeline stages.
auto Fetch = std::make_unique<EntryStage>(SrcMgr); auto Fetch = std::make_unique<EntryStage>(SrcMgr);
auto Dispatch = auto Dispatch = std::make_unique<DispatchStage>(STI, MCRI, Opts.DispatchWidth,
std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF); *RCU, *PRF);
auto Execute = auto Execute =
std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis); std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
// Pass the ownership of all the hardware units to this Context. // Pass the ownership of all the hardware units to this Context.
addHardwareUnit(std::move(RCU)); addHardwareUnit(std::move(RCU));
addHardwareUnit(std::move(PRF)); addHardwareUnit(std::move(PRF));
addHardwareUnit(std::move(LSU)); addHardwareUnit(std::move(LSU));
Show All 10 LinesContext::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
StagePipeline->appendStage(std::move(Retire)); StagePipeline->appendStage(std::move(Retire));
return StagePipeline; return StagePipeline;
} }
std::unique_ptr<Pipeline> std::unique_ptr<Pipeline>
Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr, Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr,
CustomBehaviour &CB) { CustomBehaviour &CB) {
const MCSchedModel &SM = STI.getSchedModel(); const MCSchedModel &SM = STI.getSchedModel();
auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); auto PRF = std::make_unique<RegisterFile>(SM, MCRI, Opts.RegisterFileSize);
auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
Opts.StoreQueueSize, Opts.AssumeNoAlias); Opts.StoreQueueSize, Opts.AssumeNoAlias);
// Create the pipeline stages. // Create the pipeline stages.
auto Entry = std::make_unique<EntryStage>(SrcMgr); auto Entry = std::make_unique<EntryStage>(SrcMgr);
auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU); auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU);
auto StagePipeline = std::make_unique<Pipeline>(); auto StagePipeline = std::make_unique<Pipeline>();
Show All 12 Lines

llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
MCPhysReg WriteRef::getRegisterID() const { MCPhysReg WriteRef::getRegisterID() const {
if (Write) if (Write)
return Write->getRegisterID(); return Write->getRegisterID();
return RegisterID; return RegisterID;
} }
RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
unsigned NumRegs) unsigned NumRegs)
: MRI(mri), : MCRI(mri),
RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}), RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}),
ZeroRegisters(mri.getNumRegs(), false), CurrentCycle() { ZeroRegisters(mri.getNumRegs(), false), CurrentCycle() {
initialize(SM, NumRegs); initialize(SM, NumRegs);
} }
void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
// Create a default register file that "sees" all the machine registers // Create a default register file that "sees" all the machine registers
// declared by the target. The number of physical registers in the default // declared by the target. The number of physical registers in the default
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines for (WriteState &WS : IS->getDefs()) {
MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs; MCPhysReg RenameAs = RegisterMappings[RegID].second.RenameAs;
if (RenameAs && RenameAs != RegID) if (RenameAs && RenameAs != RegID)
RegID = RenameAs; RegID = RenameAs;
WriteRef &WR = RegisterMappings[RegID].first; WriteRef &WR = RegisterMappings[RegID].first;
if (WR.getWriteState() == &WS) if (WR.getWriteState() == &WS)
WR.notifyExecuted(CurrentCycle); WR.notifyExecuted(CurrentCycle);
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
WriteRef &OtherWR = RegisterMappings[*I].first; WriteRef &OtherWR = RegisterMappings[*I].first;
if (OtherWR.getWriteState() == &WS) if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle); OtherWR.notifyExecuted(CurrentCycle);
} }
if (!WS.clearsSuperRegisters()) if (!WS.clearsSuperRegisters())
continue; continue;
for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
WriteRef &OtherWR = RegisterMappings[*I].first; WriteRef &OtherWR = RegisterMappings[*I].first;
if (OtherWR.getWriteState() == &WS) if (OtherWR.getWriteState() == &WS)
OtherWR.notifyExecuted(CurrentCycle); OtherWR.notifyExecuted(CurrentCycle);
} }
} }
} }
void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF, void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF,
Show All 13 Linesvoid RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF,
// We optimistically assume that a register can be renamed at the cost of a // We optimistically assume that a register can be renamed at the cost of a
// single physical register. The constructor of RegisterFile ensures that // single physical register. The constructor of RegisterFile ensures that
// a RegisterMapping exists for each logical register defined by the Target. // a RegisterMapping exists for each logical register defined by the Target.
if (Entries.empty()) if (Entries.empty())
return; return;
// Now update the cost of individual registers. // Now update the cost of individual registers.
for (const MCRegisterCostEntry &RCE : Entries) { for (const MCRegisterCostEntry &RCE : Entries) {
const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); const MCRegisterClass &RC = MCRI.getRegClass(RCE.RegisterClassID);
for (const MCPhysReg Reg : RC) { for (const MCPhysReg Reg : RC) {
RegisterRenamingInfo &Entry = RegisterMappings[Reg].second; RegisterRenamingInfo &Entry = RegisterMappings[Reg].second;
IndexPlusCostPairTy &IPC = Entry.IndexPlusCost; IndexPlusCostPairTy &IPC = Entry.IndexPlusCost;
if (IPC.first && IPC.first != RegisterFileIndex) { if (IPC.first && IPC.first != RegisterFileIndex) {
// The only register file that is allowed to overlap is the default // The only register file that is allowed to overlap is the default
// register file at index #0. The analysis is inaccurate if register // register file at index #0. The analysis is inaccurate if register
// files overlap. // files overlap.
errs() << "warning: register " << MRI.getName(Reg) errs() << "warning: register " << MCRI.getName(Reg)
<< " defined in multiple register files."; << " defined in multiple register files.";
} }
IPC = std::make_pair(RegisterFileIndex, RCE.Cost); IPC = std::make_pair(RegisterFileIndex, RCE.Cost);
Entry.RenameAs = Reg; Entry.RenameAs = Reg;
Entry.AllowMoveElimination = RCE.AllowMoveElimination; Entry.AllowMoveElimination = RCE.AllowMoveElimination;
// Assume the same cost for each sub-register. // Assume the same cost for each sub-register.
for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) { for (MCSubRegIterator I(Reg, &MCRI); I.isValid(); ++I) {
RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second; RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second;
if (!OtherEntry.IndexPlusCost.first && if (!OtherEntry.IndexPlusCost.first &&
(!OtherEntry.RenameAs || (!OtherEntry.RenameAs ||
MRI.isSuperRegister(*I, OtherEntry.RenameAs))) { MCRI.isSuperRegister(*I, OtherEntry.RenameAs))) {
OtherEntry.IndexPlusCost = IPC; OtherEntry.IndexPlusCost = IPC;
OtherEntry.RenameAs = Reg; OtherEntry.RenameAs = Reg;
} }
} }
} }
} }
} }
Show All 34 Linesvoid RegisterFile::addRegisterWrite(WriteRef Write,
// This allows InstrPostProcess to remove register Defs // This allows InstrPostProcess to remove register Defs
// by setting their RegisterID to 0. // by setting their RegisterID to 0.
if (!RegID) if (!RegID)
return; return;
LLVM_DEBUG({ LLVM_DEBUG({
dbgs() << "[PRF] addRegisterWrite [ " << Write.getSourceIndex() << ", " dbgs() << "[PRF] addRegisterWrite [ " << Write.getSourceIndex() << ", "
<< MRI.getName(RegID) << "]\n"; << MCRI.getName(RegID) << "]\n";
}); });
// If RenameAs is equal to RegID, then RegID is subject to register renaming // If RenameAs is equal to RegID, then RegID is subject to register renaming
// and false dependencies on RegID are all eliminated. // and false dependencies on RegID are all eliminated.
// If RenameAs references the invalid register, then we optimistically assume // If RenameAs references the invalid register, then we optimistically assume
// that it can be renamed. In the absence of tablegen descriptors for register // that it can be renamed. In the absence of tablegen descriptors for register
// files, RenameAs is always set to the invalid register ID. In all other // files, RenameAs is always set to the invalid register ID. In all other
Show All 28 Lines if (!WS.clearsSuperRegisters()) {
} }
} }
} }
// Update zero registers. // Update zero registers.
MCPhysReg ZeroRegisterID = MCPhysReg ZeroRegisterID =
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID(); WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero); ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I) for (MCSubRegIterator I(ZeroRegisterID, &MCRI); I.isValid(); ++I)
ZeroRegisters.setBitVal(*I, IsWriteZero); ZeroRegisters.setBitVal(*I, IsWriteZero);
// If this move has been eliminated, then method tryEliminateMoveOrSwap should // If this move has been eliminated, then method tryEliminateMoveOrSwap should
// have already updated all the register mappings. // have already updated all the register mappings.
if (!IsEliminated) { if (!IsEliminated) {
// Check if this is one of multiple writes performed by this // Check if this is one of multiple writes performed by this
// instruction to register RegID. // instruction to register RegID.
const WriteRef &OtherWrite = RegisterMappings[RegID].first; const WriteRef &OtherWrite = RegisterMappings[RegID].first;
const WriteState *OtherWS = OtherWrite.getWriteState(); const WriteState *OtherWS = OtherWrite.getWriteState();
if (OtherWS && OtherWrite.getSourceIndex() == Write.getSourceIndex()) { if (OtherWS && OtherWrite.getSourceIndex() == Write.getSourceIndex()) {
if (OtherWS->getLatency() > WS.getLatency()) { if (OtherWS->getLatency() > WS.getLatency()) {
// Conservatively keep the slowest write on RegID. // Conservatively keep the slowest write on RegID.
if (ShouldAllocatePhysRegs) if (ShouldAllocatePhysRegs)
allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs); allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);
return; return;
} }
} }
// Update the mapping for register RegID including its sub-registers. // Update the mapping for register RegID including its sub-registers.
RegisterMappings[RegID].first = Write; RegisterMappings[RegID].first = Write;
RegisterMappings[RegID].second.AliasRegID = 0U; RegisterMappings[RegID].second.AliasRegID = 0U;
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
RegisterMappings[*I].first = Write; RegisterMappings[*I].first = Write;
RegisterMappings[*I].second.AliasRegID = 0U; RegisterMappings[*I].second.AliasRegID = 0U;
} }
// No physical registers are allocated for instructions that are optimized // No physical registers are allocated for instructions that are optimized
// in hardware. For example, zero-latency data-dependency breaking // in hardware. For example, zero-latency data-dependency breaking
// instructions don't consume physical registers. // instructions don't consume physical registers.
if (ShouldAllocatePhysRegs) if (ShouldAllocatePhysRegs)
allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs); allocatePhysRegs(RegisterMappings[RegID].second, UsedPhysRegs);
} }
if (!WS.clearsSuperRegisters()) if (!WS.clearsSuperRegisters())
return; return;
for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
if (!IsEliminated) { if (!IsEliminated) {
RegisterMappings[*I].first = Write; RegisterMappings[*I].first = Write;
RegisterMappings[*I].second.AliasRegID = 0U; RegisterMappings[*I].second.AliasRegID = 0U;
} }
ZeroRegisters.setBitVal(*I, IsWriteZero); ZeroRegisters.setBitVal(*I, IsWriteZero);
} }
} }
Show All 29 Linesvoid RegisterFile::removeRegisterWrite(
if (ShouldFreePhysRegs) if (ShouldFreePhysRegs)
freePhysRegs(RegisterMappings[RegID].second, FreedPhysRegs); freePhysRegs(RegisterMappings[RegID].second, FreedPhysRegs);
WriteRef &WR = RegisterMappings[RegID].first; WriteRef &WR = RegisterMappings[RegID].first;
if (WR.getWriteState() == &WS) if (WR.getWriteState() == &WS)
WR.commit(); WR.commit();
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
WriteRef &OtherWR = RegisterMappings[*I].first; WriteRef &OtherWR = RegisterMappings[*I].first;
if (OtherWR.getWriteState() == &WS) if (OtherWR.getWriteState() == &WS)
OtherWR.commit(); OtherWR.commit();
} }
if (!WS.clearsSuperRegisters()) if (!WS.clearsSuperRegisters())
return; return;
for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSuperRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
WriteRef &OtherWR = RegisterMappings[*I].first; WriteRef &OtherWR = RegisterMappings[*I].first;
if (OtherWR.getWriteState() == &WS) if (OtherWR.getWriteState() == &WS)
OtherWR.commit(); OtherWR.commit();
} }
} }
bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS, bool RegisterFile::canEliminateMove(const WriteState &WS, const ReadState &RS,
unsigned RegisterFileIndex) const { unsigned RegisterFileIndex) const {
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines MCPhysReg AliasedReg =
RRIFrom.RenameAs ? RRIFrom.RenameAs : RS.getRegisterID(); RRIFrom.RenameAs ? RRIFrom.RenameAs : RS.getRegisterID();
MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID(); MCPhysReg AliasReg = RRITo.RenameAs ? RRITo.RenameAs : WS.getRegisterID();
const RegisterRenamingInfo &RMAlias = RegisterMappings[AliasedReg].second; const RegisterRenamingInfo &RMAlias = RegisterMappings[AliasedReg].second;
if (RMAlias.AliasRegID) if (RMAlias.AliasRegID)
AliasedReg = RMAlias.AliasRegID; AliasedReg = RMAlias.AliasRegID;
RegisterMappings[AliasReg].second.AliasRegID = AliasedReg; RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
for (MCSubRegIterator I(AliasReg, &MRI); I.isValid(); ++I) for (MCSubRegIterator I(AliasReg, &MCRI); I.isValid(); ++I)
RegisterMappings[*I].second.AliasRegID = AliasedReg; RegisterMappings[*I].second.AliasRegID = AliasedReg;
if (ZeroRegisters[RS.getRegisterID()]) { if (ZeroRegisters[RS.getRegisterID()]) {
WS.setWriteZero(); WS.setWriteZero();
RS.setReadZero(); RS.setReadZero();
} }
WS.setEliminated(); WS.setEliminated();
Show All 20 Linesvoid RegisterFile::collectWrites(
SmallVectorImpl<WriteRef> &Writes, SmallVectorImpl<WriteRef> &Writes,
SmallVectorImpl<WriteRef> &CommittedWrites) const { SmallVectorImpl<WriteRef> &CommittedWrites) const {
const ReadDescriptor &RD = RS.getDescriptor(); const ReadDescriptor &RD = RS.getDescriptor();
const MCSchedModel &SM = STI.getSchedModel(); const MCSchedModel &SM = STI.getSchedModel();
const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
MCPhysReg RegID = RS.getRegisterID(); MCPhysReg RegID = RS.getRegisterID();
assert(RegID && RegID < RegisterMappings.size()); assert(RegID && RegID < RegisterMappings.size());
LLVM_DEBUG(dbgs() << "[PRF] collecting writes for register " LLVM_DEBUG(dbgs() << "[PRF] collecting writes for register "
<< MRI.getName(RegID) << '\n'); << MCRI.getName(RegID) << '\n');
// Check if this is an alias. // Check if this is an alias.
const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second; const RegisterRenamingInfo &RRI = RegisterMappings[RegID].second;
if (RRI.AliasRegID) if (RRI.AliasRegID)
RegID = RRI.AliasRegID; RegID = RRI.AliasRegID;
const WriteRef &WR = RegisterMappings[RegID].first; const WriteRef &WR = RegisterMappings[RegID].first;
if (WR.getWriteState()) { if (WR.getWriteState()) {
Writes.push_back(WR); Writes.push_back(WR);
} else if (WR.hasKnownWriteBackCycle()) { } else if (WR.hasKnownWriteBackCycle()) {
unsigned WriteResID = WR.getWriteResourceID(); unsigned WriteResID = WR.getWriteResourceID();
int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
if (ReadAdvance < 0) { if (ReadAdvance < 0) {
unsigned Elapsed = getElapsedCyclesFromWriteBack(WR); unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
if (Elapsed < static_cast<unsigned>(-ReadAdvance)) if (Elapsed < static_cast<unsigned>(-ReadAdvance))
CommittedWrites.push_back(WR); CommittedWrites.push_back(WR);
} }
} }
// Handle potential partial register updates. // Handle potential partial register updates.
for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { for (MCSubRegIterator I(RegID, &MCRI); I.isValid(); ++I) {
const WriteRef &WR = RegisterMappings[*I].first; const WriteRef &WR = RegisterMappings[*I].first;
if (WR.getWriteState()) { if (WR.getWriteState()) {
Writes.push_back(WR); Writes.push_back(WR);
} else if (WR.hasKnownWriteBackCycle()) { } else if (WR.hasKnownWriteBackCycle()) {
unsigned WriteResID = WR.getWriteResourceID(); unsigned WriteResID = WR.getWriteResourceID();
int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
if (ReadAdvance < 0) { if (ReadAdvance < 0) {
unsigned Elapsed = getElapsedCyclesFromWriteBack(WR); unsigned Elapsed = getElapsedCyclesFromWriteBack(WR);
Show All 11 Lines if (Writes.size() > 1) {
auto It = std::unique(Writes.begin(), Writes.end()); auto It = std::unique(Writes.begin(), Writes.end());
Writes.resize(std::distance(Writes.begin(), It)); Writes.resize(std::distance(Writes.begin(), It));
} }
LLVM_DEBUG({ LLVM_DEBUG({
for (const WriteRef &WR : Writes) { for (const WriteRef &WR : Writes) {
const WriteState &WS = *WR.getWriteState(); const WriteState &WS = *WR.getWriteState();
dbgs() << "[PRF] Found a dependent use of Register " dbgs() << "[PRF] Found a dependent use of Register "
<< MRI.getName(WS.getRegisterID()) << " (defined by instruction #" << MCRI.getName(WS.getRegisterID()) << " (defined by instruction #"
<< WR.getSourceIndex() << ")\n"; << WR.getSourceIndex() << ")\n";
} }
}); });
} }
RegisterFile::RAWHazard RegisterFile::RAWHazard
RegisterFile::checkRAWHazards(const MCSubtargetInfo &STI, RegisterFile::checkRAWHazards(const MCSubtargetInfo &STI,
const ReadState &RS) const { const ReadState &RS) const {
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Linesvoid WriteRef::dump() const {
dbgs() << "IID=" << getSourceIndex() << ' '; dbgs() << "IID=" << getSourceIndex() << ' ';
if (isValid()) if (isValid())
getWriteState()->dump(); getWriteState()->dump();
else else
dbgs() << "(null)"; dbgs() << "(null)";
} }
void RegisterFile::dump() const { void RegisterFile::dump() const {
for (unsigned I = 0, E = MRI.getNumRegs(); I < E; ++I) { for (unsigned I = 0, E = MCRI.getNumRegs(); I < E; ++I) {
const RegisterMapping &RM = RegisterMappings[I]; const RegisterMapping &RM = RegisterMappings[I];
const RegisterRenamingInfo &RRI = RM.second; const RegisterRenamingInfo &RRI = RM.second;
if (ZeroRegisters[I]) { if (ZeroRegisters[I]) {
dbgs() << MRI.getName(I) << ", " << I dbgs() << MCRI.getName(I) << ", " << I
<< ", PRF=" << RRI.IndexPlusCost.first << ", PRF=" << RRI.IndexPlusCost.first
<< ", Cost=" << RRI.IndexPlusCost.second << ", Cost=" << RRI.IndexPlusCost.second
<< ", RenameAs=" << RRI.RenameAs << ", IsZero=" << ZeroRegisters[I] << ", RenameAs=" << RRI.RenameAs << ", IsZero=" << ZeroRegisters[I]
<< ","; << ",";
RM.first.dump(); RM.first.dump();
dbgs() << '\n'; dbgs() << '\n';
} }
} }
Show All 12 Lines

llvm/lib/MCA/InstrBuilder.cpp

Show All 26 Lines
char RecycledInstErr::ID = 0; char RecycledInstErr::ID = 0;
InstrBuilder::InstrBuilder(const llvm::MCSubtargetInfo &sti, InstrBuilder::InstrBuilder(const llvm::MCSubtargetInfo &sti,
const llvm::MCInstrInfo &mcii, const llvm::MCInstrInfo &mcii,
const llvm::MCRegisterInfo &mri, const llvm::MCRegisterInfo &mri,
const llvm::MCInstrAnalysis *mcia, const llvm::MCInstrAnalysis *mcia,
const mca::InstrumentManager &im) const mca::InstrumentManager &im)
: STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), IM(im), FirstCallInst(true), : STI(sti), MCII(mcii), MCRI(mri), MCIA(mcia), IM(im), FirstCallInst(true),
FirstReturnInst(true) { FirstReturnInst(true) {
const MCSchedModel &SM = STI.getSchedModel(); const MCSchedModel &SM = STI.getSchedModel();
ProcResourceMasks.resize(SM.getNumProcResourceKinds()); ProcResourceMasks.resize(SM.getNumProcResourceKinds());
computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
} }
static void initializeUsedResources(InstrDesc &ID, static void initializeUsedResources(InstrDesc &ID,
const MCSchedClassDesc &SCDesc, const MCSchedClassDesc &SCDesc,
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines if (Index < NumWriteLatencyEntries) {
Write.Latency = ID.MaxLatency; Write.Latency = ID.MaxLatency;
Write.SClassOrWriteResourceID = 0; Write.SClassOrWriteResourceID = 0;
} }
Write.IsOptionalDef = false; Write.IsOptionalDef = false;
assert(Write.RegisterID != 0 && "Expected a valid phys register!"); assert(Write.RegisterID != 0 && "Expected a valid phys register!");
LLVM_DEBUG({ LLVM_DEBUG({
dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex
<< ", PhysReg=" << MRI.getName(Write.RegisterID) << ", PhysReg=" << MCRI.getName(Write.RegisterID)
<< ", Latency=" << Write.Latency << ", Latency=" << Write.Latency
<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n'; << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
}); });
} }
if (MCDesc.hasOptionalDef()) { if (MCDesc.hasOptionalDef()) {
WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs];
Write.OpIndex = OptionalDefIdx; Write.OpIndex = OptionalDefIdx;
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesvoid InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
for (unsigned I = 0; I < NumImplicitUses; ++I) { for (unsigned I = 0; I < NumImplicitUses; ++I) {
ReadDescriptor &Read = ID.Reads[CurrentUse + I]; ReadDescriptor &Read = ID.Reads[CurrentUse + I];
Read.OpIndex = ~I; Read.OpIndex = ~I;
Read.UseIndex = NumExplicitUses + I; Read.UseIndex = NumExplicitUses + I;
Read.RegisterID = MCDesc.getImplicitUses()[I]; Read.RegisterID = MCDesc.getImplicitUses()[I];
Read.SchedClassID = SchedClassID; Read.SchedClassID = SchedClassID;
LLVM_DEBUG(dbgs() << "\t\t[Use][I] OpIdx=" << ~Read.OpIndex LLVM_DEBUG(dbgs() << "\t\t[Use][I] OpIdx=" << ~Read.OpIndex
<< ", UseIndex=" << Read.UseIndex << ", RegisterID=" << ", UseIndex=" << Read.UseIndex << ", RegisterID="
<< MRI.getName(Read.RegisterID) << '\n'); << MCRI.getName(Read.RegisterID) << '\n');
} }
CurrentUse += NumImplicitUses; CurrentUse += NumImplicitUses;
bool AssumeDefsOnly = MCDesc.variadicOpsAreDefs(); bool AssumeDefsOnly = MCDesc.variadicOpsAreDefs();
for (unsigned I = 0, OpIndex = MCDesc.getNumOperands(); for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
I < NumVariadicOps && !AssumeDefsOnly; ++I, ++OpIndex) { I < NumVariadicOps && !AssumeDefsOnly; ++I, ++OpIndex) {
const MCOperand &Op = MCI.getOperand(OpIndex); const MCOperand &Op = MCI.getOperand(OpIndex);
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 LinesInstrBuilder::createInstruction(const MCInst &MCI,
// Track register writes that implicitly clear the upper portion of the // Track register writes that implicitly clear the upper portion of the
// underlying super-registers using an APInt. // underlying super-registers using an APInt.
APInt WriteMask(D.Writes.size(), 0); APInt WriteMask(D.Writes.size(), 0);
// Now query the MCInstrAnalysis object to obtain information about which // Now query the MCInstrAnalysis object to obtain information about which
// register writes implicitly clear the upper portion of a super-register. // register writes implicitly clear the upper portion of a super-register.
if (MCIA) if (MCIA)
MCIA->clearsSuperRegisters(MRI, MCI, WriteMask); MCIA->clearsSuperRegisters(MCRI, MCI, WriteMask);
// Initialize writes. // Initialize writes.
unsigned WriteIndex = 0; unsigned WriteIndex = 0;
Idx = 0U; Idx = 0U;
for (const WriteDescriptor &WD : D.Writes) { for (const WriteDescriptor &WD : D.Writes) {
RegID = WD.isImplicitWrite() ? WD.RegisterID RegID = WD.isImplicitWrite() ? WD.RegisterID
: MCI.getOperand(WD.OpIndex).getReg(); : MCI.getOperand(WD.OpIndex).getReg();
// Check if this is a optional definition that references NoReg. // Check if this is a optional definition that references NoReg.
Show All 29 Lines

llvm/lib/MCA/Stages/DispatchStage.cpp

Show All 20 Lines
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#define DEBUG_TYPE "llvm-mca" #define DEBUG_TYPE "llvm-mca"
namespace llvm { namespace llvm {
namespace mca { namespace mca {
DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget, DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
unsigned MaxDispatchWidth, RetireControlUnit &R, unsigned MaxDispatchWidth, RetireControlUnit &R,
RegisterFile &F) RegisterFile &F)
: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) { CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) {
if (!DispatchWidth) if (!DispatchWidth)
DispatchWidth = Subtarget.getSchedModel().IssueWidth; DispatchWidth = Subtarget.getSchedModel().IssueWidth;
} }
▲ Show 20 Lines • Show All 149 Lines • Show Last 20 Lines

llvm/lib/Object/ModuleSymbolTable.cpp

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 LinesinitializeRecordStreamer(const Module &M,
if (InlineAsm.empty()) if (InlineAsm.empty())
return; return;
std::string Err; std::string Err;
const Triple TT(M.getTargetTriple()); const Triple TT(M.getTargetTriple());
const Target *T = TargetRegistry::lookupTarget(TT.str(), Err); const Target *T = TargetRegistry::lookupTarget(TT.str(), Err);
assert(T && T->hasMCAsmParser()); assert(T && T->hasMCAsmParser());
std::unique_ptr<MCRegisterInfo> MRI(T->createMCRegInfo(TT.str())); std::unique_ptr<MCRegisterInfo> MCRI(T->createMCRegInfo(TT.str()));
if (!MRI) if (!MCRI)
return; return;
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<MCAsmInfo> MAI(T->createMCAsmInfo(*MRI, TT.str(), MCOptions)); std::unique_ptr<MCAsmInfo> MAI(
T->createMCAsmInfo(*MCRI, TT.str(), MCOptions));
if (!MAI) if (!MAI)
return; return;
std::unique_ptr<MCSubtargetInfo> STI( std::unique_ptr<MCSubtargetInfo> STI(
T->createMCSubtargetInfo(TT.str(), "", "")); T->createMCSubtargetInfo(TT.str(), "", ""));
if (!STI) if (!STI)
return; return;
std::unique_ptr<MCInstrInfo> MCII(T->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MCII(T->createMCInstrInfo());
if (!MCII) if (!MCII)
return; return;
std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(InlineAsm)); std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(InlineAsm));
SourceMgr SrcMgr; SourceMgr SrcMgr;
SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc()); SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc());
MCContext MCCtx(TT, MAI.get(), MRI.get(), STI.get(), &SrcMgr); MCContext MCCtx(TT, MAI.get(), MCRI.get(), STI.get(), &SrcMgr);
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
T->createMCObjectFileInfo(MCCtx, /*PIC=*/false)); T->createMCObjectFileInfo(MCCtx, /*PIC=*/false));
MOFI->setSDKVersion(M.getSDKVersion()); MOFI->setSDKVersion(M.getSDKVersion());
MCCtx.setObjectFileInfo(MOFI.get()); MCCtx.setObjectFileInfo(MOFI.get());
RecordStreamer Streamer(MCCtx, M); RecordStreamer Streamer(MCCtx, M);
T->createNullTargetStreamer(Streamer); T->createNullTargetStreamer(Streamer);
std::unique_ptr<MCAsmParser> Parser( std::unique_ptr<MCAsmParser> Parser(
▲ Show 20 Lines • Show All 116 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,644 Lines • ▼ Show 20 Lines
#include "AArch64GenAsmMatcher.inc" #include "AArch64GenAsmMatcher.inc"
// FIXME? Maybe this could be a TableGen attribute on some registers and // FIXME? Maybe this could be a TableGen attribute on some registers and
// this table could be generated automatically from RegInfo. // this table could be generated automatically from RegInfo.
Register AArch64TargetLowering:: Register AArch64TargetLowering::
getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const {
Register Reg = MatchRegisterName(RegName); Register Reg = MatchRegisterName(RegName);
if (AArch64::X1 <= Reg && Reg <= AArch64::X28) { if (AArch64::X1 <= Reg && Reg <= AArch64::X28) {
const MCRegisterInfo *MRI = Subtarget->getRegisterInfo(); const MCRegisterInfo *MCRI = Subtarget->getRegisterInfo();
unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false); unsigned DwarfRegNum = MCRI->getDwarfRegNum(Reg, false);
if (!Subtarget->isXRegisterReserved(DwarfRegNum)) if (!Subtarget->isXRegisterReserved(DwarfRegNum))
Reg = 0; Reg = 0;
} }
if (Reg) if (Reg)
return Reg; return Reg;
report_fatal_error(Twine("Invalid register name \"" report_fatal_error(Twine("Invalid register name \""
+ StringRef(RegName) + "\".")); + StringRef(RegName) + "\"."));
} }
▲ Show 20 Lines • Show All 14,364 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,990 Lines • ▼ Show 20 Lines MachineInstr *STRXpre = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
.addReg(AArch64::SP, RegState::Define) .addReg(AArch64::SP, RegState::Define)
.addReg(AArch64::LR) .addReg(AArch64::LR)
.addReg(AArch64::SP) .addReg(AArch64::SP)
.addImm(-16); .addImm(-16);
It = MBB.insert(It, STRXpre); It = MBB.insert(It, STRXpre);
if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo(MF)) { if (MF.getInfo<AArch64FunctionInfo>()->needsDwarfUnwindInfo(MF)) {
const TargetSubtargetInfo &STI = MF.getSubtarget(); const TargetSubtargetInfo &STI = MF.getSubtarget();
const MCRegisterInfo *MRI = STI.getRegisterInfo(); const MCRegisterInfo *MCRI = STI.getRegisterInfo();
unsigned DwarfReg = MRI->getDwarfRegNum(AArch64::LR, true); unsigned DwarfReg = MCRI->getDwarfRegNum(AArch64::LR, true);
// Add a CFI saying the stack was moved 16 B down. // Add a CFI saying the stack was moved 16 B down.
int64_t StackPosEntry = int64_t StackPosEntry =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 16)); MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 16));
BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
.addCFIIndex(StackPosEntry) .addCFIIndex(StackPosEntry)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

Show First 20 Lines • Show All 535 Lines • ▼ Show 20 Linesenum CompactUnwindEncodings {
UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400, UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
}; };
} // end CU namespace } // end CU namespace
// FIXME: This should be in a separate file. // FIXME: This should be in a separate file.
class DarwinAArch64AsmBackend : public AArch64AsmBackend { class DarwinAArch64AsmBackend : public AArch64AsmBackend {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
/// Encode compact unwind stack adjustment for frameless functions. /// Encode compact unwind stack adjustment for frameless functions.
/// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
/// The stack size always needs to be 16 byte aligned. /// The stack size always needs to be 16 byte aligned.
uint32_t encodeStackAdjustment(uint32_t StackSize) const { uint32_t encodeStackAdjustment(uint32_t StackSize) const {
return (StackSize / 16) << 12; return (StackSize / 16) << 12;
} }
public: public:
DarwinAArch64AsmBackend(const Target &T, const Triple &TT, DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {} : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MCRI(MCRI) {}
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override { createObjectTargetWriter() const override {
uint32_t CPUType = cantFail(MachO::getCPUType(TheTriple)); uint32_t CPUType = cantFail(MachO::getCPUType(TheTriple));
uint32_t CPUSubType = cantFail(MachO::getCPUSubType(TheTriple)); uint32_t CPUSubType = cantFail(MachO::getCPUSubType(TheTriple));
return createAArch64MachObjectWriter(CPUType, CPUSubType, return createAArch64MachObjectWriter(CPUType, CPUSubType,
TheTriple.isArch32Bit()); TheTriple.isArch32Bit());
} }
Show All 14 Lines for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
switch (Inst.getOperation()) { switch (Inst.getOperation()) {
default: default:
// Cannot handle this directive: bail out. // Cannot handle this directive: bail out.
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
case MCCFIInstruction::OpDefCfa: { case MCCFIInstruction::OpDefCfa: {
// Defines a frame pointer. // Defines a frame pointer.
unsigned XReg = unsigned XReg =
getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true)); getXRegFromWReg(*MCRI.getLLVMRegNum(Inst.getRegister(), true));
// Other CFA registers than FP are not supported by compact unwind. // Other CFA registers than FP are not supported by compact unwind.
// Fallback on DWARF. // Fallback on DWARF.
// FIXME: When opt-remarks are supported in MC, add a remark to notify // FIXME: When opt-remarks are supported in MC, add a remark to notify
// the user. // the user.
if (XReg != AArch64::FP) if (XReg != AArch64::FP)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
if (i + 2 >= e) if (i + 2 >= e)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
const MCCFIInstruction &LRPush = Instrs[++i]; const MCCFIInstruction &LRPush = Instrs[++i];
if (LRPush.getOperation() != MCCFIInstruction::OpOffset) if (LRPush.getOperation() != MCCFIInstruction::OpOffset)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
const MCCFIInstruction &FPPush = Instrs[++i]; const MCCFIInstruction &FPPush = Instrs[++i];
if (FPPush.getOperation() != MCCFIInstruction::OpOffset) if (FPPush.getOperation() != MCCFIInstruction::OpOffset)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
if (FPPush.getOffset() + 8 != LRPush.getOffset()) if (FPPush.getOffset() + 8 != LRPush.getOffset())
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
CurOffset = FPPush.getOffset(); CurOffset = FPPush.getOffset();
unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true); unsigned LRReg = *MCRI.getLLVMRegNum(LRPush.getRegister(), true);
unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true); unsigned FPReg = *MCRI.getLLVMRegNum(FPPush.getRegister(), true);
LRReg = getXRegFromWReg(LRReg); LRReg = getXRegFromWReg(LRReg);
FPReg = getXRegFromWReg(FPReg); FPReg = getXRegFromWReg(FPReg);
if (LRReg != AArch64::LR || FPReg != AArch64::FP) if (LRReg != AArch64::LR || FPReg != AArch64::FP)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
// Indicate that the function has a frame. // Indicate that the function has a frame.
CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME; CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
HasFP = true; HasFP = true;
break; break;
} }
case MCCFIInstruction::OpDefCfaOffset: { case MCCFIInstruction::OpDefCfaOffset: {
if (StackSize != 0) if (StackSize != 0)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
StackSize = std::abs(Inst.getOffset()); StackSize = std::abs(Inst.getOffset());
break; break;
} }
case MCCFIInstruction::OpOffset: { case MCCFIInstruction::OpOffset: {
// Registers are saved in pairs. We expect there to be two consecutive // Registers are saved in pairs. We expect there to be two consecutive
// `.cfi_offset' instructions with the appropriate registers specified. // `.cfi_offset' instructions with the appropriate registers specified.
unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); unsigned Reg1 = *MCRI.getLLVMRegNum(Inst.getRegister(), true);
if (i + 1 == e) if (i + 1 == e)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
if (CurOffset != 0 && Inst.getOffset() != CurOffset - 8) if (CurOffset != 0 && Inst.getOffset() != CurOffset - 8)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
CurOffset = Inst.getOffset(); CurOffset = Inst.getOffset();
const MCCFIInstruction &Inst2 = Instrs[++i]; const MCCFIInstruction &Inst2 = Instrs[++i];
if (Inst2.getOperation() != MCCFIInstruction::OpOffset) if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); unsigned Reg2 = *MCRI.getLLVMRegNum(Inst2.getRegister(), true);
if (Inst2.getOffset() != CurOffset - 8) if (Inst2.getOffset() != CurOffset - 8)
return CU::UNWIND_ARM64_MODE_DWARF; return CU::UNWIND_ARM64_MODE_DWARF;
CurOffset = Inst2.getOffset(); CurOffset = Inst2.getOffset();
// N.B. The encodings must be in register number order, and the X // N.B. The encodings must be in register number order, and the X
// registers before the D registers. // registers before the D registers.
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Linespublic:
createObjectTargetWriter() const override { createObjectTargetWriter() const override {
return createAArch64WinCOFFObjectWriter(TheTriple); return createAArch64WinCOFFObjectWriter(TheTriple);
} }
}; };
} }
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSBinFormatMachO()) { if (TheTriple.isOSBinFormatMachO()) {
return new DarwinAArch64AsmBackend(T, TheTriple, MRI); return new DarwinAArch64AsmBackend(T, TheTriple, MCRI);
} }
if (TheTriple.isOSBinFormatCOFF()) if (TheTriple.isOSBinFormatCOFF())
return new COFFAArch64AsmBackend(T, TheTriple); return new COFFAArch64AsmBackend(T, TheTriple);
assert(TheTriple.isOSBinFormatELF() && "Invalid target"); assert(TheTriple.isOSBinFormatELF() && "Invalid target");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32; bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true, return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,
IsILP32); IsILP32);
} }
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
assert(TheTriple.isOSBinFormatELF() && assert(TheTriple.isOSBinFormatELF() &&
"Big endian is only supported for ELF targets!"); "Big endian is only supported for ELF targets!");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32; bool IsILP32 = STI.getTargetTriple().getEnvironment() == Triple::GNUILP32;
return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false, return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,
IsILP32); IsILP32);
} }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

Show All 17 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
#include "../Utils/AArch64BaseInfo.h" #include "../Utils/AArch64BaseInfo.h"
namespace llvm { namespace llvm {
class AArch64InstPrinter : public MCInstPrinter { class AArch64InstPrinter : public MCInstPrinter {
public: public:
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
bool applyTargetSpecificCLOption(StringRef Opt) override; bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const;
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Linesprotected:
template <unsigned ImmIs0, unsigned ImmIs1> template <unsigned ImmIs0, unsigned ImmIs1>
void printExactFPImm(const MCInst *MI, unsigned OpNum, void printExactFPImm(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
}; };
class AArch64AppleInstPrinter : public AArch64InstPrinter { class AArch64AppleInstPrinter : public AArch64InstPrinter {
public: public:
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
bool printAliasInstr(const MCInst *MI, uint64_t Address, bool printAliasInstr(const MCInst *MI, uint64_t Address,
Show All 15 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

Show All 37 Lines
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "AArch64GenAsmWriter.inc" #include "AArch64GenAsmWriter.inc"
#define GET_INSTRUCTION_NAME #define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "AArch64GenAsmWriter1.inc" #include "AArch64GenAsmWriter1.inc"
AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: AArch64InstPrinter(MAI, MII, MRI) {} : AArch64InstPrinter(MAI, MII, MCRI) {}
bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) { bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
if (Opt == "no-aliases") { if (Opt == "no-aliases") {
PrintAliases = false; PrintAliases = false;
return true; return true;
} }
return false; return false;
} }
▲ Show 20 Lines • Show All 775 Lines • ▼ Show 20 Lines#endif
unsigned PRFOp = MI->getOperand(0).getImm(); unsigned PRFOp = MI->getOperand(0).getImm();
unsigned Mask = 0x18; // 0b11000 unsigned Mask = 0x18; // 0b11000
if ((PRFOp & Mask) != Mask) if ((PRFOp & Mask) != Mask)
return false; // Rt != '11xxx', it's a PRFM instruction. return false; // Rt != '11xxx', it's a PRFM instruction.
unsigned Rm = MI->getOperand(2).getReg(); unsigned Rm = MI->getOperand(2).getReg();
// "Rm" must be a 64-bit GPR for RPRFM. // "Rm" must be a 64-bit GPR for RPRFM.
if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm)) if (MCRI.getRegClass(AArch64::GPR32RegClassID).contains(Rm))
Rm = MRI.getMatchingSuperReg(Rm, AArch64::sub_32, Rm = MCRI.getMatchingSuperReg(Rm, AArch64::sub_32,
&MRI.getRegClass(AArch64::GPR64RegClassID)); &MCRI.getRegClass(AArch64::GPR64RegClassID));
unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>". unsigned SignExtend = MI->getOperand(3).getImm(); // encoded in "option<2>".
unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S". unsigned Shift = MI->getOperand(4).getImm(); // encoded in "S".
assert((SignExtend <= 1) && "sign extend should be a single bit!"); assert((SignExtend <= 1) && "sign extend should be a single bit!");
assert((Shift <= 1) && "Shift should be a single bit!"); assert((Shift <= 1) && "Shift should be a single bit!");
unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0; unsigned Option0 = (Opcode == AArch64::PRFMroX) ? 1 : 0;
▲ Show 20 Lines • Show All 733 Lines • ▼ Show 20 Linesvoid AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
raw_ostream &O) { raw_ostream &O) {
static_assert(size == 64 || size == 32, static_assert(size == 64 || size == 32,
"Template parameter must be either 32 or 64"); "Template parameter must be either 32 or 64");
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
unsigned Even = MRI.getSubReg(Reg, Sube); unsigned Even = MCRI.getSubReg(Reg, Sube);
unsigned Odd = MRI.getSubReg(Reg, Subo); unsigned Odd = MCRI.getSubReg(Reg, Subo);
printRegName(O, Even); printRegName(O, Even);
O << ", "; O << ", ";
printRegName(O, Odd); printRegName(O, Odd);
} }
void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum, void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
Show All 25 Linesvoid AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
StringRef LayoutSuffix) { StringRef LayoutSuffix) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
O << "{ "; O << "{ ";
// Work out how many registers there are in the list (if there is an actual // Work out how many registers there are in the list (if there is an actual
// list). // list).
unsigned NumRegs = 1; unsigned NumRegs = 1;
if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || if (MCRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || MCRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || MCRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || MCRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) MCRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
NumRegs = 2; NumRegs = 2;
else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || else if (MCRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || MCRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) MCRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
NumRegs = 3; NumRegs = 3;
else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || else if (MCRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || MCRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) || MCRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) MCRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
NumRegs = 4; NumRegs = 4;
unsigned Stride = 1; unsigned Stride = 1;
if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) if (MCRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
Stride = 8; Stride = 8;
else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) else if (MCRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
Stride = 4; Stride = 4;
// Now forget about the list and find out what the first register is. // Now forget about the list and find out what the first register is.
if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::dsub0))
Reg = FirstReg; Reg = FirstReg;
else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::qsub0))
Reg = FirstReg; Reg = FirstReg;
else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::zsub0))
Reg = FirstReg; Reg = FirstReg;
else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) else if (unsigned FirstReg = MCRI.getSubReg(Reg, AArch64::psub0))
Reg = FirstReg; Reg = FirstReg;
// If it's a D-reg, we need to promote it to the equivalent Q-reg before // If it's a D-reg, we need to promote it to the equivalent Q-reg before
// printing (otherwise getRegisterName fails). // printing (otherwise getRegisterName fails).
if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { if (MCRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
const MCRegisterClass &FPR128RC = const MCRegisterClass &FPR128RC =
MRI.getRegClass(AArch64::FPR128RegClassID); MCRI.getRegClass(AArch64::FPR128RegClassID);
Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); Reg = MCRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
} }
if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || if ((MCRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && MCRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) &&
NumRegs > 1 && Stride == 1 && NumRegs > 1 && Stride == 1 &&
// Do not print the range when the last register is lower than the first. // Do not print the range when the last register is lower than the first.
// Because it is a wrap-around register. // Because it is a wrap-around register.
Reg < getNextVectorRegister(Reg, NumRegs - 1)) { Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
printRegName(O, Reg); printRegName(O, Reg);
O << LayoutSuffix; O << LayoutSuffix;
if (NumRegs > 1) { if (NumRegs > 1) {
// Set of two sve registers should be separated by ',' // Set of two sve registers should be separated by ','
StringRef split_char = NumRegs == 2 ? ", " : " - "; StringRef split_char = NumRegs == 2 ? ", " : " - ";
O << split_char; O << split_char;
printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1))); printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
O << LayoutSuffix; O << LayoutSuffix;
} }
} else { } else {
for (unsigned i = 0; i < NumRegs; for (unsigned i = 0; i < NumRegs;
++i, Reg = getNextVectorRegister(Reg, Stride)) { ++i, Reg = getNextVectorRegister(Reg, Stride)) {
// wrap-around sve register // wrap-around sve register
if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || if (MCRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) MCRI.getRegClass(AArch64::PPRRegClassID).contains(Reg))
printRegName(O, Reg); printRegName(O, Reg);
else else
printRegName(O, Reg, AArch64::vreg); printRegName(O, Reg, AArch64::vreg);
O << LayoutSuffix; O << LayoutSuffix;
if (i + 1 != NumRegs) if (i + 1 != NumRegs)
O << ", "; O << ", ";
} }
} }
▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Linesvoid AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
printRegName(O, getWRegFromXReg(Reg)); printRegName(O, getWRegFromXReg(Reg));
} }
void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum, void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
printRegName(O, MRI.getSubReg(Reg, AArch64::x8sub_0)); printRegName(O, MCRI.getSubReg(Reg, AArch64::x8sub_0));
} }
void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum, void AArch64InstPrinter::printSyspXzrPair(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
assert(Reg == AArch64::XZR && assert(Reg == AArch64::XZR &&
"MC representation of SyspXzrPair should be XZR"); "MC representation of SyspXzrPair should be XZR");
O << getRegisterName(Reg) << ", " << getRegisterName(Reg); O << getRegisterName(Reg) << ", " << getRegisterName(Reg);
} }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

Show All 33 Lines
class MCTargetStreamer; class MCTargetStreamer;
class Target; class Target;
class Triple; class Triple;
MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T, MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createAArch64beAsmBackend(const Target &T, MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32); createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
bool IsILP32); bool IsILP32);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAArch64WinCOFFObjectWriter(const Triple &TheTriple); createAArch64WinCOFFObjectWriter(const Triple &TheTriple);
MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S, MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
bool isVerboseAsm); bool isVerboseAsm);
namespace AArch64_MC { namespace AArch64_MC {
void initLLVMToCVRegMapping(MCRegisterInfo *MRI); void initLLVMToCVRegMapping(MCRegisterInfo *MCRI);
bool isQForm(const MCInst &MI, const MCInstrInfo *MCII); bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
} }
namespace AArch64 { namespace AArch64 {
enum OperandType { enum OperandType {
OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET, OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET,
}; };
Show All 20 Lines

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines if (CPU.empty()) {
if (TT.isArm64e()) if (TT.isArm64e())
CPU = "apple-a12"; CPU = "apple-a12";
} }
return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MCRI) {
// Mapping from CodeView to MC register id. // Mapping from CodeView to MC register id.
static const struct { static const struct {
codeview::RegisterId CVReg; codeview::RegisterId CVReg;
MCPhysReg Reg; MCPhysReg Reg;
} RegMap[] = { } RegMap[] = {
{codeview::RegisterId::ARM64_W0, AArch64::W0}, {codeview::RegisterId::ARM64_W0, AArch64::W0},
{codeview::RegisterId::ARM64_W1, AArch64::W1}, {codeview::RegisterId::ARM64_W1, AArch64::W1},
{codeview::RegisterId::ARM64_W2, AArch64::W2}, {codeview::RegisterId::ARM64_W2, AArch64::W2},
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines MCPhysReg Reg;
{codeview::RegisterId::ARM64_H26, AArch64::H26}, {codeview::RegisterId::ARM64_H26, AArch64::H26},
{codeview::RegisterId::ARM64_H27, AArch64::H27}, {codeview::RegisterId::ARM64_H27, AArch64::H27},
{codeview::RegisterId::ARM64_H28, AArch64::H28}, {codeview::RegisterId::ARM64_H28, AArch64::H28},
{codeview::RegisterId::ARM64_H29, AArch64::H29}, {codeview::RegisterId::ARM64_H29, AArch64::H29},
{codeview::RegisterId::ARM64_H30, AArch64::H30}, {codeview::RegisterId::ARM64_H30, AArch64::H30},
{codeview::RegisterId::ARM64_H31, AArch64::H31}, {codeview::RegisterId::ARM64_H31, AArch64::H31},
}; };
for (const auto &I : RegMap) for (const auto &I : RegMap)
MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); MCRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
} }
bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) { bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
return llvm::any_of(MI, [&](const MCOperand &Op) { return llvm::any_of(MI, [&](const MCOperand &Op) {
return Op.isReg() && FPR128.contains(Op.getReg()); return Op.isReg() && FPR128.contains(Op.getReg());
}); });
} }
Show All 18 Lines
static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitAArch64MCRegisterInfo(X, AArch64::LR); InitAArch64MCRegisterInfo(X, AArch64::LR);
AArch64_MC::initLLVMToCVRegMapping(X); AArch64_MC::initLLVMToCVRegMapping(X);
return X; return X;
} }
static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TheTriple, const Triple &TheTriple,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI; MCAsmInfo *MAI;
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32); MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
else if (TheTriple.isWindowsMSVCEnvironment()) else if (TheTriple.isWindowsMSVCEnvironment())
MAI = new AArch64MCAsmInfoMicrosoftCOFF(); MAI = new AArch64MCAsmInfoMicrosoftCOFF();
else if (TheTriple.isOSBinFormatCOFF()) else if (TheTriple.isOSBinFormatCOFF())
MAI = new AArch64MCAsmInfoGNUCOFF(); MAI = new AArch64MCAsmInfoGNUCOFF();
else { else {
assert(TheTriple.isOSBinFormatELF() && "Invalid target"); assert(TheTriple.isOSBinFormatELF() && "Invalid target");
MAI = new AArch64MCAsmInfoELF(TheTriple); MAI = new AArch64MCAsmInfoELF(TheTriple);
} }
// Initial state of the frame pointer is SP. // Initial state of the frame pointer is SP.
unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true); unsigned Reg = MCRI.getDwarfRegNum(AArch64::SP, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new AArch64InstPrinter(MAI, MII, MRI); return new AArch64InstPrinter(MAI, MII, MCRI);
if (SyntaxVariant == 1) if (SyntaxVariant == 1)
return new AArch64AppleInstPrinter(MAI, MII, MRI); return new AArch64AppleInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
std::unique_ptr<MCAsmBackend> &&TAB, std::unique_ptr<MCAsmBackend> &&TAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter, std::unique_ptr<MCCodeEmitter> &&Emitter,
▲ Show 20 Lines • Show All 141 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 537 Lines • ▼ Show 20 LinesAMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
FS, Options, getEffectiveRelocModel(RM), FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel), getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
TLOF(createTLOF(getTargetTriple())) { TLOF(createTLOF(getTargetTriple())) {
initAsmInfo(); initAsmInfo();
if (TT.getArch() == Triple::amdgcn) { if (TT.getArch() == Triple::amdgcn) {
if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64")) if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64)); MCRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave64));
else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32")) else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
MRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32)); MCRI.reset(llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour::Wave32));
} }
} }
bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false; bool AMDGPUTargetMachine::EnableLateStructurizeCFG = false;
bool AMDGPUTargetMachine::EnableFunctionCalls = false; bool AMDGPUTargetMachine::EnableFunctionCalls = false;
bool AMDGPUTargetMachine::EnableLowerModuleLDS = true; bool AMDGPUTargetMachine::EnableLowerModuleLDS = true;
AMDGPUTargetMachine::~AMDGPUTargetMachine() = default; AMDGPUTargetMachine::~AMDGPUTargetMachine() = default;
▲ Show 20 Lines • Show All 1,055 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,288 Lines • ▼ Show 20 Linesprivate:
bool ParseDirectiveAMDGCNTarget(); bool ParseDirectiveAMDGCNTarget();
bool ParseDirectiveAMDHSAKernel(); bool ParseDirectiveAMDHSAKernel();
bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor); bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
bool ParseDirectiveHSACodeObjectVersion(); bool ParseDirectiveHSACodeObjectVersion();
bool ParseDirectiveHSACodeObjectISA(); bool ParseDirectiveHSACodeObjectISA();
bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header); bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
bool ParseDirectiveAMDKernelCodeT(); bool ParseDirectiveAMDKernelCodeT();
// TODO: Possibly make subtargetHasRegister const. // TODO: Possibly make subtargetHasRegister const.
bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo); bool subtargetHasRegister(const MCRegisterInfo &MCRI, unsigned RegNo);
bool ParseDirectiveAMDGPUHsaKernel(); bool ParseDirectiveAMDGPUHsaKernel();
bool ParseDirectiveISAVersion(); bool ParseDirectiveISAVersion();
bool ParseDirectiveHSAMetadata(); bool ParseDirectiveHSAMetadata();
bool ParseDirectivePALMetadataBegin(); bool ParseDirectivePALMetadataBegin();
bool ParseDirectivePALMetadata(); bool ParseDirectivePALMetadata();
bool ParseDirectiveAMDGPULDS(); bool ParseDirectiveAMDGPULDS();
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines bool hasIntClamp() const {
return getFeatureBits()[AMDGPU::FeatureIntClamp]; return getFeatureBits()[AMDGPU::FeatureIntClamp];
} }
AMDGPUTargetStreamer &getTargetStreamer() { AMDGPUTargetStreamer &getTargetStreamer() {
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
return static_cast<AMDGPUTargetStreamer &>(TS); return static_cast<AMDGPUTargetStreamer &>(TS);
} }
const MCRegisterInfo *getMRI() const { const MCRegisterInfo *getMCRI() const {
// We need this const_cast because for some reason getContext() is not const // We need this const_cast because for some reason getContext() is not const
// in MCAsmParser. // in MCAsmParser.
return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo(); return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo();
} }
const MCInstrInfo *getMII() const { const MCInstrInfo *getMII() const {
return &MII; return &MII;
} }
▲ Show 20 Lines • Show All 523 Lines • ▼ Show 20 Lines MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :
(type == MVT::v2i16)? MVT::i16 : (type == MVT::v2i16)? MVT::i16 :
(type == MVT::v2f32)? MVT::f32 : type; (type == MVT::v2f32)? MVT::f32 : type;
APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val)); APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
return canLosslesslyConvertToFPType(FPLiteral, ExpectedType); return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);
} }
bool AMDGPUOperand::isRegClass(unsigned RCID) const { bool AMDGPUOperand::isRegClass(unsigned RCID) const {
return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); return isRegKind() &&
AsmParser->getMCRI()->getRegClass(RCID).contains(getReg());
} }
bool AMDGPUOperand::isVRegWithInputMods() const { bool AMDGPUOperand::isVRegWithInputMods() const {
return isRegClass(AMDGPU::VGPR_32RegClassID) || return isRegClass(AMDGPU::VGPR_32RegClassID) ||
// GFX90A allows DPP on 64-bit operands. // GFX90A allows DPP on 64-bit operands.
(isRegClass(AMDGPU::VReg_64RegClassID) && (isRegClass(AMDGPU::VReg_64RegClassID) &&
AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]); AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);
} }
▲ Show 20 Lines • Show All 1,577 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);
int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);
assert(VDataIdx != -1); assert(VDataIdx != -1);
if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray
return true; return true;
unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); unsigned VDataSize = AMDGPU::getRegOperandSize(getMCRI(), Desc, VDataIdx);
unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0; unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;
unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf; unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
if (DMask == 0) if (DMask == 0)
DMask = 1; DMask = 1;
bool IsPackedD16 = false; bool IsPackedD16 = false;
unsigned DataSize = unsigned DataSize =
(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask); (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);
Show All 40 Linesbool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
if (DimIdx == -1) if (DimIdx == -1)
return true; // intersect_ray return true; // intersect_ray
unsigned Dim = Inst.getOperand(DimIdx).getImm(); unsigned Dim = Inst.getOperand(DimIdx).getImm();
const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
bool IsNSA = SrsrcIdx - VAddr0Idx > 1; bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
unsigned ActualAddrSize = unsigned ActualAddrSize =
IsNSA ? SrsrcIdx - VAddr0Idx IsNSA ? SrsrcIdx - VAddr0Idx
: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; : AMDGPU::getRegOperandSize(getMCRI(), Desc, VAddr0Idx) / 4;
bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm()); bool IsA16 = (A16Idx != -1 && Inst.getOperand(A16Idx).getImm());
unsigned ExpectedAddrSize = unsigned ExpectedAddrSize =
AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16()); AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());
if (!IsNSA) { if (!IsNSA) {
if (ExpectedAddrSize > 12) if (ExpectedAddrSize > 12)
ExpectedAddrSize = 16; ExpectedAddrSize = 16;
▲ Show 20 Lines • Show All 566 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
if (DppCtrlIdx < 0) if (DppCtrlIdx < 0)
return true; return true;
unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm(); unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) { if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {
// DPP64 is supported for row_newbcast only. // DPP64 is supported for row_newbcast only.
int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
if (Src0Idx >= 0 && if (Src0Idx >= 0 &&
getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) { getMCRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands); SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
Error(S, "64 bit dpp only supports row_newbcast"); Error(S, "64 bit dpp only supports row_newbcast");
return false; return false;
} }
} }
return true; return true;
} }
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines if (NumLiterals > 1) {
return false; return false;
} }
return true; return true;
} }
// Returns -1 if not a register, 0 if VGPR and 1 if AGPR. // Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
const MCRegisterInfo *MRI) { const MCRegisterInfo *MCRI) {
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx); int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);
if (OpIdx < 0) if (OpIdx < 0)
return -1; return -1;
const MCOperand &Op = Inst.getOperand(OpIdx); const MCOperand &Op = Inst.getOperand(OpIdx);
if (!Op.isReg()) if (!Op.isReg())
return -1; return -1;
unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg(); auto Reg = Sub ? Sub : Op.getReg();
const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); const MCRegisterClass &AGPR32 = MCRI->getRegClass(AMDGPU::AGPR_32RegClassID);
return AGPR32.contains(Reg) ? 1 : 0; return AGPR32.contains(Reg) ? 1 : 0;
} }
bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const { bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
if ((TSFlags & (SIInstrFlags::FLAT | SIInstrFlags::MUBUF | if ((TSFlags & (SIInstrFlags::FLAT | SIInstrFlags::MUBUF |
SIInstrFlags::MTBUF | SIInstrFlags::MIMG | SIInstrFlags::MTBUF | SIInstrFlags::MIMG |
SIInstrFlags::DS)) == 0) SIInstrFlags::DS)) == 0)
return true; return true;
uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
: AMDGPU::OpName::vdata; : AMDGPU::OpName::vdata;
const MCRegisterInfo *MRI = getMRI(); const MCRegisterInfo *MCRI = getMCRI();
int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI); int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MCRI);
int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI); int DataAreg = IsAGPROperand(Inst, DataNameIdx, MCRI);
if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) { if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {
int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI); int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MCRI);
if (Data2Areg >= 0 && Data2Areg != DataAreg) if (Data2Areg >= 0 && Data2Areg != DataAreg)
return false; return false;
} }
auto FB = getFeatureBits(); auto FB = getFeatureBits();
if (FB[AMDGPU::FeatureGFX90AInsts]) { if (FB[AMDGPU::FeatureGFX90AInsts]) {
if (DataAreg < 0 || DstAreg < 0) if (DataAreg < 0 || DstAreg < 0)
return true; return true;
return DstAreg == DataAreg; return DstAreg == DataAreg;
} }
return DstAreg < 1 && DataAreg < 1; return DstAreg < 1 && DataAreg < 1;
} }
bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const { bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
auto FB = getFeatureBits(); auto FB = getFeatureBits();
if (!FB[AMDGPU::FeatureGFX90AInsts]) if (!FB[AMDGPU::FeatureGFX90AInsts])
return true; return true;
const MCRegisterInfo *MRI = getMRI(); const MCRegisterInfo *MCRI = getMCRI();
const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); const MCRegisterClass &VGPR32 = MCRI->getRegClass(AMDGPU::VGPR_32RegClassID);
const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID); const MCRegisterClass &AGPR32 = MCRI->getRegClass(AMDGPU::AGPR_32RegClassID);
for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) { for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
const MCOperand &Op = Inst.getOperand(I); const MCOperand &Op = Inst.getOperand(I);
if (!Op.isReg()) if (!Op.isReg())
continue; continue;
unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0);
if (!Sub) if (!Sub)
continue; continue;
if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
return false; return false;
if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1)) if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
return false; return false;
} }
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])
return true; return true;
int Opc = Inst.getOpcode(); int Opc = Inst.getOpcode();
if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi && if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&
Opc != AMDGPU::DS_GWS_SEMA_BR_vi) Opc != AMDGPU::DS_GWS_SEMA_BR_vi)
return true; return true;
const MCRegisterInfo *MRI = getMRI(); const MCRegisterInfo *MCRI = getMCRI();
const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID); const MCRegisterClass &VGPR32 = MCRI->getRegClass(AMDGPU::VGPR_32RegClassID);
int Data0Pos = int Data0Pos =
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0); AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);
assert(Data0Pos != -1); assert(Data0Pos != -1);
auto Reg = Inst.getOperand(Data0Pos).getReg(); auto Reg = Inst.getOperand(Data0Pos).getReg();
auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
if (RegIdx & 1) { if (RegIdx & 1) {
SMLoc RegLoc = getRegLoc(Reg, Operands); SMLoc RegLoc = getRegLoc(Reg, Operands);
Error(RegLoc, "vgpr must be even aligned"); Error(RegLoc, "vgpr must be even aligned");
▲ Show 20 Lines • Show All 1,198 Lines • ▼ Show 20 Lines if (IDVal == PALMD::AssemblerDirectiveBegin)
return ParseDirectivePALMetadataBegin(); return ParseDirectivePALMetadataBegin();
if (IDVal == PALMD::AssemblerDirective) if (IDVal == PALMD::AssemblerDirective)
return ParseDirectivePALMetadata(); return ParseDirectivePALMetadata();
return true; return true;
} }
bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MCRI,
unsigned RegNo) { unsigned RegNo) {
if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo)) if (MCRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
return isGFX9Plus(); return isGFX9Plus();
// GFX10+ has 2 more SGPRs 104 and 105. // GFX10+ has 2 more SGPRs 104 and 105.
if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo)) if (MCRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))
return hasSGPR104_SGPR105(); return hasSGPR104_SGPR105();
switch (RegNo) { switch (RegNo) {
case AMDGPU::SRC_SHARED_BASE_LO: case AMDGPU::SRC_SHARED_BASE_LO:
case AMDGPU::SRC_SHARED_BASE: case AMDGPU::SRC_SHARED_BASE:
case AMDGPU::SRC_SHARED_LIMIT_LO: case AMDGPU::SRC_SHARED_LIMIT_LO:
case AMDGPU::SRC_SHARED_LIMIT: case AMDGPU::SRC_SHARED_LIMIT:
case AMDGPU::SRC_PRIVATE_BASE_LO: case AMDGPU::SRC_PRIVATE_BASE_LO:
Show All 34 Lines case AMDGPU::FLAT_SCR_HI:
return false; return false;
default: default:
return true; return true;
} }
} }
// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
// SI/CI have. // SI/CI have.
if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo)) if (MCRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))
return hasSGPR102_SGPR103(); return hasSGPR102_SGPR103();
return true; return true;
} }
OperandMatchResultTy OperandMatchResultTy
AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic, AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic,
OperandMode Mode) { OperandMode Mode) {
▲ Show 20 Lines • Show All 3,498 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPUDisassembler // AMDGPUDisassembler
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class AMDGPUDisassembler : public MCDisassembler { class AMDGPUDisassembler : public MCDisassembler {
private: private:
std::unique_ptr<MCInstrInfo const> const MCII; std::unique_ptr<MCInstrInfo const> const MCII;
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const unsigned TargetMaxInstBytes; const unsigned TargetMaxInstBytes;
mutable ArrayRef<uint8_t> Bytes; mutable ArrayRef<uint8_t> Bytes;
mutable uint32_t Literal; mutable uint32_t Literal;
mutable bool HasLiteral; mutable bool HasLiteral;
public: public:
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
MCInstrInfo const *MCII); MCInstrInfo const *MCII);
▲ Show 20 Lines • Show All 212 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Show All 39 Lines
#define SGPR_MAX \ #define SGPR_MAX \
(isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
: AMDGPU::EncValues::SGPR_MAX_SI) : AMDGPU::EncValues::SGPR_MAX_SI)
using DecodeStatus = llvm::MCDisassembler::DecodeStatus; using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
MCContext &Ctx, MCContext &Ctx, MCInstrInfo const *MCII)
MCInstrInfo const *MCII) : : MCDisassembler(STI, Ctx), MCII(MCII), MCRI(*Ctx.getRegisterInfo()),
MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
// ToDo: AMDGPUDisassembler supports only VI ISA. // ToDo: AMDGPUDisassembler supports only VI ISA.
if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
report_fatal_error("Disassembly not yet supported for subtarget"); report_fatal_error("Disassembly not yet supported for subtarget");
} }
inline static MCDisassembler::DecodeStatus inline static MCDisassembler::DecodeStatus
addOperand(MCInst &Inst, const MCOperand& Opnd) { addOperand(MCInst &Inst, const MCOperand& Opnd) {
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
uint64_t Addr, const void *Decoder) { uint64_t Addr, const void *Decoder) {
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
} }
static bool IsAGPROperand(const MCInst &Inst, int OpIdx, static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
const MCRegisterInfo *MRI) { const MCRegisterInfo *MCRI) {
if (OpIdx < 0) if (OpIdx < 0)
return false; return false;
const MCOperand &Op = Inst.getOperand(OpIdx); const MCOperand &Op = Inst.getOperand(OpIdx);
if (!Op.isReg()) if (!Op.isReg())
return false; return false;
unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); unsigned Sub = MCRI->getSubReg(Op.getReg(), AMDGPU::sub0);
auto Reg = Sub ? Sub : Op.getReg(); auto Reg = Sub ? Sub : Op.getReg();
return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
} }
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm,
AMDGPUDisassembler::OpWidthTy Opw, AMDGPUDisassembler::OpWidthTy Opw,
const MCDisassembler *Decoder) { const MCDisassembler *Decoder) {
auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
if (!DAsm->isGFX90A()) { if (!DAsm->isGFX90A()) {
Imm &= 511; Imm &= 511;
} else { } else {
// If atomic has both vdata and vdst their register classes are tied. // If atomic has both vdata and vdst their register classes are tied.
// The bit is decoded along with the vdst, first operand. We need to // The bit is decoded along with the vdst, first operand. We need to
// change register class to AGPR if vdst was AGPR. // change register class to AGPR if vdst was AGPR.
// If a DS instruction has both data0 and data1 their register classes // If a DS instruction has both data0 and data1 their register classes
// are also tied. // are also tied.
unsigned Opc = Inst.getOpcode(); unsigned Opc = Inst.getOpcode();
uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
: AMDGPU::OpName::vdata; : AMDGPU::OpName::vdata;
const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = DAsm->getContext().getRegisterInfo();
int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
if ((int)Inst.getNumOperands() == DataIdx) { if ((int)Inst.getNumOperands() == DataIdx) {
int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (IsAGPROperand(Inst, DstIdx, MRI)) if (IsAGPROperand(Inst, DstIdx, MCRI))
Imm |= 512; Imm |= 512;
} }
if (TSFlags & SIInstrFlags::DS) { if (TSFlags & SIInstrFlags::DS) {
int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
if ((int)Inst.getNumOperands() == Data2Idx && if ((int)Inst.getNumOperands() == Data2Idx &&
IsAGPROperand(Inst, DataIdx, MRI)) IsAGPROperand(Inst, DataIdx, MCRI))
Imm |= 512; Imm |= 512;
} }
} }
return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
} }
static DecodeStatus static DecodeStatus
DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr,
▲ Show 20 Lines • Show All 604 Lines • ▼ Show 20 LinesDecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
// Widen the register to the correct number of enabled channels. // Widen the register to the correct number of enabled channels.
unsigned NewVdata = AMDGPU::NoRegister; unsigned NewVdata = AMDGPU::NoRegister;
if (DstSize != Info->VDataDwords) { if (DstSize != Info->VDataDwords) {
auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
// Get first subregister of VData // Get first subregister of VData
unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); unsigned VdataSub0 = MCRI.getSubReg(Vdata0, AMDGPU::sub0);
Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, NewVdata = MCRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
&MRI.getRegClass(DataRCID)); &MCRI.getRegClass(DataRCID));
if (NewVdata == AMDGPU::NoRegister) { if (NewVdata == AMDGPU::NoRegister) {
// It's possible to encode this such that the low register + enabled // It's possible to encode this such that the low register + enabled
// components exceeds the register count. // components exceeds the register count.
return MCDisassembler::Success; return MCDisassembler::Success;
} }
} }
// If not using NSA on GFX10+, widen address register to correct size. // If not using NSA on GFX10+, widen address register to correct size.
unsigned NewVAddr0 = AMDGPU::NoRegister; unsigned NewVAddr0 = AMDGPU::NoRegister;
if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) {
unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); unsigned VAddrSub0 = MCRI.getSubReg(VAddr0, AMDGPU::sub0);
VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass; auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass;
NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, NewVAddr0 = MCRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
&MRI.getRegClass(AddrRCID)); &MCRI.getRegClass(AddrRCID));
if (NewVAddr0 == AMDGPU::NoRegister) if (NewVAddr0 == AMDGPU::NoRegister)
return MCDisassembler::Success; return MCDisassembler::Success;
} }
MI.setOpcode(NewOpcode); MI.setOpcode(NewOpcode);
if (NewVdata != AMDGPU::NoRegister) { if (NewVdata != AMDGPU::NoRegister) {
MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
▲ Show 20 Lines • Show All 692 Lines • ▼ Show 20 Lines
// Bit 0 of DstY isn't stored in the instruction, because it's always the // Bit 0 of DstY isn't stored in the instruction, because it's always the
// opposite of bit 0 of DstX. // opposite of bit 0 of DstX.
MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst,
unsigned Val) const { unsigned Val) const {
int VDstXInd = int VDstXInd =
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);
assert(VDstXInd != -1); assert(VDstXInd != -1);
assert(Inst.getOperand(VDstXInd).isReg()); assert(Inst.getOperand(VDstXInd).isReg());
unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); unsigned XDstReg = MCRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
Val |= ~XDstReg & 1; Val |= ~XDstReg & 1;
auto Width = llvm::AMDGPUDisassembler::OPW32; auto Width = llvm::AMDGPUDisassembler::OPW32;
return createRegOperand(getVgprClassId(Width), Val); return createRegOperand(getVgprClassId(Width), Val);
} }
MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
using namespace AMDGPU; using namespace AMDGPU;
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llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Lines return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend,
ABIVersion); ABIVersion);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
getHsaAbiVersion(&STI).value_or(0)); getHsaAbiVersion(&STI).value_or(0));
} }

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Show All 13 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class MCInstrDesc; class MCInstrDesc;
class AMDGPUInstPrinter : public MCInstPrinter { class AMDGPUInstPrinter : public MCInstPrinter {
public: public:
AMDGPUInstPrinter(const MCAsmInfo &MAI, AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCInstrInfo &MII, const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Autogenerated by tblgen // Autogenerated by tblgen
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
static void printRegOperand(unsigned RegNo, raw_ostream &O, static void printRegOperand(unsigned RegNo, raw_ostream &O,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
private: private:
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmOperand(const MCInst *MI, unsigned OpNo, void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
▲ Show 20 Lines • Show All 214 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Lines if (isValidDfmtNfmt(Val, STI)) {
O << ']'; O << ']';
} else { } else {
O << " format:" << Val; O << " format:" << Val;
} }
} }
} }
void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O, void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
#if !defined(NDEBUG) #if !defined(NDEBUG)
switch (RegNo) { switch (RegNo) {
case AMDGPU::FP_REG: case AMDGPU::FP_REG:
case AMDGPU::SP_REG: case AMDGPU::SP_REG:
case AMDGPU::PRIVATE_RSRC_REG: case AMDGPU::PRIVATE_RSRC_REG:
llvm_unreachable("pseudo-register should not ever be emitted"); llvm_unreachable("pseudo-register should not ever be emitted");
case AMDGPU::SCC: case AMDGPU::SCC:
llvm_unreachable("pseudo scc should not ever be emitted"); llvm_unreachable("pseudo scc should not ever be emitted");
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void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand, void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
if (!FirstOperand) if (!FirstOperand)
O << ", "; O << ", ";
printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
? AMDGPU::VCC ? AMDGPU::VCC
: AMDGPU::VCC_LO, : AMDGPU::VCC_LO,
O, MRI); O, MCRI);
if (FirstOperand) if (FirstOperand)
O << ", "; O << ", ";
} }
void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
uint8_t Imm = MI->getOperand(OpNo).getImm(); uint8_t Imm = MI->getOperand(OpNo).getImm();
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesvoid AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
if (OpNo >= MI->getNumOperands()) { if (OpNo >= MI->getNumOperands()) {
O << "/*Missing OP" << OpNo << "*/"; O << "/*Missing OP" << OpNo << "*/";
return; return;
} }
const MCOperand &Op = MI->getOperand(OpNo); const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) { if (Op.isReg()) {
printRegOperand(Op.getReg(), O, MRI); printRegOperand(Op.getReg(), O, MCRI);
// Check if operand register class contains register used. // Check if operand register class contains register used.
// Intention: print disassembler message when invalid code is decoded, // Intention: print disassembler message when invalid code is decoded,
// for example sgpr register used in VReg or VISrc(VReg or imm) operand. // for example sgpr register used in VReg or VISrc(VReg or imm) operand.
int RCID = Desc.operands()[OpNo].RegClass; int RCID = Desc.operands()[OpNo].RegClass;
if (RCID != -1) { if (RCID != -1) {
const MCRegisterClass RC = MRI.getRegClass(RCID); const MCRegisterClass RC = MCRI.getRegClass(RCID);
auto Reg = mc2PseudoReg(Op.getReg()); auto Reg = mc2PseudoReg(Op.getReg());
if (!RC.contains(Reg) && !isInlineValue(Reg)) { if (!RC.contains(Reg) && !isInlineValue(Reg)) {
O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC) O << "/*Invalid register, operand has \'" << MCRI.getRegClassName(&RC)
<< "\' register class*/"; << "\' register class*/";
} }
} }
} else if (Op.isImm()) { } else if (Op.isImm()) {
const uint8_t OpTy = Desc.operands()[OpNo].OperandType; const uint8_t OpTy = Desc.operands()[OpNo].OperandType;
switch (OpTy) { switch (OpTy) {
case AMDGPU::OPERAND_REG_IMM_INT32: case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_FP32: case AMDGPU::OPERAND_REG_IMM_FP32:
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesvoid AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
} else if (Op.isDFPImm()) { } else if (Op.isDFPImm()) {
double Value = bit_cast<double>(Op.getDFPImm()); double Value = bit_cast<double>(Op.getDFPImm());
// We special case 0.0 because otherwise it will be printed as an integer. // We special case 0.0 because otherwise it will be printed as an integer.
if (Value == 0.0) if (Value == 0.0)
O << "0.0"; O << "0.0";
else { else {
const MCInstrDesc &Desc = MII.get(MI->getOpcode()); const MCInstrDesc &Desc = MII.get(MI->getOpcode());
int RCID = Desc.operands()[OpNo].RegClass; int RCID = Desc.operands()[OpNo].RegClass;
unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); unsigned RCBits = AMDGPU::getRegBitWidth(MCRI.getRegClass(RCID));
if (RCBits == 32) if (RCBits == 32)
printImmediate32(FloatToBits(Value), STI, O); printImmediate32(FloatToBits(Value), STI, O);
else if (RCBits == 64) else if (RCBits == 64)
printImmediate64(DoubleToBits(Value), STI, O); printImmediate64(DoubleToBits(Value), STI, O);
else else
llvm_unreachable("Invalid register class size"); llvm_unreachable("Invalid register class size");
} }
} else if (Op.isExpr()) { } else if (Op.isExpr()) {
▲ Show 20 Lines • Show All 336 Lines • ▼ Show 20 Linesvoid AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
// If compr is set, print as src0, src0, src1, src1 // If compr is set, print as src0, src0, src1, src1
if (MI->getOperand(ComprIdx).getImm()) if (MI->getOperand(ComprIdx).getImm())
OpNo = OpNo - N + N / 2; OpNo = OpNo - N + N / 2;
if (En & (1 << N)) if (En & (1 << N))
printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI); printRegOperand(MI->getOperand(OpNo).getReg(), O, MCRI);
else else
O << "off"; O << "off";
} }
void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
printExpSrcN(MI, OpNo, STI, O, 0); printExpSrcN(MI, OpNo, STI, O, 0);
▲ Show 20 Lines • Show All 515 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

Show All 31 Lines
MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour); MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
bool HasRelocationAddend, uint8_t ABIVersion); bool HasRelocationAddend, uint8_t ABIVersion);
} // End llvm namespace } // End llvm namespace
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
Show All 11 Lines

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines if (TT.getArch() == Triple::r600)
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T, static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (T.getArch() == Triple::r600) if (T.getArch() == Triple::r600)
return new R600InstPrinter(MAI, MII, MRI); return new R600InstPrinter(MAI, MII, MCRI);
else else
return new AMDGPUInstPrinter(MAI, MII, MRI); return new AMDGPUInstPrinter(MAI, MII, MCRI);
} }
static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S, static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
bool isVerboseAsm) { bool isVerboseAsm) {
return new AMDGPUTargetAsmStreamer(S, OS); return new AMDGPUTargetAsmStreamer(S, OS);
} }
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.h

Show All 10 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class R600InstPrinter : public MCInstPrinter { class R600InstPrinter : public MCInstPrinter {
public: public:
R600InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, R600InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp

Show All 23 Lines
#include "llvm/MC/SubtargetFeature.h" #include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/EndianStream.h" #include "llvm/Support/EndianStream.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
class R600MCCodeEmitter : public MCCodeEmitter { class R600MCCodeEmitter : public MCCodeEmitter {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const MCInstrInfo &MCII; const MCInstrInfo &MCII;
public: public:
R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
: MRI(mri), MCII(mcii) {} : MCRI(mri), MCII(mcii) {}
R600MCCodeEmitter(const R600MCCodeEmitter &) = delete; R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete; R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;
/// Encode the instruction and write it to the OS. /// Encode the instruction and write it to the OS.
void encodeInstruction(const MCInst &MI, raw_ostream &OS, void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override; const MCSubtargetInfo &STI) const override;
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Linesvoid R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
support::endian::write(OS, Value, support::little); support::endian::write(OS, Value, support::little);
} }
void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const { void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
support::endian::write(OS, Value, support::little); support::endian::write(OS, Value, support::little);
} }
unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
return MRI.getEncodingValue(RegNo) & HW_REG_MASK; return MCRI.getEncodingValue(RegNo) & HW_REG_MASK;
} }
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
if (MO.isReg()) { if (MO.isReg()) {
if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
return MRI.getEncodingValue(MO.getReg()); return MCRI.getEncodingValue(MO.getReg());
return getHWReg(MO.getReg()); return getHWReg(MO.getReg());
} }
if (MO.isExpr()) { if (MO.isExpr()) {
// We put rodata at the end of code section, then map the entire // We put rodata at the end of code section, then map the entire
// code secetion as vtx buf. Thus the section relative address is the // code secetion as vtx buf. Thus the section relative address is the
// correct one. // correct one.
// Each R600 literal instruction has two operands // Each R600 literal instruction has two operands
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llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

Show All 27 Lines
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include <optional> #include <optional>
using namespace llvm; using namespace llvm;
namespace { namespace {
class SIMCCodeEmitter : public AMDGPUMCCodeEmitter { class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
/// Encode an fp or int literal /// Encode an fp or int literal
std::optional<uint32_t> getLitEncoding(const MCOperand &MO, std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
const MCOperandInfo &OpInfo, const MCOperandInfo &OpInfo,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const;
public: public:
SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
: AMDGPUMCCodeEmitter(mcii), MRI(*ctx.getRegisterInfo()) {} : AMDGPUMCCodeEmitter(mcii), MCRI(*ctx.getRegisterInfo()) {}
SIMCCodeEmitter(const SIMCCodeEmitter &) = delete; SIMCCodeEmitter(const SIMCCodeEmitter &) = delete;
SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete; SIMCCodeEmitter &operator=(const SIMCCodeEmitter &) = delete;
/// Encode the instruction and write it to the OS. /// Encode the instruction and write it to the OS.
void encodeInstruction(const MCInst &MI, raw_ostream &OS, void encodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override; const MCSubtargetInfo &STI) const override;
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Linesvoid SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
// GFX10+ v_cmpx opcodes promoted to VOP3 have implied dst=EXEC. // GFX10+ v_cmpx opcodes promoted to VOP3 have implied dst=EXEC.
// Documentation requires dst to be encoded as EXEC (0x7E), // Documentation requires dst to be encoded as EXEC (0x7E),
// but it looks like the actual value encoded for dst operand // but it looks like the actual value encoded for dst operand
// is ignored by HW. It was decided to define dst as "do not care" // is ignored by HW. It was decided to define dst as "do not care"
// in td files to allow disassembler accept any dst value. // in td files to allow disassembler accept any dst value.
// However, dst is encoded as EXEC for compatibility with SP3. // However, dst is encoded as EXEC for compatibility with SP3.
if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) { if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {
assert((Encoding & 0xFF) == 0); assert((Encoding & 0xFF) == 0);
Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO); Encoding |= MCRI.getEncodingValue(AMDGPU::EXEC_LO);
} }
for (unsigned i = 0; i < bytes; i++) { for (unsigned i = 0; i < bytes; i++) {
OS.write((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i)); OS.write((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i));
} }
// NSA encoding. // NSA encoding.
if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Linesvoid SIMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
using namespace AMDGPU::SDWA; using namespace AMDGPU::SDWA;
uint64_t RegEnc = 0; uint64_t RegEnc = 0;
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) { if (MO.isReg()) {
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
RegEnc |= MRI.getEncodingValue(Reg); RegEnc |= MCRI.getEncodingValue(Reg);
RegEnc &= SDWA9EncValues::SRC_VGPR_MASK; RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MCRI)) {
RegEnc |= SDWA9EncValues::SRC_SGPR_MASK; RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
} }
Op = RegEnc; Op = RegEnc;
return; return;
} else { } else {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI); auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI);
if (Enc && *Enc != 255) { if (Enc && *Enc != 255) {
Show All 12 Linesvoid SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
using namespace AMDGPU::SDWA; using namespace AMDGPU::SDWA;
uint64_t RegEnc = 0; uint64_t RegEnc = 0;
const MCOperand &MO = MI.getOperand(OpNo); const MCOperand &MO = MI.getOperand(OpNo);
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) { if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
RegEnc |= MRI.getEncodingValue(Reg); RegEnc |= MCRI.getEncodingValue(Reg);
RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK; RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK; RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
} }
Op = RegEnc; Op = RegEnc;
} }
void SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo, void SIMCCodeEmitter::getAVOperandEncoding(const MCInst &MI, unsigned OpNo,
APInt &Op, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
unsigned Reg = MI.getOperand(OpNo).getReg(); unsigned Reg = MI.getOperand(OpNo).getReg();
uint64_t Enc = MRI.getEncodingValue(Reg); uint64_t Enc = MCRI.getEncodingValue(Reg);
// VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
// instructions use acc[0:1] modifier bits to distinguish. These bits are // instructions use acc[0:1] modifier bits to distinguish. These bits are
// encoded as a virtual 9th bit of the register for these operands. // encoded as a virtual 9th bit of the register for these operands.
if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) || if (MCRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) || MCRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||
MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg)) MCRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
Enc |= 512; Enc |= 512;
Op = Enc; Op = Enc;
} }
static bool needsPCRel(const MCExpr *Expr) { static bool needsPCRel(const MCExpr *Expr) {
switch (Expr->getKind()) { switch (Expr->getKind()) {
case MCExpr::SymbolRef: { case MCExpr::SymbolRef: {
Show All 17 Linesstatic bool needsPCRel(const MCExpr *Expr) {
llvm_unreachable("invalid kind"); llvm_unreachable("invalid kind");
} }
void SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, void SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, APInt &Op, const MCOperand &MO, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
if (MO.isReg()){ if (MO.isReg()){
Op = MRI.getEncodingValue(MO.getReg()); Op = MCRI.getEncodingValue(MO.getReg());
return; return;
} }
unsigned OpNo = &MO - MI.begin(); unsigned OpNo = &MO - MI.begin();
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI); getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
} }
void SIMCCodeEmitter::getMachineOpValueCommon( void SIMCCodeEmitter::getMachineOpValueCommon(
const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op, const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Show First 20 Lines • Show All 1,153 Lines • ▼ Show 20 Lines
/// Get the size in bits of a register from the register class \p RC. /// Get the size in bits of a register from the register class \p RC.
unsigned getRegBitWidth(unsigned RCID); unsigned getRegBitWidth(unsigned RCID);
/// Get the size in bits of a register from the register class \p RC. /// Get the size in bits of a register from the register class \p RC.
unsigned getRegBitWidth(const MCRegisterClass &RC); unsigned getRegBitWidth(const MCRegisterClass &RC);
/// Get size of register operand /// Get size of register operand
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned getRegOperandSize(const MCRegisterInfo *MCRI, const MCInstrDesc &Desc,
unsigned OpNo); unsigned OpNo);
LLVM_READNONE LLVM_READNONE
inline unsigned getOperandSize(const MCOperandInfo &OpInfo) { inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
switch (OpInfo.OperandType) { switch (OpInfo.OperandType) {
case AMDGPU::OPERAND_REG_IMM_INT32: case AMDGPU::OPERAND_REG_IMM_INT32:
case AMDGPU::OPERAND_REG_IMM_FP32: case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 2,322 Lines • ▼ Show 20 Lines default:
llvm_unreachable("Unexpected register class"); llvm_unreachable("Unexpected register class");
} }
} }
unsigned getRegBitWidth(const MCRegisterClass &RC) { unsigned getRegBitWidth(const MCRegisterClass &RC) {
return getRegBitWidth(RC.getID()); return getRegBitWidth(RC.getID());
} }
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned getRegOperandSize(const MCRegisterInfo *MCRI, const MCInstrDesc &Desc,
unsigned OpNo) { unsigned OpNo) {
assert(OpNo < Desc.NumOperands); assert(OpNo < Desc.NumOperands);
unsigned RCID = Desc.operands()[OpNo].RegClass; unsigned RCID = Desc.operands()[OpNo].RegClass;
return getRegBitWidth(MRI->getRegClass(RCID)) / 8; return getRegBitWidth(MCRI->getRegClass(RCID)) / 8;
} }
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) { bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
if (isInlinableIntLiteral(Literal)) if (isInlinableIntLiteral(Literal))
return true; return true;
uint64_t Val = static_cast<uint64_t>(Literal); uint64_t Val = static_cast<uint64_t>(Literal);
return (Val == DoubleToBits(0.0)) || return (Val == DoubleToBits(0.0)) ||
▲ Show 20 Lines • Show All 325 Lines • Show Last 20 Lines

llvm/lib/Target/ARC/ARCFrameLowering.cpp

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
/// For ARC, this inserts a call to a function that puts required callee saved /// For ARC, this inserts a call to a function that puts required callee saved
/// registers onto the stack, when enough callee saved registers are required. /// registers onto the stack, when enough callee saved registers are required.
void ARCFrameLowering::emitPrologue(MachineFunction &MF, void ARCFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
LLVM_DEBUG(dbgs() << "Emit Prologue: " << MF.getName() << "\n"); LLVM_DEBUG(dbgs() << "Emit Prologue: " << MF.getName() << "\n");
auto *AFI = MF.getInfo<ARCFunctionInfo>(); auto *AFI = MF.getInfo<ARCFunctionInfo>();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
MCContext &Context = MMI.getContext(); MCContext &Context = MMI.getContext();
const MCRegisterInfo *MRI = Context.getRegisterInfo(); const MCRegisterInfo *MCRI = Context.getRegisterInfo();
const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo(); const ARCInstrInfo *TII = MF.getSubtarget<ARCSubtarget>().getInstrInfo();
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
// Debug location must be unknown since the first debug location is used // Debug location must be unknown since the first debug location is used
// to determine the end of the prologue. // to determine the end of the prologue.
DebugLoc dl; DebugLoc dl;
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
unsigned Last = determineLastCalleeSave(CSI); unsigned Last = determineLastCalleeSave(CSI);
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize())); MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));
BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
int CurOffset = -4; int CurOffset = -4;
if (hasFP(MF)) { if (hasFP(MF)) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(ARC::FP, true), CurOffset)); nullptr, MCRI->getDwarfRegNum(ARC::FP, true), CurOffset));
BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
CurOffset -= 4; CurOffset -= 4;
} }
if (MFI.hasCalls()) { if (MFI.hasCalls()) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(ARC::BLINK, true), CurOffset)); nullptr, MCRI->getDwarfRegNum(ARC::BLINK, true), CurOffset));
BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
// CFI for the rest of the registers. // CFI for the rest of the registers.
for (const auto &Entry : CSI) { for (const auto &Entry : CSI) {
unsigned Reg = Entry.getReg(); unsigned Reg = Entry.getReg();
int FI = Entry.getFrameIdx(); int FI = Entry.getFrameIdx();
// Skip BLINK and FP. // Skip BLINK and FP.
if ((hasFP(MF) && Reg == ARC::FP) || (MFI.hasCalls() && Reg == ARC::BLINK)) if ((hasFP(MF) && Reg == ARC::FP) || (MFI.hasCalls() && Reg == ARC::BLINK))
continue; continue;
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
} }
/// Insert epilog code into the function. /// Insert epilog code into the function.
/// For ARC, this inserts a call to a function that restores callee saved /// For ARC, this inserts a call to a function that restores callee saved
▲ Show 20 Lines • Show All 261 Lines • Show Last 20 Lines

llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h

Show All 16 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class ARCInstPrinter : public MCInstPrinter { class ARCInstPrinter : public MCInstPrinter {
public: public:
ARCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, ARCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
Show All 20 Lines

llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Linesstatic MCRegisterInfo *createARCMCRegisterInfo(const Triple &TT) {
return X; return X;
} }
static MCSubtargetInfo *createARCMCSubtargetInfo(const Triple &TT, static MCSubtargetInfo *createARCMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) { StringRef CPU, StringRef FS) {
return createARCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS); return createARCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS);
} }
static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createARCMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new ARCMCAsmInfo(TT); MCAsmInfo *MAI = new ARCMCAsmInfo(TT);
// Initial state of the frame pointer is SP. // Initial state of the frame pointer is SP.
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, ARC::SP, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, ARC::SP, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createARCMCInstPrinter(const Triple &T, static MCInstPrinter *createARCMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new ARCInstPrinter(MAI, MII, MRI); return new ARCInstPrinter(MAI, MII, MCRI);
} }
ARCTargetStreamer::ARCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} ARCTargetStreamer::ARCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
ARCTargetStreamer::~ARCTargetStreamer() = default; ARCTargetStreamer::~ARCTargetStreamer() = default;
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrint, MCInstPrinter *InstPrint,
Show All 26 Lines

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 6,491 Lines • ▼ Show 20 Lines int64_t StackPosEntry =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Align)); MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Align));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(StackPosEntry) .addCFIIndex(StackPosEntry)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
// Add a CFI saying that the LR that we want to find is now higher than // Add a CFI saying that the LR that we want to find is now higher than
// before. // before.
int LROffset = Auth ? Align - 4 : Align; int LROffset = Auth ? Align - 4 : Align;
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo();
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true);
int64_t LRPosEntry = MF.addFrameInst( int64_t LRPosEntry = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset)); MCCFIInstruction::createOffset(nullptr, DwarfLR, -LROffset));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(LRPosEntry) .addCFIIndex(LRPosEntry)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
if (Auth) { if (Auth) {
// Add a CFI for the location of the return adddress PAC. // Add a CFI for the location of the return adddress PAC.
unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); unsigned DwarfRAC = MCRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
int64_t RACPosEntry = MF.addFrameInst( int64_t RACPosEntry = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align)); MCCFIInstruction::createOffset(nullptr, DwarfRAC, -Align));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(RACPosEntry) .addCFIIndex(RACPosEntry)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
} }
void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB, void ARMBaseInstrInfo::emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator It, MachineBasicBlock::iterator It,
Register Reg) const { Register Reg) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo();
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true);
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true);
int64_t LRPosEntry = MF.addFrameInst( int64_t LRPosEntry = MF.addFrameInst(
MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(LRPosEntry) .addCFIIndex(LRPosEntry)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
Show All 23 Lines if (Auth) {
MIB.addImm(Subtarget.getStackAlignment().value()) MIB.addImm(Subtarget.getStackAlignment().value())
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.setMIFlags(MachineInstr::FrameDestroy); .setMIFlags(MachineInstr::FrameDestroy);
} }
if (CFI) { if (CFI) {
// Now stack has moved back up... // Now stack has moved back up...
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo();
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true);
int64_t StackPosEntry = int64_t StackPosEntry =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(StackPosEntry) .addCFIIndex(StackPosEntry)
.setMIFlags(MachineInstr::FrameDestroy); .setMIFlags(MachineInstr::FrameDestroy);
// ... and we have restored LR. // ... and we have restored LR.
int64_t LRPosEntry = int64_t LRPosEntry =
MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR)); MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(LRPosEntry) .addCFIIndex(LRPosEntry)
.setMIFlags(MachineInstr::FrameDestroy); .setMIFlags(MachineInstr::FrameDestroy);
if (Auth) { if (Auth) {
unsigned DwarfRAC = MRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true); unsigned DwarfRAC = MCRI->getDwarfRegNum(ARM::RA_AUTH_CODE, true);
int64_t Entry = int64_t Entry =
MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, DwarfRAC)); MF.addFrameInst(MCCFIInstruction::createUndefined(nullptr, DwarfRAC));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(Entry) .addCFIIndex(Entry)
.setMIFlags(MachineInstr::FrameDestroy); .setMIFlags(MachineInstr::FrameDestroy);
} }
} }
if (Auth) if (Auth)
BuildMI(MBB, It, DebugLoc(), get(ARM::t2AUT)); BuildMI(MBB, It, DebugLoc(), get(ARM::t2AUT));
} }
void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg( void ARMBaseInstrInfo::emitCFIForLRRestoreFromReg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const { MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
const MCRegisterInfo *MRI = Subtarget.getRegisterInfo(); const MCRegisterInfo *MCRI = Subtarget.getRegisterInfo();
unsigned DwarfLR = MRI->getDwarfRegNum(ARM::LR, true); unsigned DwarfLR = MCRI->getDwarfRegNum(ARM::LR, true);
int64_t LRPosEntry = int64_t LRPosEntry =
MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR)); MF.addFrameInst(MCCFIInstruction::createRestore(nullptr, DwarfLR));
BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION)) BuildMI(MBB, It, DebugLoc(), get(ARM::CFI_INSTRUCTION))
.addCFIIndex(LRPosEntry) .addCFIIndex(LRPosEntry)
.setMIFlags(MachineInstr::FrameDestroy); .setMIFlags(MachineInstr::FrameDestroy);
} }
▲ Show 20 Lines • Show All 447 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMFrameLowering.cpp

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines
void ARMFrameLowering::emitPrologue(MachineFunction &MF, void ARMFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
MCContext &Context = MMI.getContext(); MCContext &Context = MMI.getContext();
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const MCRegisterInfo *MRI = Context.getRegisterInfo(); const MCRegisterInfo *MCRI = Context.getRegisterInfo();
const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
assert(!AFI->isThumb1OnlyFunction() && assert(!AFI->isThumb1OnlyFunction() &&
"This emitPrologue does not support Thumb1!"); "This emitPrologue does not support Thumb1!");
bool isARM = !AFI->isThumbFunction(); bool isARM = !AFI->isThumbFunction();
Align Alignment = STI.getFrameLowering()->getStackAlign(); Align Alignment = STI.getFrameLowering()->getStackAlign();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
unsigned NumBytes = MFI.getStackSize(); unsigned NumBytes = MFI.getStackSize();
▲ Show 20 Lines • Show All 333 Lines • ▼ Show 20 Lines if (HasFP) {
} else { } else {
emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII, emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII,
FramePtr, ARM::SP, FPOffset, FramePtr, ARM::SP, FPOffset,
MachineInstr::FrameSetup); MachineInstr::FrameSetup);
} }
if (!NeedsWinCFI) { if (!NeedsWinCFI) {
if (FramePtrOffsetInPush + PushSize != 0) { if (FramePtrOffsetInPush + PushSize != 0) {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
nullptr, MRI->getDwarfRegNum(FramePtr, true), nullptr, MCRI->getDwarfRegNum(FramePtr, true),
FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush)); FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush));
BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} else { } else {
unsigned CFIIndex = unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
nullptr, MRI->getDwarfRegNum(FramePtr, true))); nullptr, MCRI->getDwarfRegNum(FramePtr, true)));
BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
} }
} }
// Emit a SEH opcode indicating the prologue end. The rest of the prologue // Emit a SEH opcode indicating the prologue end. The rest of the prologue
Show All 31 Lines for (const auto &Entry : CSI) {
case ARM::R2: case ARM::R2:
case ARM::R3: case ARM::R3:
case ARM::R4: case ARM::R4:
case ARM::R5: case ARM::R5:
case ARM::R6: case ARM::R6:
case ARM::R7: case ARM::R7:
case ARM::LR: case ARM::LR:
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
break; break;
} }
} }
} }
if (GPRCS2Size > 0 && !NeedsWinCFI) { if (GPRCS2Size > 0 && !NeedsWinCFI) {
MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
for (const auto &Entry : CSI) { for (const auto &Entry : CSI) {
Register Reg = Entry.getReg(); Register Reg = Entry.getReg();
int FI = Entry.getFrameIdx(); int FI = Entry.getFrameIdx();
switch (Reg) { switch (Reg) {
case ARM::R8: case ARM::R8:
case ARM::R9: case ARM::R9:
case ARM::R10: case ARM::R10:
case ARM::R11: case ARM::R11:
case ARM::R12: case ARM::R12:
if (STI.splitFramePushPop(MF)) { if (STI.splitFramePushPop(MF)) {
unsigned DwarfReg = MRI->getDwarfRegNum( unsigned DwarfReg = MCRI->getDwarfRegNum(
Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true); Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true);
unsigned Offset = MFI.getObjectOffset(FI); unsigned Offset = MFI.getObjectOffset(FI);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
break; break;
} }
} }
} }
if (DPRCSSize > 0 && !NeedsWinCFI) { if (DPRCSSize > 0 && !NeedsWinCFI) {
// Since vpush register list cannot have gaps, there may be multiple vpush // Since vpush register list cannot have gaps, there may be multiple vpush
// instructions in the prologue. // instructions in the prologue.
MachineBasicBlock::iterator Pos = std::next(LastPush); MachineBasicBlock::iterator Pos = std::next(LastPush);
for (const auto &Entry : CSI) { for (const auto &Entry : CSI) {
Register Reg = Entry.getReg(); Register Reg = Entry.getReg();
int FI = Entry.getFrameIdx(); int FI = Entry.getFrameIdx();
if ((Reg >= ARM::D0 && Reg <= ARM::D31) && if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
(Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) { (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true);
unsigned Offset = MFI.getObjectOffset(FI); unsigned Offset = MFI.getObjectOffset(FI);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
} }
▲ Show 20 Lines • Show All 1,748 Lines • ▼ Show 20 Linesvoid ARMFrameLowering::adjustForSegmentedStacks(
if (MF.getFunction().isVarArg()) if (MF.getFunction().isVarArg())
report_fatal_error("Segmented stacks do not support vararg functions."); report_fatal_error("Segmented stacks do not support vararg functions.");
if (!ST->isTargetAndroid() && !ST->isTargetLinux()) if (!ST->isTargetAndroid() && !ST->isTargetLinux())
report_fatal_error("Segmented stacks not supported on this platform."); report_fatal_error("Segmented stacks not supported on this platform.");
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
MCContext &Context = MMI.getContext(); MCContext &Context = MMI.getContext();
const MCRegisterInfo *MRI = Context.getRegisterInfo(); const MCRegisterInfo *MCRI = Context.getRegisterInfo();
const ARMBaseInstrInfo &TII = const ARMBaseInstrInfo &TII =
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
DebugLoc DL; DebugLoc DL;
if (!MFI.needsSplitStackProlog()) if (!MFI.needsSplitStackProlog())
return; return;
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesvoid ARMFrameLowering::adjustForSegmentedStacks(
// Emit the relevant DWARF information about the change in stack pointer as // Emit the relevant DWARF information about the change in stack pointer as
// well as where to find both r4 and r5 (the callee-save registers) // well as where to find both r4 and r5 (the callee-save registers)
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) { if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8)); CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8));
BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4)); nullptr, MCRI->getDwarfRegNum(ScratchReg1, true), -4));
BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8)); nullptr, MCRI->getDwarfRegNum(ScratchReg0, true), -8));
BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
// mov SR1, sp // mov SR1, sp
if (Thumb) { if (Thumb) {
BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
.addReg(ARM::SP) .addReg(ARM::SP)
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Linesvoid ARMFrameLowering::adjustForSegmentedStacks(
// Emit the DWARF info about the change in stack as well as where to find the // Emit the DWARF info about the change in stack as well as where to find the
// previous link register // previous link register
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) { if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12)); CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12));
BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12)); nullptr, MCRI->getDwarfRegNum(ARM::LR, true), -12));
BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
// Call __morestack(). // Call __morestack().
if (Thumb) { if (Thumb) {
BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesvoid ARMFrameLowering::adjustForSegmentedStacks(
if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) { if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0)); CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
// Tell debuggers that r4 and r5 are now the same as they were in the // Tell debuggers that r4 and r5 are now the same as they were in the
// previous function, that they're the "Same Value". // previous function, that they're the "Same Value".
CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
nullptr, MRI->getDwarfRegNum(ScratchReg0, true))); nullptr, MCRI->getDwarfRegNum(ScratchReg0, true)));
BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue( CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
nullptr, MRI->getDwarfRegNum(ScratchReg1, true))); nullptr, MCRI->getDwarfRegNum(ScratchReg1, true)));
BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
// Organizing MBB lists // Organizing MBB lists
PostStackMBB->addSuccessor(&PrologueMBB); PostStackMBB->addSuccessor(&PrologueMBB);
AllocMBB->addSuccessor(PostStackMBB); AllocMBB->addSuccessor(PostStackMBB);
Show All 12 Lines

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines for (StringRef Mnemonic :
CDE.insert(Mnemonic); CDE.insert(Mnemonic);
CDEWithVPTSuffix.insert(Mnemonic); CDEWithVPTSuffix.insert(Mnemonic);
CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t"); CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t");
CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e"); CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e");
} }
} }
class ARMAsmParser : public MCTargetAsmParser { class ARMAsmParser : public MCTargetAsmParser {
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
UnwindContext UC; UnwindContext UC;
ARMMnemonicSets MS; ARMMnemonicSets MS;
ARMTargetStreamer &getTargetStreamer() { ARMTargetStreamer &getTargetStreamer() {
assert(getParser().getStreamer().getTargetStreamer() && assert(getParser().getStreamer().getTargetStreamer() &&
"do not have a target streamer"); "do not have a target streamer");
MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
return static_cast<ARMTargetStreamer &>(TS); return static_cast<ARMTargetStreamer &>(TS);
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesclass ARMAsmParser : public MCTargetAsmParser {
void discardImplicitITBlock() { void discardImplicitITBlock() {
assert(inImplicitITBlock()); assert(inImplicitITBlock());
assert(ITState.CurPosition == 1); assert(ITState.CurPosition == 1);
ITState.CurPosition = ~0U; ITState.CurPosition = ~0U;
} }
// Return the low-subreg of a given Q register. // Return the low-subreg of a given Q register.
unsigned getDRegFromQReg(unsigned QReg) const { unsigned getDRegFromQReg(unsigned QReg) const {
return MRI->getSubReg(QReg, ARM::dsub_0); return MCRI->getSubReg(QReg, ARM::dsub_0);
} }
// Get the condition code corresponding to the current IT block slot. // Get the condition code corresponding to the current IT block slot.
ARMCC::CondCodes currentITCond() { ARMCC::CondCodes currentITCond() {
unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition); unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond; return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
} }
▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines#include "ARMGenAsmMatcher.inc"
}; };
ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) { : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) {
MCAsmParserExtension::Initialize(Parser); MCAsmParserExtension::Initialize(Parser);
// Cache the MCRegisterInfo. // Cache the MCRegisterInfo.
MRI = getContext().getRegisterInfo(); MCRI = getContext().getRegisterInfo();
// Initialize the set of available features. // Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
// Add build attributes based on the selected target. // Add build attributes based on the selected target.
if (AddBuildAttributes) if (AddBuildAttributes)
getTargetStreamer().emitTargetAttributes(STI); getTargetStreamer().emitTargetAttributes(STI);
▲ Show 20 Lines • Show All 3,797 Lines • ▼ Show 20 Linesbool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
// The reglist instructions have at most 16 registers, so reserve // The reglist instructions have at most 16 registers, so reserve
// space for that many. // space for that many.
int EReg = 0; int EReg = 0;
SmallVector<std::pair<unsigned, unsigned>, 16> Registers; SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
// Allow Q regs and just interpret them as the two D sub-registers. // Allow Q regs and just interpret them as the two D sub-registers.
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg); Reg = getDRegFromQReg(Reg);
EReg = MRI->getEncodingValue(Reg); EReg = MCRI->getEncodingValue(Reg);
Registers.emplace_back(EReg, Reg); Registers.emplace_back(EReg, Reg);
++Reg; ++Reg;
} }
const MCRegisterClass *RC; const MCRegisterClass *RC;
if (Reg == ARM::RA_AUTH_CODE || if (Reg == ARM::RA_AUTH_CODE ||
ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
else else
return Error(RegLoc, "invalid register in register list"); return Error(RegLoc, "invalid register in register list");
// Store the register. // Store the register.
EReg = MRI->getEncodingValue(Reg); EReg = MCRI->getEncodingValue(Reg);
Registers.emplace_back(EReg, Reg); Registers.emplace_back(EReg, Reg);
// This starts immediately after the first register token in the list, // This starts immediately after the first register token in the list,
// so we can see either a comma or a minus (range separator) as a legal // so we can see either a comma or a minus (range separator) as a legal
// next token. // next token.
while (Parser.getTok().is(AsmToken::Comma) || while (Parser.getTok().is(AsmToken::Comma) ||
Parser.getTok().is(AsmToken::Minus)) { Parser.getTok().is(AsmToken::Minus)) {
if (Parser.getTok().is(AsmToken::Minus)) { if (Parser.getTok().is(AsmToken::Minus)) {
Show All 12 Lines if (Parser.getTok().is(AsmToken::Minus)) {
// If the register is the same as the start reg, there's nothing // If the register is the same as the start reg, there's nothing
// more to do. // more to do.
if (Reg == EndReg) if (Reg == EndReg)
continue; continue;
// The register must be in the same register class as the first. // The register must be in the same register class as the first.
if (!RC->contains(Reg)) if (!RC->contains(Reg))
return Error(AfterMinusLoc, "invalid register in register list"); return Error(AfterMinusLoc, "invalid register in register list");
// Ranges must go from low to high. // Ranges must go from low to high.
if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) if (MCRI->getEncodingValue(Reg) > MCRI->getEncodingValue(EndReg))
return Error(AfterMinusLoc, "bad range in register list"); return Error(AfterMinusLoc, "bad range in register list");
// Add all the registers in the range to the register list. // Add all the registers in the range to the register list.
while (Reg != EndReg) { while (Reg != EndReg) {
Reg = getNextRegister(Reg); Reg = getNextRegister(Reg);
EReg = MRI->getEncodingValue(Reg); EReg = MCRI->getEncodingValue(Reg);
if (!insertNoDuplicates(Registers, EReg, Reg)) { if (!insertNoDuplicates(Registers, EReg, Reg)) {
Warning(AfterMinusLoc, StringRef("duplicated register (") + Warning(AfterMinusLoc, StringRef("duplicated register (") +
ARMInstPrinter::getRegisterName(Reg) + ARMInstPrinter::getRegisterName(Reg) +
") in register list"); ") in register list");
} }
} }
continue; continue;
} }
Show All 19 Lines if (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg) &&
// subset of GPRRegClassId except it contains APSR as well. // subset of GPRRegClassId except it contains APSR as well.
RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
} }
if (Reg == ARM::VPR && if (Reg == ARM::VPR &&
(RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] || RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) { RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
EReg = MRI->getEncodingValue(Reg); EReg = MCRI->getEncodingValue(Reg);
if (!insertNoDuplicates(Registers, EReg, Reg)) { if (!insertNoDuplicates(Registers, EReg, Reg)) {
Warning(RegLoc, "duplicated register (" + RegTok.getString() + Warning(RegLoc, "duplicated register (" + RegTok.getString() +
") in register list"); ") in register list");
} }
continue; continue;
} }
// The register must be in the same register class as the first. // The register must be in the same register class as the first.
if ((Reg == ARM::RA_AUTH_CODE && if ((Reg == ARM::RA_AUTH_CODE &&
RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) || RC != &ARMMCRegisterClasses[ARM::GPRRegClassID]) ||
(Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg))) (Reg != ARM::RA_AUTH_CODE && !RC->contains(Reg)))
return Error(RegLoc, "invalid register in register list"); return Error(RegLoc, "invalid register in register list");
// In most cases, the list must be monotonically increasing. An // In most cases, the list must be monotonically increasing. An
// exception is CLRM, which is order-independent anyway, so // exception is CLRM, which is order-independent anyway, so
// there's no potential for confusion if you write clrm {r2,r1} // there's no potential for confusion if you write clrm {r2,r1}
// instead of clrm {r1,r2}. // instead of clrm {r1,r2}.
if (EnforceOrder && if (EnforceOrder &&
MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { MCRI->getEncodingValue(Reg) < MCRI->getEncodingValue(OldReg)) {
if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
Warning(RegLoc, "register list not in ascending order"); Warning(RegLoc, "register list not in ascending order");
else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
return Error(RegLoc, "register list not in ascending order"); return Error(RegLoc, "register list not in ascending order");
} }
// VFP register lists must also be contiguous. // VFP register lists must also be contiguous.
if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
Reg != OldReg + 1) Reg != OldReg + 1)
return Error(RegLoc, "non-contiguous register range"); return Error(RegLoc, "non-contiguous register range");
EReg = MRI->getEncodingValue(Reg); EReg = MCRI->getEncodingValue(Reg);
if (!insertNoDuplicates(Registers, EReg, Reg)) { if (!insertNoDuplicates(Registers, EReg, Reg)) {
Warning(RegLoc, "duplicated register (" + RegTok.getString() + Warning(RegLoc, "duplicated register (" + RegTok.getString() +
") in register list"); ") in register list");
} }
if (isQReg) { if (isQReg) {
EReg = MRI->getEncodingValue(++Reg); EReg = MCRI->getEncodingValue(++Reg);
Registers.emplace_back(EReg, Reg); Registers.emplace_back(EReg, Reg);
} }
} }
if (Parser.getTok().isNot(AsmToken::RCurly)) if (Parser.getTok().isNot(AsmToken::RCurly))
return Error(Parser.getTok().getLoc(), "'}' expected"); return Error(Parser.getTok().getLoc(), "'}' expected");
SMLoc E = Parser.getTok().getEndLoc(); SMLoc E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat '}' token. Parser.Lex(); // Eat '}' token.
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
} }
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg); Reg = getDRegFromQReg(Reg);
OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
if (Res != MatchOperand_Success) if (Res != MatchOperand_Success)
return Res; return Res;
switch (LaneKind) { switch (LaneKind) {
case NoLanes: case NoLanes:
Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, Reg = MCRI->getMatchingSuperReg(
&ARMMCRegisterClasses[ARM::DPairRegClassID]); Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
break; break;
case AllLanes: case AllLanes:
Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, Reg = MCRI->getMatchingSuperReg(
&ARMMCRegisterClasses[ARM::DPairRegClassID]); Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]);
Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
S, E)); S, E));
break; break;
case IndexedLane: case IndexedLane:
Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
LaneIndex, LaneIndex,
false, S, E)); false, S, E));
break; break;
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 LinesARMAsmParser::parseVectorList(OperandVector &Operands) {
case NoLanes: case NoLanes:
case AllLanes: { case AllLanes: {
// Two-register operands have been converted to the // Two-register operands have been converted to the
// composite register classes. // composite register classes.
if (Count == 2 && !hasMVE()) { if (Count == 2 && !hasMVE()) {
const MCRegisterClass *RC = (Spacing == 1) ? const MCRegisterClass *RC = (Spacing == 1) ?
&ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairRegClassID] :
&ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); FirstReg = MCRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
} }
auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
ARMOperand::CreateVectorListAllLanes); ARMOperand::CreateVectorListAllLanes);
Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
break; break;
} }
case IndexedLane: case IndexedLane:
Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
▲ Show 20 Lines • Show All 2,037 Lines • ▼ Show 20 Linesvoid ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
if (!Op2.isReg()) if (!Op2.isReg())
return; return;
if (!Op3.isGPRMem()) if (!Op3.isGPRMem())
return; return;
const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID); const MCRegisterClass &GPR = MCRI->getRegClass(ARM::GPRRegClassID);
if (!GPR.contains(Op2.getReg())) if (!GPR.contains(Op2.getReg()))
return; return;
unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg()); unsigned RtEncoding = MCRI->getEncodingValue(Op2.getReg());
if (!isThumb() && (RtEncoding & 1)) { if (!isThumb() && (RtEncoding & 1)) {
// In ARM mode, the registers must be from an aligned pair, this // In ARM mode, the registers must be from an aligned pair, this
// restriction does not apply in Thumb mode. // restriction does not apply in Thumb mode.
return; return;
} }
if (Op2.getReg() == ARM::PC) if (Op2.getReg() == ARM::PC)
return; return;
unsigned PairedReg = GPR.getRegister(RtEncoding + 1); unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
▲ Show 20 Lines • Show All 435 Lines • ▼ Show 20 Lines if (VPTPredicationCode != ARMVCC::None) {
if (!isThumb() && Operands.size() > 4 && if (!isThumb() && Operands.size() > 4 &&
(Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
Mnemonic == "stlexd")) { Mnemonic == "stlexd")) {
bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
unsigned Idx = isLoad ? 2 : 3; unsigned Idx = isLoad ? 2 : 3;
ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID); const MCRegisterClass &MRC = MCRI->getRegClass(ARM::GPRRegClassID);
// Adjust only if Op1 and Op2 are GPRs. // Adjust only if Op1 and Op2 are GPRs.
if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
MRC.contains(Op2.getReg())) { MRC.contains(Op2.getReg())) {
unsigned Reg1 = Op1.getReg(); unsigned Reg1 = Op1.getReg();
unsigned Reg2 = Op2.getReg(); unsigned Reg2 = Op2.getReg();
unsigned Rt = MRI->getEncodingValue(Reg1); unsigned Rt = MCRI->getEncodingValue(Reg1);
unsigned Rt2 = MRI->getEncodingValue(Reg2); unsigned Rt2 = MCRI->getEncodingValue(Reg2);
// Rt2 must be Rt + 1 and Rt must be even. // Rt2 must be Rt + 1 and Rt must be even.
if (Rt + 1 != Rt2 || (Rt & 1)) { if (Rt + 1 != Rt2 || (Rt & 1)) {
return Error(Op2.getStartLoc(), return Error(Op2.getStartLoc(),
isLoad ? "destination operands must be sequential" isLoad ? "destination operands must be sequential"
: "source operands must be sequential"); : "source operands must be sequential");
} }
unsigned NewReg = MRI->getMatchingSuperReg( unsigned NewReg = MCRI->getMatchingSuperReg(
Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID))); Reg1, ARM::gsub_0, &(MCRI->getRegClass(ARM::GPRPairRegClassID)));
Operands[Idx] = Operands[Idx] =
ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
Operands.erase(Operands.begin() + Idx + 1); Operands.erase(Operands.begin() + Idx + 1);
} }
} }
// GNU Assembler extension (compatibility). // GNU Assembler extension (compatibility).
fixupGNULDRDAlias(Mnemonic, Operands); fixupGNULDRDAlias(Mnemonic, Operands);
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
"PC may not be in the register list"); "PC may not be in the register list");
return false; return false;
} }
bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst, bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
const OperandVector &Operands, const OperandVector &Operands,
bool Load, bool ARMMode, bool Writeback) { bool Load, bool ARMMode, bool Writeback) {
unsigned RtIndex = Load || !Writeback ? 0 : 1; unsigned RtIndex = Load || !Writeback ? 0 : 1;
unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); unsigned Rt2 = MCRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
if (ARMMode) { if (ARMMode) {
// Rt can't be R14. // Rt can't be R14.
if (Rt == 14) if (Rt == 14)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"Rt can't be R14"); "Rt can't be R14");
// Rt must be even-numbered. // Rt must be even-numbered.
Show All 17 Linesbool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
if (!ARMMode && Load) { if (!ARMMode && Load) {
if (Rt2 == Rt) if (Rt2 == Rt)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"destination operands can't be identical"); "destination operands can't be identical");
} }
if (Writeback) { if (Writeback) {
unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(3).getReg());
if (Rn == Rt || Rn == Rt2) { if (Rn == Rt || Rn == Rt2) {
if (Load) if (Load)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"base register needs to be different from destination " "base register needs to be different from destination "
"registers"); "registers");
else else
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Linesbool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::t2STRH_POST: case ARM::t2STRH_POST:
case ARM::STRB_PRE_IMM: case ARM::STRB_PRE_IMM:
case ARM::STRB_PRE_REG: case ARM::STRB_PRE_REG:
case ARM::t2STRB_PRE: case ARM::t2STRB_PRE:
case ARM::STRB_POST_IMM: case ARM::STRB_POST_IMM:
case ARM::STRB_POST_REG: case ARM::STRB_POST_REG:
case ARM::t2STRB_POST: { case ARM::t2STRB_POST: {
// Rt must be different from Rn. // Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(1).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(2).getReg());
if (Rt == Rn) if (Rt == Rn)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"source register and base register can't be identical"); "source register and base register can't be identical");
return false; return false;
} }
case ARM::t2LDR_PRE_imm: case ARM::t2LDR_PRE_imm:
case ARM::t2LDR_POST_imm: case ARM::t2LDR_POST_imm:
case ARM::t2STR_PRE_imm: case ARM::t2STR_PRE_imm:
case ARM::t2STR_POST_imm: { case ARM::t2STR_POST_imm: {
// Rt must be different from Rn. // Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg()); const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(1).getReg());
if (Rt == Rn) if (Rt == Rn)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"destination register and base register can't be identical"); "destination register and base register can't be identical");
if (Inst.getOpcode() == ARM::t2LDR_POST_imm || if (Inst.getOpcode() == ARM::t2LDR_POST_imm ||
Inst.getOpcode() == ARM::t2STR_POST_imm) { Inst.getOpcode() == ARM::t2STR_POST_imm) {
int Imm = Inst.getOperand(2).getImm(); int Imm = Inst.getOperand(2).getImm();
if (Imm > 255 || Imm < -255) if (Imm > 255 || Imm < -255)
Show All 29 Linesbool ARMAsmParser::validateInstruction(MCInst &Inst,
case ARM::LDRB_POST_IMM: case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG: case ARM::LDRB_POST_REG:
case ARM::t2LDRB_POST: case ARM::t2LDRB_POST:
case ARM::LDRSB_PRE: case ARM::LDRSB_PRE:
case ARM::t2LDRSB_PRE: case ARM::t2LDRSB_PRE:
case ARM::LDRSB_POST: case ARM::LDRSB_POST:
case ARM::t2LDRSB_POST: { case ARM::t2LDRSB_POST: {
// Rt must be different from Rn. // Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); const unsigned Rt = MCRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); const unsigned Rn = MCRI->getEncodingValue(Inst.getOperand(2).getReg());
if (Rt == Rn) if (Rt == Rn)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"destination register and base register can't be identical"); "destination register and base register can't be identical");
return false; return false;
} }
case ARM::MVE_VLDRBU8_rq: case ARM::MVE_VLDRBU8_rq:
Show All 26 Lines case ARM::MVE_VLDRDU64_qi:
break; break;
case ARM::MVE_VLDRWU32_qi_pre: case ARM::MVE_VLDRWU32_qi_pre:
case ARM::MVE_VLDRDU64_qi_pre: case ARM::MVE_VLDRDU64_qi_pre:
QdIdx = 1; QdIdx = 1;
QmIsPointer = true; QmIsPointer = true;
break; break;
} }
const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); const unsigned Qd = MCRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg()); const unsigned Qm = MCRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
if (Qd == Qm) { if (Qd == Qm) {
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
Twine("destination vector register and vector ") + Twine("destination vector register and vector ") +
(QmIsPointer ? "pointer" : "offset") + (QmIsPointer ? "pointer" : "offset") +
" register can't be identical"); " register can't be identical");
} }
return false; return false;
▲ Show 20 Lines • Show All 320 Lines • ▼ Show 20 Lines case ARM::t2DSB: {
if (Option == 4 && Pred != ARMCC::AL) if (Option == 4 && Pred != ARMCC::AL)
return Error(Operands[1]->getStartLoc(), return Error(Operands[1]->getStartLoc(),
"instruction 'pssbb' is not predicable, but condition code " "instruction 'pssbb' is not predicable, but condition code "
"specified"); "specified");
break; break;
} }
case ARM::VMOVRRS: { case ARM::VMOVRRS: {
// Source registers must be sequential. // Source registers must be sequential.
const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg()); const unsigned Sm = MCRI->getEncodingValue(Inst.getOperand(2).getReg());
const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg()); const unsigned Sm1 = MCRI->getEncodingValue(Inst.getOperand(3).getReg());
if (Sm1 != Sm + 1) if (Sm1 != Sm + 1)
return Error(Operands[5]->getStartLoc(), return Error(Operands[5]->getStartLoc(),
"source operands must be sequential"); "source operands must be sequential");
break; break;
} }
case ARM::VMOVSRR: { case ARM::VMOVSRR: {
// Destination registers must be sequential. // Destination registers must be sequential.
const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg()); const unsigned Sm = MCRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); const unsigned Sm1 = MCRI->getEncodingValue(Inst.getOperand(1).getReg());
if (Sm1 != Sm + 1) if (Sm1 != Sm + 1)
return Error(Operands[3]->getStartLoc(), return Error(Operands[3]->getStartLoc(),
"destination operands must be sequential"); "destination operands must be sequential");
break; break;
} }
case ARM::VLDMDIA: case ARM::VLDMDIA:
case ARM::VSTMDIA: { case ARM::VSTMDIA: {
ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
▲ Show 20 Lines • Show All 2,615 Lines • ▼ Show 20 Linesbool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
// All branch & call instructions terminate IT blocks with the exception of // All branch & call instructions terminate IT blocks with the exception of
// SVC. // SVC.
if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) || if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch()) MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
return true; return true;
// Any arithmetic instruction which writes to the PC also terminates the IT // Any arithmetic instruction which writes to the PC also terminates the IT
// block. // block.
if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI)) if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MCRI))
return true; return true;
return false; return false;
} }
unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
SmallVectorImpl<NearMissInfo> &NearMisses, SmallVectorImpl<NearMissInfo> &NearMisses,
bool MatchingInlineAsm, bool MatchingInlineAsm,
▲ Show 20 Lines • Show All 1,212 Lines • ▼ Show 20 Linesbool ARMAsmParser::parseDirectiveSEHSaveRegs(SMLoc L, bool Wide) {
if (parseRegisterList(Operands) || parseEOL()) if (parseRegisterList(Operands) || parseEOL())
return true; return true;
ARMOperand &Op = (ARMOperand &)*Operands[0]; ARMOperand &Op = (ARMOperand &)*Operands[0];
if (!Op.isRegList()) if (!Op.isRegList())
return Error(L, ".seh_save_regs{_w} expects GPR registers"); return Error(L, ".seh_save_regs{_w} expects GPR registers");
const SmallVectorImpl<unsigned> &RegList = Op.getRegList(); const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
uint32_t Mask = 0; uint32_t Mask = 0;
for (size_t i = 0; i < RegList.size(); ++i) { for (size_t i = 0; i < RegList.size(); ++i) {
unsigned Reg = MRI->getEncodingValue(RegList[i]); unsigned Reg = MCRI->getEncodingValue(RegList[i]);
if (Reg == 15) // pc -> lr if (Reg == 15) // pc -> lr
Reg = 14; Reg = 14;
if (Reg == 13) if (Reg == 13)
return Error(L, ".seh_save_regs{_w} can't include SP"); return Error(L, ".seh_save_regs{_w} can't include SP");
assert(Reg < 16U && "Register out of range"); assert(Reg < 16U && "Register out of range");
unsigned Bit = (1u << Reg); unsigned Bit = (1u << Reg);
Mask |= Bit; Mask |= Bit;
} }
if (!Wide && (Mask & 0x1f00) != 0) if (!Wide && (Mask & 0x1f00) != 0)
return Error(L, return Error(L,
".seh_save_regs cannot save R8-R12, needs .seh_save_regs_w"); ".seh_save_regs cannot save R8-R12, needs .seh_save_regs_w");
getTargetStreamer().emitARMWinCFISaveRegMask(Mask, Wide); getTargetStreamer().emitARMWinCFISaveRegMask(Mask, Wide);
return false; return false;
} }
/// parseDirectiveSEHSaveSP /// parseDirectiveSEHSaveSP
/// ::= .seh_save_sp /// ::= .seh_save_sp
bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) { bool ARMAsmParser::parseDirectiveSEHSaveSP(SMLoc L) {
int Reg = tryParseRegister(); int Reg = tryParseRegister();
if (Reg == -1 || !MRI->getRegClass(ARM::GPRRegClassID).contains(Reg)) if (Reg == -1 || !MCRI->getRegClass(ARM::GPRRegClassID).contains(Reg))
return Error(L, "expected GPR"); return Error(L, "expected GPR");
unsigned Index = MRI->getEncodingValue(Reg); unsigned Index = MCRI->getEncodingValue(Reg);
if (Index > 14 || Index == 13) if (Index > 14 || Index == 13)
return Error(L, "invalid register for .seh_save_sp"); return Error(L, "invalid register for .seh_save_sp");
getTargetStreamer().emitARMWinCFISaveSP(Index); getTargetStreamer().emitARMWinCFISaveSP(Index);
return false; return false;
} }
/// parseDirectiveSEHSaveFRegs /// parseDirectiveSEHSaveFRegs
/// ::= .seh_save_fregs /// ::= .seh_save_fregs
bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) { bool ARMAsmParser::parseDirectiveSEHSaveFRegs(SMLoc L) {
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
if (parseRegisterList(Operands) || parseEOL()) if (parseRegisterList(Operands) || parseEOL())
return true; return true;
ARMOperand &Op = (ARMOperand &)*Operands[0]; ARMOperand &Op = (ARMOperand &)*Operands[0];
if (!Op.isDPRRegList()) if (!Op.isDPRRegList())
return Error(L, ".seh_save_fregs expects DPR registers"); return Error(L, ".seh_save_fregs expects DPR registers");
const SmallVectorImpl<unsigned> &RegList = Op.getRegList(); const SmallVectorImpl<unsigned> &RegList = Op.getRegList();
uint32_t Mask = 0; uint32_t Mask = 0;
for (size_t i = 0; i < RegList.size(); ++i) { for (size_t i = 0; i < RegList.size(); ++i) {
unsigned Reg = MRI->getEncodingValue(RegList[i]); unsigned Reg = MCRI->getEncodingValue(RegList[i]);
assert(Reg < 32U && "Register out of range"); assert(Reg < 32U && "Register out of range");
unsigned Bit = (1u << Reg); unsigned Bit = (1u << Reg);
Mask |= Bit; Mask |= Bit;
} }
if (Mask == 0) if (Mask == 0)
return Error(L, ".seh_save_fregs missing registers"); return Error(L, ".seh_save_fregs missing registers");
▲ Show 20 Lines • Show All 456 Lines • ▼ Show 20 Lines case MCK_ModImm:
} }
break; break;
case MCK_rGPR: case MCK_rGPR:
if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP) if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
return Match_Success; return Match_Success;
return Match_rGPR; return Match_rGPR;
case MCK_GPRPair: case MCK_GPRPair:
if (Op.isReg() && if (Op.isReg() &&
MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) MCRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
return Match_Success; return Match_Success;
break; break;
} }
return Match_InvalidOperand; return Match_InvalidOperand;
} }
bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic, bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
StringRef ExtraToken) { StringRef ExtraToken) {
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Show First 20 Lines • Show All 1,123 Lines • ▼ Show 20 Linesuint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
DenseMap<unsigned, int> RegOffsets; DenseMap<unsigned, int> RegOffsets;
int FloatRegCount = 0; int FloatRegCount = 0;
// Process each .cfi directive and build up compact unwind info. // Process each .cfi directive and build up compact unwind info.
for (const MCCFIInstruction &Inst : Instrs) { for (const MCCFIInstruction &Inst : Instrs) {
unsigned Reg; unsigned Reg;
switch (Inst.getOperation()) { switch (Inst.getOperation()) {
case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
CFARegisterOffset = Inst.getOffset(); CFARegisterOffset = Inst.getOffset();
CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); CFARegister = *MCRI.getLLVMRegNum(Inst.getRegister(), true);
break; break;
case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
CFARegisterOffset = Inst.getOffset(); CFARegisterOffset = Inst.getOffset();
break; break;
case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); CFARegister = *MCRI.getLLVMRegNum(Inst.getRegister(), true);
break; break;
case MCCFIInstruction::OpOffset: // DW_CFA_offset case MCCFIInstruction::OpOffset: // DW_CFA_offset
Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); Reg = *MCRI.getLLVMRegNum(Inst.getRegister(), true);
if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
RegOffsets[Reg] = Inst.getOffset(); RegOffsets[Reg] = Inst.getOffset();
else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
RegOffsets[Reg] = Inst.getOffset(); RegOffsets[Reg] = Inst.getOffset();
++FloatRegCount; ++FloatRegCount;
} else { } else {
DEBUG_WITH_TYPE("compact-unwind", DEBUG_WITH_TYPE("compact-unwind",
llvm::dbgs() << ".cfi_offset on unknown register=" llvm::dbgs() << ".cfi_offset on unknown register="
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Linesuint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
for (auto CSReg : GPRCSRegs) { for (auto CSReg : GPRCSRegs) {
auto Offset = RegOffsets.find(CSReg.Reg); auto Offset = RegOffsets.find(CSReg.Reg);
if (Offset == RegOffsets.end()) if (Offset == RegOffsets.end())
continue; continue;
int RegOffset = Offset->second; int RegOffset = Offset->second;
if (RegOffset != CurOffset - 4) { if (RegOffset != CurOffset - 4) {
DEBUG_WITH_TYPE("compact-unwind", DEBUG_WITH_TYPE("compact-unwind",
llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " llvm::dbgs() << MCRI.getName(CSReg.Reg) << " saved at "
<< RegOffset << " but only supported at " << RegOffset << " but only supported at "
<< CurOffset << "\n"); << CurOffset << "\n");
return CU::UNWIND_ARM_MODE_DWARF; return CU::UNWIND_ARM_MODE_DWARF;
} }
CompactUnwindEncoding |= CSReg.Encoding; CompactUnwindEncoding |= CSReg.Encoding;
CurOffset -= 4; CurOffset -= 4;
} }
Show All 17 Linesuint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
// Floating point registers must either be saved sequentially, or we defer to // Floating point registers must either be saved sequentially, or we defer to
// DWARF. No gaps allowed here so check that each saved d-register is // DWARF. No gaps allowed here so check that each saved d-register is
// precisely where it should be. // precisely where it should be.
static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
auto Offset = RegOffsets.find(FPRCSRegs[Idx]); auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
if (Offset == RegOffsets.end()) { if (Offset == RegOffsets.end()) {
DEBUG_WITH_TYPE("compact-unwind", DEBUG_WITH_TYPE("compact-unwind",
llvm::dbgs() << FloatRegCount << " D-regs saved, but " llvm::dbgs()
<< MRI.getName(FPRCSRegs[Idx]) << FloatRegCount << " D-regs saved, but "
<< " not saved\n"); << MCRI.getName(FPRCSRegs[Idx]) << " not saved\n");
return CU::UNWIND_ARM_MODE_DWARF; return CU::UNWIND_ARM_MODE_DWARF;
} else if (Offset->second != CurOffset - 8) { } else if (Offset->second != CurOffset - 8) {
DEBUG_WITH_TYPE("compact-unwind", DEBUG_WITH_TYPE("compact-unwind",
llvm::dbgs() << FloatRegCount << " D-regs saved, but " llvm::dbgs()
<< MRI.getName(FPRCSRegs[Idx]) << FloatRegCount << " D-regs saved, but "
<< " saved at " << Offset->second << MCRI.getName(FPRCSRegs[Idx]) << " saved at "
<< ", expected at " << CurOffset - 8 << Offset->second << ", expected at " << CurOffset - 8
<< "\n"); << "\n");
return CU::UNWIND_ARM_MODE_DWARF; return CU::UNWIND_ARM_MODE_DWARF;
} }
CurOffset -= 8; CurOffset -= 8;
} }
return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
} }
static MCAsmBackend *createARMAsmBackend(const Target &T, static MCAsmBackend *createARMAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options, const MCTargetOptions &Options,
support::endianness Endian) { support::endianness Endian) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
switch (TheTriple.getObjectFormat()) { switch (TheTriple.getObjectFormat()) {
default: default:
llvm_unreachable("unsupported object format"); llvm_unreachable("unsupported object format");
case Triple::MachO: case Triple::MachO:
return new ARMAsmBackendDarwin(T, STI, MRI); return new ARMAsmBackendDarwin(T, STI, MCRI);
case Triple::COFF: case Triple::COFF:
assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb()); return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
case Triple::ELF: case Triple::ELF:
assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI, return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
Endian); Endian);
} }
} }
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, STI, MRI, Options, support::little); return createARMAsmBackend(T, STI, MCRI, Options, support::little);
} }
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, STI, MRI, Options, support::big); return createARMAsmBackend(T, STI, MCRI, Options, support::big);
} }

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h

Show All 9 Lines
#define LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H
#include "ARMAsmBackend.h" #include "ARMAsmBackend.h"
#include "llvm/BinaryFormat/MachO.h" #include "llvm/BinaryFormat/MachO.h"
#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCObjectWriter.h"
namespace llvm { namespace llvm {
class ARMAsmBackendDarwin : public ARMAsmBackend { class ARMAsmBackendDarwin : public ARMAsmBackend {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
Triple TT; Triple TT;
public: public:
const MachO::CPUSubTypeARM Subtype; const MachO::CPUSubTypeARM Subtype;
ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: ARMAsmBackend(T, STI.getTargetTriple().isThumb(), support::little), : ARMAsmBackend(T, STI.getTargetTriple().isThumb(), support::little),
MRI(MRI), TT(STI.getTargetTriple()), MCRI(MCRI), TT(STI.getTargetTriple()),
Subtype((MachO::CPUSubTypeARM)cantFail( Subtype((MachO::CPUSubTypeARM)cantFail(
MachO::getCPUSubType(STI.getTargetTriple()))) {} MachO::getCPUSubType(STI.getTargetTriple()))) {}
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override { createObjectTargetWriter() const override {
return createARMMachObjectWriter( return createARMMachObjectWriter(
/*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype); /*Is64Bit=*/false, cantFail(MachO::getCPUType(TT)), Subtype);
} }
uint32_t generateCompactUnwindEncoding( uint32_t generateCompactUnwindEncoding(
ArrayRef<MCCFIInstruction> Instrs) const override; ArrayRef<MCCFIInstruction> Instrs) const override;
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif

llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

Show First 20 Lines • Show All 1,287 Lines • ▼ Show 20 Lines if (PendingOffset != 0) {
UnwindOpAsm.EmitSPOffset(-PendingOffset); UnwindOpAsm.EmitSPOffset(-PendingOffset);
PendingOffset = 0; PendingOffset = 0;
} }
} }
void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) { void ARMELFStreamer::FlushUnwindOpcodes(bool NoHandlerData) {
// Emit the unwind opcode to restore $sp. // Emit the unwind opcode to restore $sp.
if (UsedFP) { if (UsedFP) {
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
int64_t LastRegSaveSPOffset = SPOffset - PendingOffset; int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset); UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); UnwindOpAsm.EmitSetSP(MCRI->getEncodingValue(FPReg));
} else { } else {
FlushPendingOffset(); FlushPendingOffset();
} }
// Finalize the unwind opcode sequence // Finalize the unwind opcode sequence
UnwindOpAsm.Finalize(PersonalityIndex, Opcodes); UnwindOpAsm.Finalize(PersonalityIndex, Opcodes);
// For compact model 0, we have to emit the unwind opcodes in the .ARM.exidx // For compact model 0, we have to emit the unwind opcodes in the .ARM.exidx
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines assert((Reg != ARM::SP && Reg != ARM::PC) &&
"the operand of .movsp cannot be either sp or pc"); "the operand of .movsp cannot be either sp or pc");
assert(FPReg == ARM::SP && "current FP must be SP"); assert(FPReg == ARM::SP && "current FP must be SP");
FlushPendingOffset(); FlushPendingOffset();
FPReg = Reg; FPReg = Reg;
FPOffset = SPOffset + Offset; FPOffset = SPOffset + Offset;
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg)); UnwindOpAsm.EmitSetSP(MCRI->getEncodingValue(FPReg));
} }
void ARMELFStreamer::emitPad(int64_t Offset) { void ARMELFStreamer::emitPad(int64_t Offset) {
// Track the change of the $sp offset // Track the change of the $sp offset
SPOffset -= Offset; SPOffset -= Offset;
// To squash multiple .pad directives, we should delay the unwind opcode // To squash multiple .pad directives, we should delay the unwind opcode
// until the .save, .vsave, .handlerdata, or .fnend directives. // until the .save, .vsave, .handlerdata, or .fnend directives.
PendingOffset -= Offset; PendingOffset -= Offset;
} }
static std::pair<unsigned, unsigned> static std::pair<unsigned, unsigned>
collectHWRegs(const MCRegisterInfo &MRI, unsigned Idx, collectHWRegs(const MCRegisterInfo &MCRI, unsigned Idx,
const SmallVectorImpl<unsigned> &RegList, bool IsVector, const SmallVectorImpl<unsigned> &RegList, bool IsVector,
uint32_t &Mask_) { uint32_t &Mask_) {
uint32_t Mask = 0; uint32_t Mask = 0;
unsigned Count = 0; unsigned Count = 0;
while (Idx > 0) { while (Idx > 0) {
unsigned Reg = RegList[Idx - 1]; unsigned Reg = RegList[Idx - 1];
if (Reg == ARM::RA_AUTH_CODE) if (Reg == ARM::RA_AUTH_CODE)
break; break;
Reg = MRI.getEncodingValue(Reg); Reg = MCRI.getEncodingValue(Reg);
assert(Reg < (IsVector ? 32U : 16U) && "Register out of range"); assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
unsigned Bit = (1u << Reg); unsigned Bit = (1u << Reg);
if ((Mask & Bit) == 0) { if ((Mask & Bit) == 0) {
Mask |= Bit; Mask |= Bit;
++Count; ++Count;
} }
--Idx; --Idx;
} }
Mask_ = Mask; Mask_ = Mask;
return {Idx, Count}; return {Idx, Count};
} }
void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
bool IsVector) { bool IsVector) {
uint32_t Mask; uint32_t Mask;
unsigned Idx, Count; unsigned Idx, Count;
const MCRegisterInfo &MRI = *getContext().getRegisterInfo(); const MCRegisterInfo &MCRI = *getContext().getRegisterInfo();
// Collect the registers in the register list. Issue unwinding instructions in // Collect the registers in the register list. Issue unwinding instructions in
// three parts: ordinary hardware registers, return address authentication // three parts: ordinary hardware registers, return address authentication
// code pseudo register, the rest of the registers. The RA PAC is kept in an // code pseudo register, the rest of the registers. The RA PAC is kept in an
// architectural register (usually r12), but we treat it as a special case in // architectural register (usually r12), but we treat it as a special case in
// order to distinguish between that register containing RA PAC or a general // order to distinguish between that register containing RA PAC or a general
// value. // value.
Idx = RegList.size(); Idx = RegList.size();
while (Idx > 0) { while (Idx > 0) {
std::tie(Idx, Count) = collectHWRegs(MRI, Idx, RegList, IsVector, Mask); std::tie(Idx, Count) = collectHWRegs(MCRI, Idx, RegList, IsVector, Mask);
if (Count) { if (Count) {
// Track the change the $sp offset: For the .save directive, the // Track the change the $sp offset: For the .save directive, the
// corresponding push instruction will decrease the $sp by (4 * Count). // corresponding push instruction will decrease the $sp by (4 * Count).
// For the .vsave directive, the corresponding vpush instruction will // For the .vsave directive, the corresponding vpush instruction will
// decrease $sp by (8 * Count). // decrease $sp by (8 * Count).
SPOffset -= Count * (IsVector ? 8 : 4); SPOffset -= Count * (IsVector ? 8 : 4);
// Emit the opcode // Emit the opcode
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h

Show All 15 Lines
#include "MCTargetDesc/ARMMCTargetDesc.h" #include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class ARMInstPrinter : public MCInstPrinter { class ARMInstPrinter : public MCInstPrinter {
public: public:
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
bool applyTargetSpecificCLOption(StringRef Opt) override; bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
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llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines if (UseMarkup)
O << "<imm:"; O << "<imm:";
O << "#" << translateShiftImm(ShImm); O << "#" << translateShiftImm(ShImm);
if (UseMarkup) if (UseMarkup)
O << ">"; O << ">";
} }
} }
ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
if (Opt == "reg-names-std") { if (Opt == "reg-names-std") {
DefaultAltIdx = ARM::NoRegAltName; DefaultAltIdx = ARM::NoRegAltName;
return true; return true;
} }
if (Opt == "reg-names-raw") { if (Opt == "reg-names-raw") {
DefaultAltIdx = ARM::RegNamesRaw; DefaultAltIdx = ARM::RegNamesRaw;
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Linesvoid ARMInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// a single GPRPair reg operand is used in the .td file to replace the two // a single GPRPair reg operand is used in the .td file to replace the two
// GPRs. However, when decoding them, the two GRPs cannot be automatically // GPRs. However, when decoding them, the two GRPs cannot be automatically
// expressed as a GPRPair, so we have to manually merge them. // expressed as a GPRPair, so we have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this. // FIXME: We would really like to be able to tablegen'erate this.
case ARM::LDREXD: case ARM::LDREXD:
case ARM::STREXD: case ARM::STREXD:
case ARM::LDAEXD: case ARM::LDAEXD:
case ARM::STLEXD: { case ARM::STLEXD: {
const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); const MCRegisterClass &MRC = MCRI.getRegClass(ARM::GPRRegClassID);
bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
if (MRC.contains(Reg)) { if (MRC.contains(Reg)) {
MCInst NewMI; MCInst NewMI;
MCOperand NewReg; MCOperand NewReg;
NewMI.setOpcode(Opcode); NewMI.setOpcode(Opcode);
if (isStore) if (isStore)
NewMI.addOperand(MI->getOperand(0)); NewMI.addOperand(MI->getOperand(0));
NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( NewReg = MCOperand::createReg(MCRI.getMatchingSuperReg(
Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID))); Reg, ARM::gsub_0, &MCRI.getRegClass(ARM::GPRPairRegClassID)));
NewMI.addOperand(NewReg); NewMI.addOperand(NewReg);
// Copy the rest operands into NewMI. // Copy the rest operands into NewMI.
for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i) for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
NewMI.addOperand(MI->getOperand(i)); NewMI.addOperand(MI->getOperand(i));
printInstruction(&NewMI, Address, STI, O); printInstruction(&NewMI, Address, STI, O);
return; return;
} }
▲ Show 20 Lines • Show All 520 Lines • ▼ Show 20 Lines
} }
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
if (MI->getOpcode() != ARM::t2CLRM) { if (MI->getOpcode() != ARM::t2CLRM) {
assert(is_sorted(drop_begin(*MI, OpNum), assert(is_sorted(drop_begin(*MI, OpNum),
[&](const MCOperand &LHS, const MCOperand &RHS) { [&](const MCOperand &LHS, const MCOperand &RHS) {
return MRI.getEncodingValue(LHS.getReg()) < return MCRI.getEncodingValue(LHS.getReg()) <
MRI.getEncodingValue(RHS.getReg()); MCRI.getEncodingValue(RHS.getReg());
})); }));
} }
O << "{"; O << "{";
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
if (i != OpNum) if (i != OpNum)
O << ", "; O << ", ";
printRegName(O, MI->getOperand(i).getReg()); printRegName(O, MI->getOperand(i).getReg());
} }
O << "}"; O << "}";
} }
void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0)); printRegName(O, MCRI.getSubReg(Reg, ARM::gsub_0));
O << ", "; O << ", ";
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); printRegName(O, MCRI.getSubReg(Reg, ARM::gsub_1));
} }
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum); const MCOperand &Op = MI->getOperand(OpNum);
if (Op.getImm()) if (Op.getImm())
O << "be"; O << "be";
▲ Show 20 Lines • Show All 588 Lines • ▼ Show 20 Linesvoid ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
printRegName(O, MI->getOperand(OpNum).getReg()); printRegName(O, MI->getOperand(OpNum).getReg());
O << "}"; O << "}";
} }
void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0);
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_1);
O << "{"; O << "{";
printRegName(O, Reg0); printRegName(O, Reg0);
O << ", "; O << ", ";
printRegName(O, Reg1); printRegName(O, Reg1);
O << "}"; O << "}";
} }
void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0);
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_2);
O << "{"; O << "{";
printRegName(O, Reg0); printRegName(O, Reg0);
O << ", "; O << ", ";
printRegName(O, Reg1); printRegName(O, Reg1);
O << "}"; O << "}";
} }
void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
Show All 37 Linesvoid ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
O << "[]}"; O << "[]}";
} }
void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
unsigned OpNum, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0);
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_1);
O << "{"; O << "{";
printRegName(O, Reg0); printRegName(O, Reg0);
O << "[], "; O << "[], ";
printRegName(O, Reg1); printRegName(O, Reg1);
O << "[]}"; O << "[]}";
} }
void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
Show All 29 Linesvoid ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
printRegName(O, MI->getOperand(OpNum).getReg() + 3); printRegName(O, MI->getOperand(OpNum).getReg() + 3);
O << "[]}"; O << "[]}";
} }
void ARMInstPrinter::printVectorListTwoSpacedAllLanes( void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg0 = MCRI.getSubReg(Reg, ARM::dsub_0);
unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); unsigned Reg1 = MCRI.getSubReg(Reg, ARM::dsub_2);
O << "{"; O << "{";
printRegName(O, Reg0); printRegName(O, Reg0);
O << "[], "; O << "[], ";
printRegName(O, Reg1); printRegName(O, Reg1);
O << "[]}"; O << "[]}";
} }
void ARMInstPrinter::printVectorListThreeSpacedAllLanes( void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
template<unsigned NumRegs> template<unsigned NumRegs>
void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printMVEVectorList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
const char *Prefix = "{"; const char *Prefix = "{";
for (unsigned i = 0; i < NumRegs; i++) { for (unsigned i = 0; i < NumRegs; i++) {
O << Prefix; O << Prefix;
printRegName(O, MRI.getSubReg(Reg, ARM::qsub_0 + i)); printRegName(O, MCRI.getSubReg(Reg, ARM::qsub_0 + i));
Prefix = ", "; Prefix = ", ";
} }
O << "}"; O << "}";
} }
template<int64_t Angle, int64_t Remainder> template<int64_t Angle, int64_t Remainder>
void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo, void ARMInstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
Show All 36 Lines

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Show First 20 Lines • Show All 1,730 Lines • ▼ Show 20 Lines if (SPRRegs || DPRRegs) {
// Ignore VPR // Ignore VPR
if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS) if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
--NumRegs; --NumRegs;
if (SPRRegs) if (SPRRegs)
Binary |= NumRegs; Binary |= NumRegs;
else else
Binary |= NumRegs * 2; Binary |= NumRegs * 2;
} else { } else {
const MCRegisterInfo &MRI = *CTX.getRegisterInfo(); const MCRegisterInfo &MCRI = *CTX.getRegisterInfo();
assert(is_sorted(drop_begin(MI, Op), assert(is_sorted(drop_begin(MI, Op),
[&](const MCOperand &LHS, const MCOperand &RHS) { [&](const MCOperand &LHS, const MCOperand &RHS) {
return MRI.getEncodingValue(LHS.getReg()) < return MCRI.getEncodingValue(LHS.getReg()) <
MRI.getEncodingValue(RHS.getReg()); MCRI.getEncodingValue(RHS.getReg());
})); }));
for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) { for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg()); unsigned RegNo = MCRI.getEncodingValue(MI.getOperand(I).getReg());
Binary |= 1 << RegNo; Binary |= 1 << RegNo;
} }
} }
return Binary; return Binary;
} }
/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

Show All 33 Lines
class MCRelocationInfo; class MCRelocationInfo;
class MCTargetStreamer; class MCTargetStreamer;
class StringRef; class StringRef;
class Target; class Target;
class Triple; class Triple;
namespace ARM_MC { namespace ARM_MC {
std::string ParseARMTriple(const Triple &TT, StringRef CPU); std::string ParseARMTriple(const Triple &TT, StringRef CPU);
void initLLVMToCVRegMapping(MCRegisterInfo *MRI); void initLLVMToCVRegMapping(MCRegisterInfo *MCRI);
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII); bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII); bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
template<class Inst> template<class Inst>
bool isLDMBaseRegInList(const Inst &MI) { bool isLDMBaseRegInList(const Inst &MI) {
auto BaseReg = MI.getOperand(0).getReg(); auto BaseReg = MI.getOperand(0).getReg();
for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) { for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
Show All 25 Lines
MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
// Construct a PE/COFF machine code streamer which will generate a PE/COFF // Construct a PE/COFF machine code streamer which will generate a PE/COFF
// object file. // object file.
MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB, std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter, std::unique_ptr<MCCodeEmitter> &&Emitter,
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Lines
} }
static MCInstrInfo *createARMMCInstrInfo() { static MCInstrInfo *createARMMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitARMMCInstrInfo(X); InitARMMCInstrInfo(X);
return X; return X;
} }
void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MCRI) {
// Mapping from CodeView to MC register id. // Mapping from CodeView to MC register id.
static const struct { static const struct {
codeview::RegisterId CVReg; codeview::RegisterId CVReg;
MCPhysReg Reg; MCPhysReg Reg;
} RegMap[] = { } RegMap[] = {
{codeview::RegisterId::ARM_R0, ARM::R0}, {codeview::RegisterId::ARM_R0, ARM::R0},
{codeview::RegisterId::ARM_R1, ARM::R1}, {codeview::RegisterId::ARM_R1, ARM::R1},
{codeview::RegisterId::ARM_R2, ARM::R2}, {codeview::RegisterId::ARM_R2, ARM::R2},
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines MCPhysReg Reg;
{codeview::RegisterId::ARM_NQ10, ARM::Q10}, {codeview::RegisterId::ARM_NQ10, ARM::Q10},
{codeview::RegisterId::ARM_NQ11, ARM::Q11}, {codeview::RegisterId::ARM_NQ11, ARM::Q11},
{codeview::RegisterId::ARM_NQ12, ARM::Q12}, {codeview::RegisterId::ARM_NQ12, ARM::Q12},
{codeview::RegisterId::ARM_NQ13, ARM::Q13}, {codeview::RegisterId::ARM_NQ13, ARM::Q13},
{codeview::RegisterId::ARM_NQ14, ARM::Q14}, {codeview::RegisterId::ARM_NQ14, ARM::Q14},
{codeview::RegisterId::ARM_NQ15, ARM::Q15}, {codeview::RegisterId::ARM_NQ15, ARM::Q15},
}; };
for (const auto &I : RegMap) for (const auto &I : RegMap)
MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); MCRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
} }
static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
ARM_MC::initLLVMToCVRegMapping(X); ARM_MC::initLLVMToCVRegMapping(X);
return X; return X;
} }
static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TheTriple, const Triple &TheTriple,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI; MCAsmInfo *MAI;
if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
MAI = new ARMMCAsmInfoDarwin(TheTriple); MAI = new ARMMCAsmInfoDarwin(TheTriple);
else if (TheTriple.isWindowsMSVCEnvironment()) else if (TheTriple.isWindowsMSVCEnvironment())
MAI = new ARMCOFFMCAsmInfoMicrosoft(); MAI = new ARMCOFFMCAsmInfoMicrosoft();
else if (TheTriple.isOSWindows()) else if (TheTriple.isOSWindows())
MAI = new ARMCOFFMCAsmInfoGNU(); MAI = new ARMCOFFMCAsmInfoGNU();
else else
MAI = new ARMELFMCAsmInfo(TheTriple); MAI = new ARMELFMCAsmInfo(TheTriple);
unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); unsigned Reg = MCRI.getDwarfRegNum(ARM::SP, true);
MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0)); MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0));
return MAI; return MAI;
} }
static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
std::unique_ptr<MCAsmBackend> &&MAB, std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
Show All 13 LinescreateARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
return createMachOStreamer(Ctx, std::move(MAB), std::move(OW), return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
std::move(Emitter), false, DWARFMustBeAtTheEnd); std::move(Emitter), false, DWARFMustBeAtTheEnd);
} }
static MCInstPrinter *createARMMCInstPrinter(const Triple &T, static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new ARMInstPrinter(MAI, MII, MRI); return new ARMInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
MCContext &Ctx) { MCContext &Ctx) {
if (TT.isOSBinFormatMachO()) if (TT.isOSBinFormatMachO())
return createARMMachORelocationInfo(Ctx); return createARMMachORelocationInfo(Ctx);
// Default to the stock relocation info. // Default to the stock relocation info.
▲ Show 20 Lines • Show All 296 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
} }
void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
const ThumbRegisterInfo *RegInfo = const ThumbRegisterInfo *RegInfo =
static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo()); static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
const Thumb1InstrInfo &TII = const Thumb1InstrInfo &TII =
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo()); *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(); unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
unsigned NumBytes = MFI.getStackSize(); unsigned NumBytes = MFI.getStackSize();
assert(NumBytes >= ArgRegsSaveSize && assert(NumBytes >= ArgRegsSaveSize &&
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines if (HasFrameRecordArea) {
.addReg(ARM::SP) .addReg(ARM::SP)
.addImm(FramePtrOffsetInBlock / 4) .addImm(FramePtrOffsetInBlock / 4)
.setMIFlags(MachineInstr::FrameSetup) .setMIFlags(MachineInstr::FrameSetup)
.add(predOps(ARMCC::AL)); .add(predOps(ARMCC::AL));
} }
if(FramePtrOffsetInBlock) { if(FramePtrOffsetInBlock) {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
nullptr, MRI->getDwarfRegNum(FramePtr, true), (CFAOffset - FramePtrOffsetInBlock))); nullptr, MCRI->getDwarfRegNum(FramePtr, true),
(CFAOffset - FramePtrOffsetInBlock)));
BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} else { } else {
unsigned CFIIndex = unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
nullptr, MRI->getDwarfRegNum(FramePtr, true))); nullptr, MCRI->getDwarfRegNum(FramePtr, true)));
BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
} }
if (NumBytes > 508) if (NumBytes > 508)
// If offset is > 508 then sp cannot be adjusted in a single instruction, // If offset is > 508 then sp cannot be adjusted in a single instruction,
// try restoring from fp instead. // try restoring from fp instead.
AFI->setShouldRestoreSPFromFP(true); AFI->setShouldRestoreSPFromFP(true);
Show All 26 Lines for (const CalleeSavedInfo &I : CSI) {
case ARM::R2: case ARM::R2:
case ARM::R3: case ARM::R3:
case ARM::R4: case ARM::R4:
case ARM::R5: case ARM::R5:
case ARM::R6: case ARM::R6:
case ARM::R7: case ARM::R7:
case ARM::LR: case ARM::LR:
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
break; break;
} }
} }
} }
// Emit call frame information for the callee-saved high registers. // Emit call frame information for the callee-saved high registers.
if (GPRCS2Size > 0) { if (GPRCS2Size > 0) {
MachineBasicBlock::iterator Pos = std::next(GPRCS2Push); MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
for (auto &I : CSI) { for (auto &I : CSI) {
Register Reg = I.getReg(); Register Reg = I.getReg();
int FI = I.getFrameIdx(); int FI = I.getFrameIdx();
switch (Reg) { switch (Reg) {
case ARM::R8: case ARM::R8:
case ARM::R9: case ARM::R9:
case ARM::R10: case ARM::R10:
case ARM::R11: case ARM::R11:
case ARM::R12: { case ARM::R12: {
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI))); nullptr, MCRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex) .addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup); .setMIFlags(MachineInstr::FrameSetup);
break; break;
} }
default: default:
break; break;
} }
▲ Show 20 Lines • Show All 792 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/AVRAsmPrinter.cpp

Show All 39 Lines
#define DEBUG_TYPE "avr-asm-printer" #define DEBUG_TYPE "avr-asm-printer"
namespace llvm { namespace llvm {
/// An AVR assembly code printer. /// An AVR assembly code printer.
class AVRAsmPrinter : public AsmPrinter { class AVRAsmPrinter : public AsmPrinter {
public: public:
AVRAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) AVRAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) {} : AsmPrinter(TM, std::move(Streamer)), MCRI(*TM.getMCRegisterInfo()) {}
StringRef getPassName() const override { return "AVR Assembly Printer"; } StringRef getPassName() const override { return "AVR Assembly Printer"; }
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) override; const char *ExtraCode, raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
const char *ExtraCode, raw_ostream &O) override; const char *ExtraCode, raw_ostream &O) override;
void emitInstruction(const MachineInstr *MI) override; void emitInstruction(const MachineInstr *MI) override;
const MCExpr *lowerConstant(const Constant *CV) override; const MCExpr *lowerConstant(const Constant *CV) override;
void emitXXStructor(const DataLayout &DL, const Constant *CV) override; void emitXXStructor(const DataLayout &DL, const Constant *CV) override;
bool doFinalization(Module &M) override; bool doFinalization(Module &M) override;
void emitStartOfAsmFile(Module &M) override; void emitStartOfAsmFile(Module &M) override;
private: private:
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
bool EmittedStructorSymbolAttrs = false; bool EmittedStructorSymbolAttrs = false;
}; };
void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O) { raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo); const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI); O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MCRI);
break; break;
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
O << MO.getImm(); O << MO.getImm();
break; break;
case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_GlobalAddress:
O << getSymbol(MO.getGlobal()); O << getSymbol(MO.getGlobal());
break; break;
case MachineOperand::MO_ExternalSymbol: case MachineOperand::MO_ExternalSymbol:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
return true; return true;
Reg = MI->getOperand(OpNum + RegIdx).getReg(); Reg = MI->getOperand(OpNum + RegIdx).getReg();
if (BytesPerReg == 2) { if (BytesPerReg == 2) {
Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
: AVR::sub_lo); : AVR::sub_lo);
} }
O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI); O << AVRInstPrinter::getPrettyRegisterName(Reg, MCRI);
return false; return false;
} }
} }
// Print global symbols. // Print global symbols.
const auto &MO = MI->getOperand(OpNum); const auto &MO = MI->getOperand(OpNum);
if (Error && MO.getType() == MachineOperand::MO_GlobalAddress) { if (Error && MO.getType() == MachineOperand::MO_GlobalAddress) {
PrintSymbolOperand(MO, O); PrintSymbolOperand(MO, O);
▲ Show 20 Lines • Show All 186 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp

Show All 35 Lines
using namespace llvm; using namespace llvm;
namespace { namespace {
/// Parses AVR assembly from a stream. /// Parses AVR assembly from a stream.
class AVRAsmParser : public MCTargetAsmParser { class AVRAsmParser : public MCTargetAsmParser {
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
MCAsmParser &Parser; MCAsmParser &Parser;
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
const std::string GENERATE_STUBS = "gs"; const std::string GENERATE_STUBS = "gs";
enum AVRMatchResultTy { enum AVRMatchResultTy {
Match_InvalidRegisterOnTiny = FIRST_TARGET_MATCH_RESULT_TY + 1, Match_InvalidRegisterOnTiny = FIRST_TARGET_MATCH_RESULT_TY + 1,
}; };
#define GET_ASSEMBLER_HEADER #define GET_ASSEMBLER_HEADER
#include "AVRGenAsmMatcher.inc" #include "AVRGenAsmMatcher.inc"
Show All 24 Lines#include "AVRGenAsmMatcher.inc"
bool tryParseRelocExpression(OperandVector &Operands); bool tryParseRelocExpression(OperandVector &Operands);
void eatComma(); void eatComma();
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override; unsigned Kind) override;
unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) { unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID]; MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
return MRI->getMatchingSuperReg(Reg, From, Class); return MCRI->getMatchingSuperReg(Reg, From, Class);
} }
bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const; bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands, bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
uint64_t const &ErrorInfo); uint64_t const &ErrorInfo);
bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo); bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
bool parseLiteralValues(unsigned SizeInBytes, SMLoc L); bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
public: public:
AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
MCAsmParserExtension::Initialize(Parser); MCAsmParserExtension::Initialize(Parser);
MRI = getContext().getRegisterInfo(); MCRI = getContext().getRegisterInfo();
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
} }
MCAsmParser &getParser() const { return Parser; } MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); } MCAsmLexer &getLexer() const { return Parser.getLexer(); }
}; };
▲ Show 20 Lines • Show All 674 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp

Show First 20 Lines • Show All 514 Lines • ▼ Show 20 Linesbool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
case AVR::fixup_7_pcrel: case AVR::fixup_7_pcrel:
case AVR::fixup_13_pcrel: case AVR::fixup_13_pcrel:
case AVR::fixup_call: case AVR::fixup_call:
return true; return true;
} }
} }
MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const llvm::MCTargetOptions &TO) { const llvm::MCTargetOptions &TO) {
return new AVRAsmBackend(STI.getTargetTriple().getOS()); return new AVRAsmBackend(STI.getTargetTriple().getOS());
} }
} // end of namespace llvm } // end of namespace llvm

llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h

Show All 17 Lines
#include "MCTargetDesc/AVRMCTargetDesc.h" #include "MCTargetDesc/AVRMCTargetDesc.h"
namespace llvm { namespace llvm {
/// Prints AVR instructions to a textual stream. /// Prints AVR instructions to a textual stream.
class AVRInstPrinter : public MCInstPrinter { class AVRInstPrinter : public MCInstPrinter {
public: public:
AVRInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, AVRInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
static const char *getPrettyRegisterName(unsigned RegNo, static const char *getPrettyRegisterName(unsigned RegNo,
MCRegisterInfo const &MRI); MCRegisterInfo const &MCRI);
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
private: private:
static const char *getRegisterName(MCRegister Reg, static const char *getRegisterName(MCRegister Reg,
unsigned AltIdx = AVR::NoRegAltName); unsigned AltIdx = AVR::NoRegAltName);
Show All 23 Lines

llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines if (!printAliasInstr(MI, Address, O))
printInstruction(MI, Address, O); printInstruction(MI, Address, O);
printAnnotation(O, Annot); printAnnotation(O, Annot);
break; break;
} }
} }
const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum,
MCRegisterInfo const &MRI) { MCRegisterInfo const &MCRI) {
// GCC prints register pairs by just printing the lower register // GCC prints register pairs by just printing the lower register
// If the register contains a subregister, print it instead // If the register contains a subregister, print it instead
if (MRI.getNumSubRegIndices() > 0) { if (MCRI.getNumSubRegIndices() > 0) {
unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); unsigned RegLoNum = MCRI.getSubReg(RegNum, AVR::sub_lo);
RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum;
} }
return getRegisterName(RegNum); return getRegisterName(RegNum);
} }
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) { raw_ostream &O) {
Show All 20 Linesvoid AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Op.isReg()) { if (Op.isReg()) {
bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
(MOI.RegClass == AVR::PTRDISPREGSRegClassID) || (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
(MOI.RegClass == AVR::ZREGRegClassID); (MOI.RegClass == AVR::ZREGRegClassID);
if (isPtrReg) { if (isPtrReg) {
O << getRegisterName(Op.getReg(), AVR::ptr); O << getRegisterName(Op.getReg(), AVR::ptr);
} else { } else {
O << getPrettyRegisterName(Op.getReg(), MRI); O << getPrettyRegisterName(Op.getReg(), MCRI);
} }
} else if (Op.isImm()) { } else if (Op.isImm()) {
O << formatImm(Op.getImm()); O << formatImm(Op.getImm());
} else { } else {
assert(Op.isExpr() && "Unknown operand kind in printOperand"); assert(Op.isExpr() && "Unknown operand kind in printOperand");
O << *Op.getExpr(); O << *Op.getExpr();
} }
} }
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h

Show All 31 Lines
MCInstrInfo *createAVRMCInstrInfo(); MCInstrInfo *createAVRMCInstrInfo();
/// Creates a machine code emitter for AVR. /// Creates a machine code emitter for AVR.
MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
/// Creates an assembly backend for AVR. /// Creates an assembly backend for AVR.
MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const llvm::MCTargetOptions &TO); const llvm::MCTargetOptions &TO);
/// Creates an ELF object writer for AVR. /// Creates an ELF object writer for AVR.
std::unique_ptr<MCObjectTargetWriter> createAVRELFObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createAVRELFObjectWriter(uint8_t OSABI);
} // end namespace llvm } // end namespace llvm
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
Show All 10 Lines

llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesstatic MCSubtargetInfo *createAVRMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) { StringRef CPU, StringRef FS) {
return createAVRMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createAVRMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createAVRMCInstPrinter(const Triple &T, static MCInstPrinter *createAVRMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) { if (SyntaxVariant == 0) {
return new AVRInstPrinter(MAI, MII, MRI); return new AVRInstPrinter(MAI, MII, MCRI);
} }
return nullptr; return nullptr;
} }
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB, std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
BPFAsmBackend::createObjectTargetWriter() const { BPFAsmBackend::createObjectTargetWriter() const {
return createBPFELFObjectWriter(0); return createBPFELFObjectWriter(0);
} }
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &) { const MCTargetOptions &) {
return new BPFAsmBackend(support::little); return new BPFAsmBackend(support::little);
} }
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &) { const MCTargetOptions &) {
return new BPFAsmBackend(support::big); return new BPFAsmBackend(support::big);
} }

llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h

Show All 13 Lines
#define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFINSTPRINTER_H #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFINSTPRINTER_H
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class BPFInstPrinter : public MCInstPrinter { class BPFInstPrinter : public MCInstPrinter {
public: public:
BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = nullptr); const char *Modifier = nullptr);
void printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, void printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,
const char *Modifier = nullptr); const char *Modifier = nullptr);
void printImm64Operand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printImm64Operand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
Show All 10 Lines

llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp

Show All 25 Lines
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "mccodeemitter" #define DEBUG_TYPE "mccodeemitter"
namespace { namespace {
class BPFMCCodeEmitter : public MCCodeEmitter { class BPFMCCodeEmitter : public MCCodeEmitter {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
bool IsLittleEndian; bool IsLittleEndian;
public: public:
BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri, BPFMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
bool IsLittleEndian) bool IsLittleEndian)
: MRI(mri), IsLittleEndian(IsLittleEndian) { } : MCRI(mri), IsLittleEndian(IsLittleEndian) {}
BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete; BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
void operator=(const BPFMCCodeEmitter &) = delete; void operator=(const BPFMCCodeEmitter &) = delete;
~BPFMCCodeEmitter() override = default; ~BPFMCCodeEmitter() override = default;
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI, uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
Show All 26 LinesMCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false); return new BPFMCCodeEmitter(MCII, *Ctx.getRegisterInfo(), false);
} }
unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const { const MCSubtargetInfo &STI) const {
if (MO.isReg()) if (MO.isReg())
return MRI.getEncodingValue(MO.getReg()); return MCRI.getEncodingValue(MO.getReg());
if (MO.isImm()) if (MO.isImm())
return static_cast<unsigned>(MO.getImm()); return static_cast<unsigned>(MO.getImm());
assert(MO.isExpr()); assert(MO.isExpr());
const MCExpr *Expr = MO.getExpr(); const MCExpr *Expr = MO.getExpr();
assert(Expr->getKind() == MCExpr::SymbolRef); assert(Expr->getKind() == MCExpr::SymbolRef);
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesuint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
// so memory operand starts from operand 0. // so memory operand starts from operand 0.
int MemOpStartIndex = 1, Opcode = MI.getOpcode(); int MemOpStartIndex = 1, Opcode = MI.getOpcode();
if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD) if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
MemOpStartIndex = 0; MemOpStartIndex = 0;
uint64_t Encoding; uint64_t Encoding;
const MCOperand Op1 = MI.getOperand(MemOpStartIndex); const MCOperand Op1 = MI.getOperand(MemOpStartIndex);
assert(Op1.isReg() && "First operand is not register."); assert(Op1.isReg() && "First operand is not register.");
Encoding = MRI.getEncodingValue(Op1.getReg()); Encoding = MCRI.getEncodingValue(Op1.getReg());
Encoding <<= 16; Encoding <<= 16;
MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1);
assert(Op2.isImm() && "Second operand is not immediate."); assert(Op2.isImm() && "Second operand is not immediate.");
Encoding |= Op2.getImm() & 0xffff; Encoding |= Op2.getImm() & 0xffff;
return Encoding; return Encoding;
} }
#include "BPFGenMCCodeEmitter.inc" #include "BPFGenMCCodeEmitter.inc"

llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h

Show All 30 Lines
class Target; class Target;
MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createBPFELFObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createBPFELFObjectWriter(uint8_t OSABI);
} }
// Defines symbolic names for BPF registers. This defines a mapping from // Defines symbolic names for BPF registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
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llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Linesstatic MCStreamer *createBPFMCStreamer(const Triple &T, MCContext &Ctx,
return createELFStreamer(Ctx, std::move(MAB), std::move(OW), std::move(Emitter), return createELFStreamer(Ctx, std::move(MAB), std::move(OW), std::move(Emitter),
RelaxAll); RelaxAll);
} }
static MCInstPrinter *createBPFMCInstPrinter(const Triple &T, static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new BPFInstPrinter(MAI, MII, MRI); return new BPFInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
namespace { namespace {
class BPFMCInstrAnalysis : public MCInstrAnalysis { class BPFMCInstrAnalysis : public MCInstrAnalysis {
public: public:
explicit BPFMCInstrAnalysis(const MCInstrInfo *Info) explicit BPFMCInstrAnalysis(const MCInstrInfo *Info)
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llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines EnableCompressedInst("enable-csky-asm-compressed-inst", cl::Hidden,
cl::init(false), cl::init(false),
cl::desc("Enable C-SKY asm compressed instruction")); cl::desc("Enable C-SKY asm compressed instruction"));
namespace { namespace {
struct CSKYOperand; struct CSKYOperand;
class CSKYAsmParser : public MCTargetAsmParser { class CSKYAsmParser : public MCTargetAsmParser {
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override; unsigned Kind) override;
bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo, bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
int64_t Lower, int64_t Upper, Twine Msg); int64_t Lower, int64_t Upper, Twine Msg);
SMLoc getLoc() const { return getParser().getTok().getLoc(); } SMLoc getLoc() const { return getParser().getTok().getLoc(); }
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines#undef GET_OPERAND_DIAGNOSTIC_TYPES
CSKYAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, CSKYAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII) { : MCTargetAsmParser(Options, STI, MII) {
MCAsmParserExtension::Initialize(Parser); MCAsmParserExtension::Initialize(Parser);
// Cache the MCRegisterInfo. // Cache the MCRegisterInfo.
MRI = getContext().getRegisterInfo(); MCRI = getContext().getRegisterInfo();
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
getTargetStreamer().emitTargetAttributes(STI); getTargetStreamer().emitTargetAttributes(STI);
} }
}; };
/// Instances of this class represent a parsed machine instruction. /// Instances of this class represent a parsed machine instruction.
struct CSKYOperand : public MCParsedAsmOperand { struct CSKYOperand : public MCParsedAsmOperand {
▲ Show 20 Lines • Show All 1,585 Lines • ▼ Show 20 Lines if (Kind == MCK_FPR64 || Kind == MCK_sFPR64) {
(Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F31_64)) (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F31_64))
return Match_InvalidRegOutOfRange; return Match_InvalidRegOutOfRange;
return Match_Success; return Match_Success;
} }
} }
if (CSKYMCRegisterClasses[CSKY::GPRRegClassID].contains(Reg)) { if (CSKYMCRegisterClasses[CSKY::GPRRegClassID].contains(Reg)) {
if (Kind == MCK_GPRPair) { if (Kind == MCK_GPRPair) {
Op.Reg.RegNum = MRI->getEncodingValue(Reg) + CSKY::R0_R1; Op.Reg.RegNum = MCRI->getEncodingValue(Reg) + CSKY::R0_R1;
return Match_Success; return Match_Success;
} }
} }
return Match_InvalidOperand; return Match_InvalidOperand;
} }
void CSKYAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { void CSKYAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
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llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

Show First 20 Lines • Show All 346 Lines • ▼ Show 20 Lines
bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
const MCSubtargetInfo *STI) const { const MCSubtargetInfo *STI) const {
OS.write_zeros(Count); OS.write_zeros(Count);
return true; return true;
} }
MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T, MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new CSKYAsmBackend(STI, Options); return new CSKYAsmBackend(STI, Options);
} }

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h

Show All 18 Lines
namespace llvm { namespace llvm {
class CSKYInstPrinter : public MCInstPrinter { class CSKYInstPrinter : public MCInstPrinter {
private: private:
bool ABIRegNames = false; bool ABIRegNames = false;
public: public:
CSKYInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, CSKYInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
bool applyTargetSpecificCLOption(StringRef Opt) override; bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, MCRegister Reg) const override; void printRegName(raw_ostream &O, MCRegister Reg) const override;
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h

Show All 25 Lines
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple; class Triple;
std::unique_ptr<MCObjectTargetWriter> createCSKYELFObjectWriter(); std::unique_ptr<MCObjectTargetWriter> createCSKYELFObjectWriter();
MCAsmBackend *createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx);
} // namespace llvm } // namespace llvm
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
#include "CSKYGenRegisterInfo.inc" #include "CSKYGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM #define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_MC_HELPER_DECLS #define GET_INSTRINFO_MC_HELPER_DECLS
#include "CSKYGenInstrInfo.inc" #include "CSKYGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_ENUM
#include "CSKYGenSubtargetInfo.inc" #include "CSKYGenSubtargetInfo.inc"
#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCTARGETDESC_H #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCTARGETDESC_H

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp

Show All 31 Lines
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "CSKYGenRegisterInfo.inc" #include "CSKYGenRegisterInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "CSKYGenSubtargetInfo.inc" #include "CSKYGenSubtargetInfo.inc"
using namespace llvm; using namespace llvm;
static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new CSKYMCAsmInfo(TT); MCAsmInfo *MAI = new CSKYMCAsmInfo(TT);
// Initial state of the frame pointer is SP. // Initial state of the frame pointer is SP.
unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true); unsigned Reg = MCRI.getDwarfRegNum(CSKY::R14, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstrInfo *createCSKYMCInstrInfo() { static MCInstrInfo *createCSKYMCInstrInfo() {
MCInstrInfo *Info = new MCInstrInfo(); MCInstrInfo *Info = new MCInstrInfo();
InitCSKYMCInstrInfo(Info); InitCSKYMCInstrInfo(Info);
return Info; return Info;
} }
static MCInstPrinter *createCSKYMCInstPrinter(const Triple &T, static MCInstPrinter *createCSKYMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new CSKYInstPrinter(MAI, MII, MRI); return new CSKYInstPrinter(MAI, MII, MCRI);
} }
static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) { static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *Info = new MCRegisterInfo(); MCRegisterInfo *Info = new MCRegisterInfo();
InitCSKYMCRegisterInfo(Info, CSKY::R15); InitCSKYMCRegisterInfo(Info, CSKY::R15);
return Info; return Info;
} }
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llvm/lib/Target/DirectX/MCTargetDesc/DirectXMCTargetDesc.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
#include "DirectXGenRegisterInfo.inc" #include "DirectXGenRegisterInfo.inc"
namespace { namespace {
// DXILInstPrinter is a null stub because DXIL instructions aren't printed. // DXILInstPrinter is a null stub because DXIL instructions aren't printed.
class DXILInstPrinter : public MCInstPrinter { class DXILInstPrinter : public MCInstPrinter {
public: public:
DXILInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, DXILInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override {} const MCSubtargetInfo &STI, raw_ostream &O) override {}
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override { std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override {
return std::make_pair<const char *, uint64_t>("", 0ull); return std::make_pair<const char *, uint64_t>("", 0ull);
} }
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
}; };
} // namespace } // namespace
static MCInstPrinter *createDXILMCInstPrinter(const Triple &T, static MCInstPrinter *createDXILMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new DXILInstPrinter(MAI, MII, MRI); return new DXILInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
MCCodeEmitter *createDXILMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createDXILMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx) { MCContext &Ctx) {
return new DXILMCCodeEmitter(); return new DXILMCCodeEmitter();
} }
MCAsmBackend *createDXILMCAsmBackend(const Target &T, MCAsmBackend *createDXILMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new DXILAsmBackend(STI); return new DXILAsmBackend(STI);
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createDirectXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createDirectXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createDirectXMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createDirectXMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

Show First 20 Lines • Show All 767 Lines • ▼ Show 20 Linespublic:
} }
}; // class HexagonAsmBackend }; // class HexagonAsmBackend
} // namespace } // namespace
// MCAsmBackend // MCAsmBackend
MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
MCRegisterInfo const & /*MRI*/, MCRegisterInfo const & /*MCRI*/,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU()); StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
return new HexagonAsmBackend(T, TT, OSABI, CPUString); return new HexagonAsmBackend(T, TT, OSABI, CPUString);
} }

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h

Show All 19 Lines
/// A trailing line includes bundle properties such as endloop0/1 /// A trailing line includes bundle properties such as endloop0/1
/// ///
/// r0 = add(r1, r2) /// r0 = add(r1, r2)
/// r0 = #0 \v jump 0x0 /// r0 = #0 \v jump 0x0
/// :endloop0 :endloop1 /// :endloop0 :endloop1
class HexagonInstPrinter : public MCInstPrinter { class HexagonInstPrinter : public MCInstPrinter {
public: public:
explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII, explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII,
MCRegisterInfo const &MRI) MCRegisterInfo const &MCRI)
: MCInstPrinter(MAI, MII, MRI), MII(MII) {} : MCInstPrinter(MAI, MII, MCRI), MII(MII) {}
void printInst(MCInst const *MI, uint64_t Address, StringRef Annot, void printInst(MCInst const *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, MCRegister Reg) const override; void printRegName(raw_ostream &O, MCRegister Reg) const override;
static char const *getRegisterName(MCRegister Reg); static char const *getRegisterName(MCRegister Reg);
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI); bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI); bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI); bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
// Return whether the predicate sense is true // Return whether the predicate sense is true
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI); bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
// Return true if this is a scalar predicate register. // Return true if this is a scalar predicate register.
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg); bool isPredReg(MCRegisterInfo const &MCRI, unsigned Reg);
// Returns true if the Ith operand is a predicate register. // Returns true if the Ith operand is a predicate register.
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I); bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
// Return whether the insn is a prefix. // Return whether the insn is a prefix.
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI); bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
// Return whether the insn is solo, i.e., cannot be in a packet. // Return whether the insn is solo, i.e., cannot be in a packet.
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

Show First 20 Lines • Show All 746 Lines • ▼ Show 20 Lines
bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII, bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
MCInst const &MCI) { MCInst const &MCI) {
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
return ( return (
!((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask)); !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
} }
bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, unsigned Reg) { bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MCRI, unsigned Reg) {
auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID); auto &PredRegClass = MCRI.getRegClass(Hexagon::PredRegsRegClassID);
return PredRegClass.contains(Reg); return PredRegClass.contains(Reg);
} }
bool HexagonMCInstrInfo::isPredRegister(MCInstrInfo const &MCII, bool HexagonMCInstrInfo::isPredRegister(MCInstrInfo const &MCII,
MCInst const &Inst, unsigned I) { MCInst const &Inst, unsigned I) {
MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst);
return Inst.getOperand(I).isReg() && return Inst.getOperand(I).isReg() &&
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Linesnamespace Hexagon_MC {
llvm::ArrayRef<MCPhysReg> GetVectRegRev(); llvm::ArrayRef<MCPhysReg> GetVectRegRev();
} }
MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &MCT); MCContext &MCT);
MCAsmBackend *createHexagonAsmBackend(const Target &T, MCAsmBackend *createHexagonAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU); createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
unsigned HexagonGetLastSlot(); unsigned HexagonGetLastSlot();
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes); unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
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llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

Show First 20 Lines • Show All 308 Lines • ▼ Show 20 Lines
static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0, InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0,
/*EHFlavour=*/0, /*PC=*/Hexagon::PC); /*EHFlavour=*/0, /*PC=*/Hexagon::PC);
return X; return X;
} }
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
// VirtualFP = (R30 + #0). // VirtualFP = (R30 + #0).
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0); nullptr, MCRI.getDwarfRegNum(Hexagon::R30, true), 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI) {
{
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new HexagonInstPrinter(MAI, MII, MRI); return new HexagonInstPrinter(MAI, MII, MCRI);
else else
return nullptr; return nullptr;
} }
static MCTargetStreamer * static MCTargetStreamer *
createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
MCInstPrinter *IP, bool IsVerboseAsm) { MCInstPrinter *IP, bool IsVerboseAsm) {
return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP); return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
▲ Show 20 Lines • Show All 357 Lines • Show Last 20 Lines

llvm/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!"); "Invalid kind!");
return Infos[Kind - FirstTargetFixupKind]; return Infos[Kind - FirstTargetFixupKind];
} }
} // namespace } // namespace
MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T, MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo & /*MRI*/, const MCRegisterInfo & /*MCRI*/,
const MCTargetOptions & /*Options*/) { const MCTargetOptions & /*Options*/) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
if (!TT.isOSBinFormatELF()) if (!TT.isOSBinFormatELF())
llvm_unreachable("OS not supported"); llvm_unreachable("OS not supported");
return new LanaiAsmBackend(T, TT.getOS()); return new LanaiAsmBackend(T, TT.getOS());
} }

llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h

Show All 15 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class StringRef; class StringRef;
class LanaiInstPrinter : public MCInstPrinter { class LanaiInstPrinter : public MCInstPrinter {
public: public:
LanaiInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, LanaiInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
const char *Modifier = nullptr); const char *Modifier = nullptr);
void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O, void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O,
const char *Modifier = nullptr); const char *Modifier = nullptr);
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llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h

Show All 24 Lines
class MCObjectTargetWriter; class MCObjectTargetWriter;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createLanaiELFObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createLanaiELFObjectWriter(uint8_t OSABI);
} // namespace llvm } // namespace llvm
// Defines symbolic names for Lanai registers. This defines a mapping from // Defines symbolic names for Lanai registers. This defines a mapping from
// register name to register number. // register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
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llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Linesstatic MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
return createELFStreamer(Context, std::move(MAB), std::move(OW), return createELFStreamer(Context, std::move(MAB), std::move(OW),
std::move(Emitter), RelaxAll); std::move(Emitter), RelaxAll);
} }
static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/, static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new LanaiInstPrinter(MAI, MII, MRI); return new LanaiInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple, static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple,
MCContext &Ctx) { MCContext &Ctx) {
return createMCRelocationInfo(TheTriple, Ctx); return createMCRelocationInfo(TheTriple, Ctx);
} }
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llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
LoongArchAsmBackend::createObjectTargetWriter() const { LoongArchAsmBackend::createObjectTargetWriter() const {
return createLoongArchELFObjectWriter(OSABI, Is64Bit); return createLoongArchELFObjectWriter(OSABI, Is64Bit);
} }
MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T, MCAsmBackend *llvm::createLoongArchAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit()); return new LoongArchAsmBackend(STI, OSABI, TT.isArch64Bit());
} }

llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h

Show All 15 Lines
#include "MCTargetDesc/LoongArchMCTargetDesc.h" #include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class LoongArchInstPrinter : public MCInstPrinter { class LoongArchInstPrinter : public MCInstPrinter {
public: public:
LoongArchInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, LoongArchInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
bool applyTargetSpecificCLOption(StringRef Opt) override; bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, MCRegister Reg) const override; void printRegName(raw_ostream &O, MCRegister Reg) const override;
void printAtomicMemOp(const MCInst *MI, unsigned OpNo, void printAtomicMemOp(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
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llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.h

Show All 26 Lines
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
MCCodeEmitter *createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createLoongArchMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createLoongArchAsmBackend(const Target &T, MCAsmBackend *createLoongArchAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit); createLoongArchELFObjectWriter(uint8_t OSABI, bool Is64Bit);
} // end namespace llvm } // end namespace llvm
// Defines symbolic names for LoongArch registers. // Defines symbolic names for LoongArch registers.
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llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
static MCSubtargetInfo * static MCSubtargetInfo *
createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty() || CPU == "generic") if (CPU.empty() || CPU == "generic")
CPU = TT.isArch64Bit() ? "la464" : "generic-la32"; CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT); MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);
// Initial state of the frame pointer is sp(r3). // Initial state of the frame pointer is sp(r3).
MCRegister SP = MRI.getDwarfRegNum(LoongArch::R3, true); MCRegister SP = MCRI.getDwarfRegNum(LoongArch::R3, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T, static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new LoongArchInstPrinter(MAI, MII, MRI); return new LoongArchInstPrinter(MAI, MII, MCRI);
} }
static MCTargetStreamer * static MCTargetStreamer *
createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { createLoongArchObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
return STI.getTargetTriple().isOSBinFormatELF() return STI.getTargetTriple().isOSBinFormatELF()
? new LoongArchTargetELFStreamer(S, STI) ? new LoongArchTargetELFStreamer(S, STI)
: nullptr; : nullptr;
} }
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llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

Show All 27 Linesstatic cl::opt<bool> RegisterPrefixOptional(
cl::desc("Enable specifying registers without the % prefix"), cl::desc("Enable specifying registers without the % prefix"),
cl::init(false)); cl::init(false));
namespace { namespace {
/// Parses M68k assembly from a stream. /// Parses M68k assembly from a stream.
class M68kAsmParser : public MCTargetAsmParser { class M68kAsmParser : public MCTargetAsmParser {
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
MCAsmParser &Parser; MCAsmParser &Parser;
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
#define GET_ASSEMBLER_HEADER #define GET_ASSEMBLER_HEADER
#include "M68kGenAsmMatcher.inc" #include "M68kGenAsmMatcher.inc"
// Helpers for Match&Emit. // Helpers for Match&Emit.
bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands, bool invalidOperand(const SMLoc &Loc, const OperandVector &Operands,
const uint64_t &ErrorInfo); const uint64_t &ErrorInfo);
bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo); bool missingFeature(const SMLoc &Loc, const uint64_t &ErrorInfo);
Show All 9 Lines#include "M68kGenAsmMatcher.inc"
OperandMatchResultTy parseMemOp(OperandVector &Operands); OperandMatchResultTy parseMemOp(OperandVector &Operands);
OperandMatchResultTy parseRegOrMoveMask(OperandVector &Operands); OperandMatchResultTy parseRegOrMoveMask(OperandVector &Operands);
public: public:
M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
MCAsmParserExtension::Initialize(Parser); MCAsmParserExtension::Initialize(Parser);
MRI = getContext().getRegisterInfo(); MCRI = getContext().getRegisterInfo();
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
} }
unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
unsigned Kind) override; unsigned Kind) override;
bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc, bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override; SMLoc &EndLoc) override;
▲ Show 20 Lines • Show All 960 Lines • Show Last 20 Lines

llvm/lib/Target/M68k/M68kFrameLowering.cpp

Show First 20 Lines • Show All 447 Lines • ▼ Show 20 Lines
} }
void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves( void M68kFrameLowering::emitPrologueCalleeSavedFrameMoves(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL) const { const DebugLoc &DL) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
// Add callee saved registers to move list. // Add callee saved registers to move list.
const auto &CSI = MFI.getCalleeSavedInfo(); const auto &CSI = MFI.getCalleeSavedInfo();
if (CSI.empty()) if (CSI.empty())
return; return;
// Calculate offsets. // Calculate offsets.
for (const auto &I : CSI) { for (const auto &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
Register Reg = I.getReg(); Register Reg = I.getReg();
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true);
BuildCFI(MBB, MBBI, DL, BuildCFI(MBB, MBBI, DL,
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
} }
} }
void M68kFrameLowering::emitPrologue(MachineFunction &MF, void M68kFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
assert(&STI == &MF.getSubtarget<M68kSubtarget>() && assert(&STI == &MF.getSubtarget<M68kSubtarget>() &&
▲ Show 20 Lines • Show All 418 Lines • Show Last 20 Lines

llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines createObjectTargetWriter() const override {
return createM68kELFObjectWriter(OSABI); return createM68kELFObjectWriter(OSABI);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createM68kAsmBackend(const Target &T, MCAsmBackend *llvm::createM68kAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
return new M68kELFAsmBackend(T, OSABI); return new M68kELFAsmBackend(T, OSABI);
} }

llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h

Show All 17 Lines
namespace llvm { namespace llvm {
class TargetMachine; class TargetMachine;
class M68kInstPrinter : public MCInstPrinter { class M68kInstPrinter : public MCInstPrinter {
public: public:
M68kInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, M68kInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Autogenerated by tblgen. // Autogenerated by tblgen.
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.h

Show All 28 Lines
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
class StringRef; class StringRef;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
MCAsmBackend *createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createM68kAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCCodeEmitter *createM68kMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createM68kMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
/// Construct an M68k ELF object writer. /// Construct an M68k ELF object writer.
std::unique_ptr<MCObjectTargetWriter> createM68kELFObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createM68kELFObjectWriter(uint8_t OSABI);
Show All 16 Lines

llvm/lib/Target/M68k/MCTargetDesc/M68kMCTargetDesc.cpp

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines if (!ArchFS.empty()) {
ArchFS = (ArchFS + "," + FS).str(); ArchFS = (ArchFS + "," + FS).str();
} else { } else {
ArchFS = FS.str(); ArchFS = FS.str();
} }
} }
return createM68kMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, ArchFS); return createM68kMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, ArchFS);
} }
static MCAsmInfo *createM68kMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createM68kMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &TO) { const MCTargetOptions &TO) {
MCAsmInfo *MAI = new M68kELFMCAsmInfo(TT); MCAsmInfo *MAI = new M68kELFMCAsmInfo(TT);
// Initialize initial frame state. // Initialize initial frame state.
// Calculate amount of bytes used for return address storing // Calculate amount of bytes used for return address storing
int StackGrowth = -4; int StackGrowth = -4;
// Initial state of the frame pointer is SP+StackGrowth. // Initial state of the frame pointer is SP+StackGrowth.
// TODO: Add tests for `cfi_*` directives // TODO: Add tests for `cfi_*` directives
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
nullptr, MRI.getDwarfRegNum(llvm::M68k::SP, true), -StackGrowth); nullptr, MCRI.getDwarfRegNum(llvm::M68k::SP, true), -StackGrowth);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
// Add return address to move list // Add return address to move list
Inst = MCCFIInstruction::createOffset( Inst = MCCFIInstruction::createOffset(
nullptr, MRI.getDwarfRegNum(M68k::PC, true), StackGrowth); nullptr, MCRI.getDwarfRegNum(M68k::PC, true), StackGrowth);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCRelocationInfo *createM68kMCRelocationInfo(const Triple &TheTriple, static MCRelocationInfo *createM68kMCRelocationInfo(const Triple &TheTriple,
MCContext &Ctx) { MCContext &Ctx) {
// Default to the stock relocation info. // Default to the stock relocation info.
return llvm::createMCRelocationInfo(TheTriple, Ctx); return llvm::createMCRelocationInfo(TheTriple, Ctx);
} }
static MCInstPrinter *createM68kMCInstPrinter(const Triple &T, static MCInstPrinter *createM68kMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new M68kInstPrinter(MAI, MII, MRI); return new M68kInstPrinter(MAI, MII, MCRI);
} }
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTargetMC() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTargetMC() {
Target &T = getTheM68kTarget(); Target &T = getTheM68kTarget();
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(T, createM68kMCAsmInfo); RegisterMCAsmInfoFn X(T, createM68kMCAsmInfo);
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llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp

Show All 32 Lines
using namespace llvm; using namespace llvm;
namespace { namespace {
/// Parses MSP430 assembly from a stream. /// Parses MSP430 assembly from a stream.
class MSP430AsmParser : public MCTargetAsmParser { class MSP430AsmParser : public MCTargetAsmParser {
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
MCAsmParser &Parser; MCAsmParser &Parser;
const MCRegisterInfo *MRI; const MCRegisterInfo *MCRI;
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out, OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo, uint64_t &ErrorInfo,
bool MatchingInlineAsm) override; bool MatchingInlineAsm) override;
bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc, bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
SMLoc &EndLoc) override; SMLoc &EndLoc) override;
Show All 27 Lines#include "MSP430GenAsmMatcher.inc"
/// } /// }
public: public:
MSP430AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, MSP430AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options) const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) { : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
MCAsmParserExtension::Initialize(Parser); MCAsmParserExtension::Initialize(Parser);
MRI = getContext().getRegisterInfo(); MCRI = getContext().getRegisterInfo();
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
} }
}; };
/// A parsed MSP430 assembly operand. /// A parsed MSP430 assembly operand.
class MSP430Operand : public MCParsedAsmOperand { class MSP430Operand : public MCParsedAsmOperand {
typedef MCParsedAsmOperand Base; typedef MCParsedAsmOperand Base;
▲ Show 20 Lines • Show All 506 Lines • Show Last 20 Lines

llvm/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Linesbool MSP430AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
return true; return true;
} }
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createMSP430MCAsmBackend(const Target &T, MCAsmBackend *llvm::createMSP430MCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new MSP430AsmBackend(STI, ELF::ELFOSABI_STANDALONE); return new MSP430AsmBackend(STI, ELF::ELFOSABI_STANDALONE);
} }

llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h

Show All 13 Lines
#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430INSTPRINTER_H #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430INSTPRINTER_H
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class MSP430InstPrinter : public MCInstPrinter { class MSP430InstPrinter : public MCInstPrinter {
public: public:
MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &O); bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &O);
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llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h

Show All 29 Lines
class MCTargetStreamer; class MCTargetStreamer;
/// Creates a machine code emitter for MSP430. /// Creates a machine code emitter for MSP430.
MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createMSP430MCAsmBackend(const Target &T, MCAsmBackend *createMSP430MCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCTargetStreamer * MCTargetStreamer *
createMSP430ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI); createMSP430ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createMSP430ELFObjectWriter(uint8_t OSABI); createMSP430ELFObjectWriter(uint8_t OSABI);
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llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp

Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createMSP430MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createMSP430MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T, static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new MSP430InstPrinter(MAI, MII, MRI); return new MSP430InstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430TargetMC() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMSP430TargetMC() {
Target &T = getTheMSP430Target(); Target &T = getTheMSP430Target();
RegisterMCAsmInfo<MSP430MCAsmInfo> X(T); RegisterMCAsmInfo<MSP430MCAsmInfo> X(T);
TargetRegistry::RegisterMCInstrInfo(T, createMSP430MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(T, createMSP430MCInstrInfo);
TargetRegistry::RegisterMCRegInfo(T, createMSP430MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(T, createMSP430MCRegisterInfo);
TargetRegistry::RegisterMCSubtargetInfo(T, createMSP430MCSubtargetInfo); TargetRegistry::RegisterMCSubtargetInfo(T, createMSP430MCSubtargetInfo);
TargetRegistry::RegisterMCInstPrinter(T, createMSP430MCInstPrinter); TargetRegistry::RegisterMCInstPrinter(T, createMSP430MCInstPrinter);
TargetRegistry::RegisterMCCodeEmitter(T, createMSP430MCCodeEmitter); TargetRegistry::RegisterMCCodeEmitter(T, createMSP430MCCodeEmitter);
TargetRegistry::RegisterMCAsmBackend(T, createMSP430MCAsmBackend); TargetRegistry::RegisterMCAsmBackend(T, createMSP430MCAsmBackend);
TargetRegistry::RegisterObjectTargetStreamer( TargetRegistry::RegisterObjectTargetStreamer(
T, createMSP430ObjectTargetStreamer); T, createMSP430ObjectTargetStreamer);
} }

llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h

Show All 24 Lines
class MCRegisterInfo; class MCRegisterInfo;
class Target; class Target;
class MipsAsmBackend : public MCAsmBackend { class MipsAsmBackend : public MCAsmBackend {
Triple TheTriple; Triple TheTriple;
bool IsN32; bool IsN32;
public: public:
MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, MipsAsmBackend(const Target &T, const MCRegisterInfo &MCRI, const Triple &TT,
StringRef CPU, bool N32) StringRef CPU, bool N32)
: MCAsmBackend(TT.isLittleEndian() ? support::little : support::big), : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
TheTriple(TT), IsN32(N32) {} TheTriple(TT), IsN32(N32) {}
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createObjectTargetWriter() const override; createObjectTargetWriter() const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
Show All 36 Lines

llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

Show First 20 Lines • Show All 591 Lines • ▼ Show 20 Lines if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) {
if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS)
return true; return true;
} }
return false; return false;
} }
MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(), MipsABIInfo ABI = MipsABIInfo::computeTargetABI(STI.getTargetTriple(),
STI.getCPU(), Options); STI.getCPU(), Options);
return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), return new MipsAsmBackend(T, MCRI, STI.getTargetTriple(), STI.getCPU(),
ABI.IsN32()); ABI.IsN32());
} }

llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
}; };
const char *MipsFCCToString(Mips::CondCode CC); const char *MipsFCCToString(Mips::CondCode CC);
} // end namespace Mips } // end namespace Mips
class MipsInstPrinter : public MCInstPrinter { class MipsInstPrinter : public MCInstPrinter {
public: public:
MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, void printInstruction(const MCInst *MI, uint64_t Address,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
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llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

Show All 30 Lines
class Triple; class Triple;
MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createMipsELFObjectWriter(const Triple &TT, bool IsN32); createMipsELFObjectWriter(const Triple &TT, bool IsN32);
namespace MIPS_MC { namespace MIPS_MC {
StringRef selectMipsCPU(const Triple &TT, StringRef CPU); StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
} }
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llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
} }
static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) { StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU); CPU = MIPS_MC::selectMipsCPU(TT, CPU);
return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options); MCAsmInfo *MAI = new MipsMCAsmInfo(TT, Options);
unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); unsigned SP = MCRI.getDwarfRegNum(Mips::SP, true);
MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new MipsInstPrinter(MAI, MII, MRI); return new MipsInstPrinter(MAI, MII, MCRI);
} }
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB, std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW, std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter, std::unique_ptr<MCCodeEmitter> &&Emitter,
bool RelaxAll) { bool RelaxAll) {
MCStreamer *S; MCStreamer *S;
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llvm/lib/Target/Mips/Mips16FrameLowering.cpp

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesvoid Mips16FrameLowering::emitPrologue(MachineFunction &MF,
DebugLoc dl; DebugLoc dl;
uint64_t StackSize = MFI.getStackSize(); uint64_t StackSize = MFI.getStackSize();
// No need to allocate space on the stack. // No need to allocate space on the stack.
if (StackSize == 0 && !MFI.adjustsStack()) return; if (StackSize == 0 && !MFI.adjustsStack()) return;
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
// Adjust stack. // Adjust stack.
TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
// emit ".cfi_def_cfa_offset StackSize" // emit ".cfi_def_cfa_offset StackSize"
unsigned CFIIndex = unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
if (!CSI.empty()) { if (!CSI.empty()) {
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
for (const CalleeSavedInfo &I : CSI) { for (const CalleeSavedInfo &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
Register Reg = I.getReg(); Register Reg = I.getReg();
unsigned DReg = MRI->getDwarfRegNum(Reg, true); unsigned DReg = MCRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, DReg, Offset)); MCCFIInstruction::createOffset(nullptr, DReg, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
if (hasFP(MF)) if (hasFP(MF))
BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0) BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
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llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

Show First 20 Lines • Show All 422 Lines • ▼ Show 20 Linesvoid MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
// First, compute final stack size. // First, compute final stack size.
uint64_t StackSize = MFI.getStackSize(); uint64_t StackSize = MFI.getStackSize();
// No need to allocate space on the stack. // No need to allocate space on the stack.
if (StackSize == 0 && !MFI.adjustsStack()) return; if (StackSize == 0 && !MFI.adjustsStack()) return;
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
// Adjust stack. // Adjust stack.
TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
// emit ".cfi_def_cfa_offset StackSize" // emit ".cfi_def_cfa_offset StackSize"
unsigned CFIIndex = unsigned CFIIndex =
MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Show All 15 Lines if (!CSI.empty()) {
for (const CalleeSavedInfo &I : CSI) { for (const CalleeSavedInfo &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
Register Reg = I.getReg(); Register Reg = I.getReg();
// If Reg is a double precision register, emit two cfa_offsets, // If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers. // one for each of the paired single precision registers.
if (Mips::AFGR64RegClass.contains(Reg)) { if (Mips::AFGR64RegClass.contains(Reg)) {
unsigned Reg0 = unsigned Reg0 =
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true); MCRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
unsigned Reg1 = unsigned Reg1 =
MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); MCRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
if (!STI.isLittle()) if (!STI.isLittle())
std::swap(Reg0, Reg1); std::swap(Reg0, Reg1);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} else if (Mips::FGR64RegClass.contains(Reg)) { } else if (Mips::FGR64RegClass.contains(Reg)) {
unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); unsigned Reg0 = MCRI->getDwarfRegNum(Reg, true);
unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; unsigned Reg1 = MCRI->getDwarfRegNum(Reg, true) + 1;
if (!STI.isLittle()) if (!STI.isLittle())
std::swap(Reg0, Reg1); std::swap(Reg0, Reg1);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} else { } else {
// Reg is either in GPR32 or FGR32. // Reg is either in GPR32 or FGR32.
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); nullptr, MCRI->getDwarfRegNum(Reg, true), Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
} }
if (MipsFI->callsEhReturn()) { if (MipsFI->callsEhReturn()) {
// Insert instructions that spill eh data registers. // Insert instructions that spill eh data registers.
for (int I = 0; I < 4; ++I) { for (int I = 0; I < 4; ++I) {
if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) if (!MBB.isLiveIn(ABI.GetEhDataReg(I)))
MBB.addLiveIn(ABI.GetEhDataReg(I)); MBB.addLiveIn(ABI.GetEhDataReg(I));
TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,
MipsFI->getEhDataRegFI(I), RC, &RegInfo, MipsFI->getEhDataRegFI(I), RC, &RegInfo,
Register()); Register());
} }
// Emit .cfi_offset directives for eh data registers. // Emit .cfi_offset directives for eh data registers.
for (int I = 0; I < 4; ++I) { for (int I = 0; I < 4; ++I) {
int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); unsigned Reg = MCRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, Offset)); MCCFIInstruction::createOffset(nullptr, Reg, Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
// if framepointer enabled, set it to point to the stack pointer. // if framepointer enabled, set it to point to the stack pointer.
if (hasFP(MF)) { if (hasFP(MF)) {
// Insert instruction "move $fp, $sp" at this location. // Insert instruction "move $fp, $sp" at this location.
BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO) BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
// emit ".cfi_def_cfa_register $fp" // emit ".cfi_def_cfa_register $fp"
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
nullptr, MRI->getDwarfRegNum(FP, true))); nullptr, MCRI->getDwarfRegNum(FP, true)));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
if (RegInfo.hasStackRealignment(MF)) { if (RegInfo.hasStackRealignment(MF)) {
// addiu $Reg, $zero, -MaxAlignment // addiu $Reg, $zero, -MaxAlignment
// andi $sp, $sp, $Reg // andi $sp, $sp, $Reg
Register VR = MF.getRegInfo().createVirtualRegister(RC); Register VR = MF.getRegInfo().createVirtualRegister(RC);
assert((Log2(MFI.getMaxAlign()) < 16) && assert((Log2(MFI.getMaxAlign()) < 16) &&
▲ Show 20 Lines • Show All 379 Lines • Show Last 20 Lines

llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h

Show All 16 Lines
namespace llvm { namespace llvm {
class MCSubtargetInfo; class MCSubtargetInfo;
class NVPTXInstPrinter : public MCInstPrinter { class NVPTXInstPrinter : public MCInstPrinter {
public: public:
NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override; const MCSubtargetInfo &STI, raw_ostream &OS) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
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llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp

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#include <cctype> #include <cctype>
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "asm-printer" #define DEBUG_TYPE "asm-printer"
#include "NVPTXGenAsmWriter.inc" #include "NVPTXGenAsmWriter.inc"
NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
// Decode the virtual register // Decode the virtual register
// Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister // Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister
unsigned RCId = (Reg.id() >> 28); unsigned RCId = (Reg.id() >> 28);
switch (RCId) { switch (RCId) {
default: report_fatal_error("Bad virtual register encoding"); default: report_fatal_error("Bad virtual register encoding");
case 0: case 0:
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llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp

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createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createNVPTXMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createNVPTXMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T, static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new NVPTXInstPrinter(MAI, MII, MRI); return new NVPTXInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &, formatted_raw_ostream &,
MCInstPrinter *, bool) { MCInstPrinter *, bool) {
return new NVPTXAsmTargetStreamer(S); return new NVPTXAsmTargetStreamer(S);
} }
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llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

Show First 20 Lines • Show All 268 Lines • ▼ Show 20 Lines#undef ELF_RELOC
if (Type != -1u) if (Type != -1u)
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
} }
return std::nullopt; return std::nullopt;
} }
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
if (TT.isOSBinFormatXCOFF()) if (TT.isOSBinFormatXCOFF())
return new XCOFFPPCAsmBackend(T, TT); return new XCOFFPPCAsmBackend(T, TT);
return new ELFPPCAsmBackend(T, TT); return new ELFPPCAsmBackend(T, TT);
} }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h

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private: private:
bool showRegistersWithPercentPrefix(const char *RegName) const; bool showRegistersWithPercentPrefix(const char *RegName) const;
bool showRegistersWithPrefix() const; bool showRegistersWithPrefix() const;
const char *getVerboseConditionRegName(unsigned RegNum, const char *getVerboseConditionRegName(unsigned RegNum,
unsigned RegEncoding) const; unsigned RegEncoding) const;
public: public:
PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, Triple T) const MCRegisterInfo &MCRI, Triple T)
: MCInstPrinter(MAI, MII, MRI), TT(T) {} : MCInstPrinter(MAI, MII, MCRI), TT(T) {}
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, void printInstruction(const MCInst *MI, uint64_t Address,
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llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

Show First 20 Lines • Show All 638 Lines • ▼ Show 20 Linesvoid PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCOperand &Op = MI->getOperand(OpNo); const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) { if (Op.isReg()) {
unsigned Reg = Op.getReg(); unsigned Reg = Op.getReg();
if (!ShowVSRNumsAsVR) if (!ShowVSRNumsAsVR)
Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()), Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
Reg, OpNo); Reg, OpNo);
const char *RegName; const char *RegName;
RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg)); RegName = getVerboseConditionRegName(Reg, MCRI.getEncodingValue(Reg));
if (RegName == nullptr) if (RegName == nullptr)
RegName = getRegisterName(Reg); RegName = getRegisterName(Reg);
if (showRegistersWithPercentPrefix(RegName)) if (showRegistersWithPercentPrefix(RegName))
O << "%"; O << "%";
if (!showRegistersWithPrefix()) if (!showRegistersWithPrefix())
RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
O << RegName; O << RegName;
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llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

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class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
/// Construct an PPC ELF object writer. /// Construct an PPC ELF object writer.
std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit, std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
uint8_t OSABI); uint8_t OSABI);
/// Construct a PPC Mach-O object writer. /// Construct a PPC Mach-O object writer.
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
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llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines if (!FullFS.empty())
FullFS = "+aix," + FullFS; FullFS = "+aix," + FullFS;
else else
FullFS = "+aix"; FullFS = "+aix";
} }
return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS); return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS);
} }
static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TheTriple, const Triple &TheTriple,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
TheTriple.getArch() == Triple::ppc64le); TheTriple.getArch() == Triple::ppc64le);
MCAsmInfo *MAI; MCAsmInfo *MAI;
if (TheTriple.isOSBinFormatXCOFF()) if (TheTriple.isOSBinFormatXCOFF())
MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple); MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple);
else else
MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple); MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
// Initial state of the frame pointer is R1. // Initial state of the frame pointer is R1.
unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
MCCFIInstruction Inst = MCCFIInstruction Inst =
MCCFIInstruction::cfiDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); MCCFIInstruction::cfiDefCfa(nullptr, MCRI.getDwarfRegNum(Reg, true), 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCStreamer * static MCStreamer *
createPPCELFStreamer(const Triple &T, MCContext &Context, createPPCELFStreamer(const Triple &T, MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB, std::unique_ptr<MCAsmBackend> &&MAB,
▲ Show 20 Lines • Show All 244 Lines • ▼ Show 20 Lines if (TT.isOSBinFormatXCOFF())
return new PPCTargetXCOFFStreamer(S); return new PPCTargetXCOFFStreamer(S);
return new PPCTargetMachOStreamer(S); return new PPCTargetMachOStreamer(S);
} }
static MCInstPrinter *createPPCMCInstPrinter(const Triple &T, static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new PPCInstPrinter(MAI, MII, MRI, T); return new PPCInstPrinter(MAI, MII, MCRI, T);
} }
namespace { namespace {
class PPCMCInstrAnalysis : public MCInstrAnalysis { class PPCMCInstrAnalysis : public MCInstrAnalysis {
public: public:
explicit PPCMCInstrAnalysis(const MCInstrInfo *Info) explicit PPCMCInstrAnalysis(const MCInstrInfo *Info)
: MCInstrAnalysis(Info) {} : MCInstrAnalysis(Info) {}
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llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

Show First 20 Lines • Show All 605 Lines • ▼ Show 20 Linesvoid PPCFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
const PPCTargetLowering &TLI = *Subtarget.getTargetLowering(); const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
DebugLoc dl; DebugLoc dl;
// AIX assembler does not support cfi directives. // AIX assembler does not support cfi directives.
const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI(); const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
const bool HasFastMFLR = Subtarget.hasFastMFLR(); const bool HasFastMFLR = Subtarget.hasFastMFLR();
// Get processor type. // Get processor type.
bool isPPC64 = Subtarget.isPPC64(); bool isPPC64 = Subtarget.isPPC64();
▲ Show 20 Lines • Show All 481 Lines • ▼ Show 20 Linesvoid PPCFrameLowering::emitPrologue(MachineFunction &MF,
// Add Call Frame Information for the instructions we generated above. // Add Call Frame Information for the instructions we generated above.
if (needsCFI) { if (needsCFI) {
unsigned CFIIndex; unsigned CFIIndex;
if (HasBP) { if (HasBP) {
// Define CFA in terms of BP. Do this in preference to using FP/SP, // Define CFA in terms of BP. Do this in preference to using FP/SP,
// because if the stack needed aligning then CFA won't be at a fixed // because if the stack needed aligning then CFA won't be at a fixed
// offset from FP/SP. // offset from FP/SP.
unsigned Reg = MRI->getDwarfRegNum(BPReg, true); unsigned Reg = MCRI->getDwarfRegNum(BPReg, true);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
} else { } else {
// Adjust the definition of CFA to account for the change in SP. // Adjust the definition of CFA to account for the change in SP.
assert(NegFrameSize); assert(NegFrameSize);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::cfiDefCfaOffset(nullptr, -NegFrameSize)); MCCFIInstruction::cfiDefCfaOffset(nullptr, -NegFrameSize));
} }
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
if (HasFP) { if (HasFP) {
// Describe where FP was saved, at a fixed offset from CFA. // Describe where FP was saved, at a fixed offset from CFA.
unsigned Reg = MRI->getDwarfRegNum(FPReg, true); unsigned Reg = MCRI->getDwarfRegNum(FPReg, true);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
if (FI->usesPICBase()) { if (FI->usesPICBase()) {
// Describe where FP was saved, at a fixed offset from CFA. // Describe where FP was saved, at a fixed offset from CFA.
unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); unsigned Reg = MCRI->getDwarfRegNum(PPC::R30, true);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
if (HasBP) { if (HasBP) {
// Describe where BP was saved, at a fixed offset from CFA. // Describe where BP was saved, at a fixed offset from CFA.
unsigned Reg = MRI->getDwarfRegNum(BPReg, true); unsigned Reg = MCRI->getDwarfRegNum(BPReg, true);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
if (MustSaveLR) { if (MustSaveLR) {
// Describe where LR was saved, at a fixed offset from CFA. // Describe where LR was saved, at a fixed offset from CFA.
unsigned Reg = MRI->getDwarfRegNum(LRReg, true); unsigned Reg = MCRI->getDwarfRegNum(LRReg, true);
CFIIndex = MF.addFrameInst( CFIIndex = MF.addFrameInst(
MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
// If there is a frame pointer, copy R1 into R31 // If there is a frame pointer, copy R1 into R31
if (HasFP) { if (HasFP) {
BuildMI(MBB, MBBI, dl, OrInst, FPReg) BuildMI(MBB, MBBI, dl, OrInst, FPReg)
.addReg(SPReg) .addReg(SPReg)
.addReg(SPReg); .addReg(SPReg);
if (!HasBP && needsCFI) { if (!HasBP && needsCFI) {
// Change the definition of CFA from SP+offset to FP+offset, because SP // Change the definition of CFA from SP+offset to FP+offset, because SP
// will change at every alloca. // will change at every alloca.
unsigned Reg = MRI->getDwarfRegNum(FPReg, true); unsigned Reg = MCRI->getDwarfRegNum(FPReg, true);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
Show All 22 Lines for (const CalleeSavedInfo &I : CSI) {
// For 64-bit SVR4 when we have spilled CRs, the spill location // For 64-bit SVR4 when we have spilled CRs, the spill location
// is SP+8, not a frame-relative slot. // is SP+8, not a frame-relative slot.
if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
// In the ELFv1 ABI, only CR2 is noted in CFI and stands in for // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
// the whole CR word. In the ELFv2 ABI, every CR that was // the whole CR word. In the ELFv2 ABI, every CR that was
// actually saved gets its own CFI record. // actually saved gets its own CFI record.
Register CRReg = isELFv2ABI? Reg : PPC::CR2; Register CRReg = isELFv2ABI? Reg : PPC::CR2;
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(CRReg, true), CRSaveOffset)); nullptr, MCRI->getDwarfRegNum(CRReg, true), CRSaveOffset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
continue; continue;
} }
if (I.isSpilledToReg()) { if (I.isSpilledToReg()) {
unsigned SpilledReg = I.getDstReg(); unsigned SpilledReg = I.getDstReg();
unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister(
nullptr, MRI->getDwarfRegNum(Reg, true), nullptr, MCRI->getDwarfRegNum(Reg, true),
MRI->getDwarfRegNum(SpilledReg, true))); MCRI->getDwarfRegNum(SpilledReg, true)));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIRegister); .addCFIIndex(CFIRegister);
} else { } else {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
// We have changed the object offset above but we do not want to change // We have changed the object offset above but we do not want to change
// the actual offsets in the CFI instruction so we have to undo the // the actual offsets in the CFI instruction so we have to undo the
// offset change here. // offset change here.
if (MovingStackUpdateDown) if (MovingStackUpdateDown)
Offset -= NegFrameSize; Offset -= NegFrameSize;
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); nullptr, MCRI->getDwarfRegNum(Reg, true), Offset));
BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
} }
} }
void PPCFrameLowering::inlineStackProbe(MachineFunction &MF, void PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
MachineBasicBlock &PrologMBB) const { MachineBasicBlock &PrologMBB) const {
bool isPPC64 = Subtarget.isPPC64(); bool isPPC64 = Subtarget.isPPC64();
const PPCTargetLowering &TLI = *Subtarget.getTargetLowering(); const PPCTargetLowering &TLI = *Subtarget.getTargetLowering();
const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
// AIX assembler does not support cfi directives. // AIX assembler does not support cfi directives.
const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI(); const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
auto StackAllocMIPos = llvm::find_if(PrologMBB, [](MachineInstr &MI) { auto StackAllocMIPos = llvm::find_if(PrologMBB, [](MachineInstr &MI) {
int Opc = MI.getOpcode(); int Opc = MI.getOpcode();
return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32; return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
}); });
if (StackAllocMIPos == PrologMBB.end()) if (StackAllocMIPos == PrologMBB.end())
return; return;
Show All 14 Linesvoid PPCFrameLowering::inlineStackProbe(MachineFunction &MF,
bool HasBP = RegInfo->hasBasePointer(MF); bool HasBP = RegInfo->hasBasePointer(MF);
Register BPReg = RegInfo->getBaseRegister(MF); Register BPReg = RegInfo->getBaseRegister(MF);
Align MaxAlign = MFI.getMaxAlign(); Align MaxAlign = MFI.getMaxAlign();
bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR); const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
// Subroutines to generate .cfi_* directives. // Subroutines to generate .cfi_* directives.
auto buildDefCFAReg = [&](MachineBasicBlock &MBB, auto buildDefCFAReg = [&](MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register Reg) { MachineBasicBlock::iterator MBBI, Register Reg) {
unsigned RegNum = MRI->getDwarfRegNum(Reg, true); unsigned RegNum = MCRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaRegister(nullptr, RegNum)); MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
}; };
auto buildDefCFA = [&](MachineBasicBlock &MBB, auto buildDefCFA = [&](MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register Reg, MachineBasicBlock::iterator MBBI, Register Reg,
int Offset) { int Offset) {
unsigned RegNum = MRI->getDwarfRegNum(Reg, true); unsigned RegNum = MCRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MBB.getParent()->addFrameInst( unsigned CFIIndex = MBB.getParent()->addFrameInst(
MCCFIInstruction::cfiDefCfa(nullptr, RegNum, Offset)); MCCFIInstruction::cfiDefCfa(nullptr, RegNum, Offset));
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
}; };
// Subroutine to determine if we can use the Imm as part of d-form. // Subroutine to determine if we can use the Imm as part of d-form.
auto CanUseDForm = [](int64_t Imm) { return isInt<16>(Imm) && Imm % 4 == 0; }; auto CanUseDForm = [](int64_t Imm) { return isInt<16>(Imm) && Imm % 4 == 0; };
// Subroutine to materialize the Imm into TempReg. // Subroutine to materialize the Imm into TempReg.
▲ Show 20 Lines • Show All 1,420 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

Show First 20 Lines • Show All 624 Lines • ▼ Show 20 Lines
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
RISCVAsmBackend::createObjectTargetWriter() const { RISCVAsmBackend::createObjectTargetWriter() const {
return createRISCVELFObjectWriter(OSABI, Is64Bit); return createRISCVELFObjectWriter(OSABI, Is64Bit);
} }
MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options); return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
} }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

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#include "MCTargetDesc/RISCVMCTargetDesc.h" #include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class RISCVInstPrinter : public MCInstPrinter { class RISCVInstPrinter : public MCInstPrinter {
public: public:
RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
bool applyTargetSpecificCLOption(StringRef Opt) override; bool applyTargetSpecificCLOption(StringRef Opt) override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
void printRegName(raw_ostream &O, MCRegister Reg) const override; void printRegName(raw_ostream &O, MCRegister Reg) const override;
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h

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class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI, std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
bool Is64Bit); bool Is64Bit);
} }
// Defines symbolic names for RISC-V registers. // Defines symbolic names for RISC-V registers.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
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llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
} }
static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitRISCVMCRegisterInfo(X, RISCV::X1); InitRISCVMCRegisterInfo(X, RISCV::X1);
return X; return X;
} }
static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); MCRegister SP = MCRI.getDwarfRegNum(RISCV::X2, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCObjectFileInfo * static MCObjectFileInfo *
createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
Show All 10 Linesstatic MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new RISCVInstPrinter(MAI, MII, MRI); return new RISCVInstPrinter(MAI, MII, MCRI);
} }
static MCTargetStreamer * static MCTargetStreamer *
createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
const Triple &TT = STI.getTargetTriple(); const Triple &TT = STI.getTargetTriple();
if (TT.isOSBinFormatELF()) if (TT.isOSBinFormatELF())
return new RISCVTargetELFStreamer(S, STI); return new RISCVTargetELFStreamer(S, STI);
return nullptr; return nullptr;
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llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVAsmBackend.cpp

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bool writeNopData(raw_ostream &OS, uint64_t Count,
return false; return false;
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T, MCAsmBackend *llvm::createSPIRVAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &) { const MCTargetOptions &) {
return new SPIRVAsmBackend(support::little); return new SPIRVAsmBackend(support::little);
} }

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.h

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class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
MCCodeEmitter *createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSPIRVMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createSPIRVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createSPIRVObjectTargetWriter(); std::unique_ptr<MCObjectTargetWriter> createSPIRVObjectTargetWriter();
} // namespace llvm } // namespace llvm
// Defines symbolic names for SPIR-V registers. This defines a mapping from // Defines symbolic names for SPIR-V registers. This defines a mapping from
// register name to register number. // register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
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llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCTargetDesc.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Linesstatic MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
MCInstPrinter *, bool) { MCInstPrinter *, bool) {
return new SPIRVTargetStreamer(S); return new SPIRVTargetStreamer(S);
} }
static MCInstPrinter *createSPIRVMCInstPrinter(const Triple &T, static MCInstPrinter *createSPIRVMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
assert(SyntaxVariant == 0); assert(SyntaxVariant == 0);
return new SPIRVInstPrinter(MAI, MII, MRI); return new SPIRVInstPrinter(MAI, MII, MCRI);
} }
namespace { namespace {
class SPIRVMCInstrAnalysis : public MCInstrAnalysis { class SPIRVMCInstrAnalysis : public MCInstrAnalysis {
public: public:
explicit SPIRVMCInstrAnalysis(const MCInstrInfo *Info) explicit SPIRVMCInstrAnalysis(const MCInstrInfo *Info)
: MCInstrAnalysis(Info) {} : MCInstrAnalysis(Info) {}
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llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

Show First 20 Lines • Show All 364 Lines • ▼ Show 20 Lines createObjectTargetWriter() const override {
return createSparcELFObjectWriter(Is64Bit, OSABI); return createSparcELFObjectWriter(Is64Bit, OSABI);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
} }

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h

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#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class SparcInstPrinter : public MCInstPrinter { class SparcInstPrinter : public MCInstPrinter {
public: public:
SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override; const MCSubtargetInfo &STI, raw_ostream &O) override;
bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &OS); raw_ostream &OS);
bool isV9(const MCSubtargetInfo &STI) const; bool isV9(const MCSubtargetInfo &STI) const;
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llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h

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class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createSparcELFObjectWriter(bool Is64Bit, std::unique_ptr<MCObjectTargetWriter> createSparcELFObjectWriter(bool Is64Bit,
uint8_t OSABI); uint8_t OSABI);
} // End llvm namespace } // End llvm namespace
// Defines symbolic names for Sparc registers. This defines a mapping from // Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
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llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp

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#include "SparcGenInstrInfo.inc" #include "SparcGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "SparcGenSubtargetInfo.inc" #include "SparcGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "SparcGenRegisterInfo.inc" #include "SparcGenRegisterInfo.inc"
static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); unsigned Reg = MCRI.getDwarfRegNum(SP::O6, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); unsigned Reg = MCRI.getDwarfRegNum(SP::O6, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstrInfo *createSparcMCInstrInfo() { static MCInstrInfo *createSparcMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitSparcMCInstrInfo(X); InitSparcMCInstrInfo(X);
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static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) { static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) {
return new SparcTargetStreamer(S); return new SparcTargetStreamer(S);
} }
static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new SparcInstPrinter(MAI, MII, MRI); return new SparcInstPrinter(MAI, MII, MCRI);
} }
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTargetMC() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(getTheSparcTarget(), createSparcMCAsmInfo); RegisterMCAsmInfoFn X(getTheSparcTarget(), createSparcMCAsmInfo);
RegisterMCAsmInfoFn Y(getTheSparcV9Target(), createSparcV9MCAsmInfo); RegisterMCAsmInfoFn Y(getTheSparcV9Target(), createSparcV9MCAsmInfo);
RegisterMCAsmInfoFn Z(getTheSparcelTarget(), createSparcMCAsmInfo); RegisterMCAsmInfoFn Z(getTheSparcelTarget(), createSparcMCAsmInfo);
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llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h

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namespace llvm { namespace llvm {
class MCOperand; class MCOperand;
class SystemZInstPrinter : public MCInstPrinter { class SystemZInstPrinter : public MCInstPrinter {
public: public:
SystemZInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, SystemZInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Automatically generated by tblgen. // Automatically generated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
// Print an address with the given base, displacement and index. // Print an address with the given base, displacement and index.
void printAddress(const MCAsmInfo *MAI, MCRegister Base, void printAddress(const MCAsmInfo *MAI, MCRegister Base,
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llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Linesbool SystemZMCAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
const MCSubtargetInfo *STI) const { const MCSubtargetInfo *STI) const {
for (uint64_t I = 0; I != Count; ++I) for (uint64_t I = 0; I != Count; ++I)
OS << '\x7'; OS << '\x7';
return true; return true;
} }
MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
uint8_t OSABI = uint8_t OSABI =
MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
return new SystemZMCAsmBackend(OSABI); return new SystemZMCAsmBackend(OSABI);
} }

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
} }
} // end namespace SystemZMC } // end namespace SystemZMC
MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSystemZMCAsmBackend(const Target &T, MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI);
} // end namespace llvm } // end namespace llvm
// Defines symbolic names for SystemZ registers. // Defines symbolic names for SystemZ registers.
// This defines a mapping from register name to register number. // This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
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llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Lines for (unsigned I = 0; I < 32; ++I) {
Map[VR64Regs[I]] = I; Map[VR64Regs[I]] = I;
Map[VR128Regs[I]] = I; Map[VR128Regs[I]] = I;
} }
} }
assert(Reg < SystemZ::NUM_TARGET_REGS); assert(Reg < SystemZ::NUM_TARGET_REGS);
return Map[Reg]; return Map[Reg];
} }
static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
if (TT.isOSzOS()) if (TT.isOSzOS())
return new SystemZMCAsmInfoGOFF(TT); return new SystemZMCAsmInfoGOFF(TT);
MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT); MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), nullptr, MCRI.getDwarfRegNum(SystemZ::R15D, true),
SystemZMC::ELFCFAOffsetFromInitialSP); SystemZMC::ELFCFAOffsetFromInitialSP);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstrInfo *createSystemZMCInstrInfo() { static MCInstrInfo *createSystemZMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitSystemZMCInstrInfo(X); InitSystemZMCInstrInfo(X);
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createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new SystemZInstPrinter(MAI, MII, MRI); return new SystemZInstPrinter(MAI, MII, MCRI);
} }
void SystemZTargetStreamer::emitConstantPools() { void SystemZTargetStreamer::emitConstantPools() {
// Emit EXRL target instructions. // Emit EXRL target instructions.
if (EXRLTargets2Sym.empty()) if (EXRLTargets2Sym.empty())
return; return;
// Switch to the .text section. // Switch to the .text section.
const MCObjectFileInfo &OFI = *Streamer.getContext().getObjectFileInfo(); const MCObjectFileInfo &OFI = *Streamer.getContext().getObjectFileInfo();
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp

Show First 20 Lines • Show All 831 Lines • ▼ Show 20 Lines if (Base)
printFormattedRegName(MAI, Base, OS); printFormattedRegName(MAI, Base, OS);
OS << ')'; OS << ')';
} }
} }
bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
const char *ExtraCode, const char *ExtraCode,
raw_ostream &OS) { raw_ostream &OS) {
const MCRegisterInfo &MRI = *TM.getMCRegisterInfo(); const MCRegisterInfo &MCRI = *TM.getMCRegisterInfo();
const MachineOperand &MO = MI->getOperand(OpNo); const MachineOperand &MO = MI->getOperand(OpNo);
MCOperand MCOp; MCOperand MCOp;
if (ExtraCode) { if (ExtraCode) {
if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() && if (ExtraCode[0] == 'N' && !ExtraCode[1] && MO.isReg() &&
SystemZ::GR128BitRegClass.contains(MO.getReg())) SystemZ::GR128BitRegClass.contains(MO.getReg()))
MCOp = MCOp = MCOperand::createReg(
MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); MCRI.getSubReg(MO.getReg(), SystemZ::subreg_l64));
else else
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
} else { } else {
SystemZMCInstLower Lower(MF->getContext(), *this); SystemZMCInstLower Lower(MF->getContext(), *this);
MCOp = Lower.lowerOperand(MO); MCOp = Lower.lowerOperand(MO);
} }
printOperand(MCOp, MAI, OS); printOperand(MCOp, MAI, OS);
return false; return false;
▲ Show 20 Lines • Show All 307 Lines • Show Last 20 Lines

llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

Show First 20 Lines • Show All 521 Lines • ▼ Show 20 Lines
// Add CFI for the new frame location. // Add CFI for the new frame location.
static void buildDefCFAReg(MachineBasicBlock &MBB, static void buildDefCFAReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, unsigned Reg, const DebugLoc &DL, unsigned Reg,
const SystemZInstrInfo *ZII) { const SystemZInstrInfo *ZII) {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
unsigned RegNum = MRI->getDwarfRegNum(Reg, true); unsigned RegNum = MCRI->getDwarfRegNum(Reg, true);
unsigned CFIIndex = MF.addFrameInst( unsigned CFIIndex = MF.addFrameInst(
MCCFIInstruction::createDefCfaRegister(nullptr, RegNum)); MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));
BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
void SystemZELFFrameLowering::emitPrologue(MachineFunction &MF, void SystemZELFFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
const SystemZSubtarget &STI = MF.getSubtarget<SystemZSubtarget>(); const SystemZSubtarget &STI = MF.getSubtarget<SystemZSubtarget>();
const SystemZTargetLowering &TLI = *STI.getTargetLowering(); const SystemZTargetLowering &TLI = *STI.getTargetLowering();
MachineFrameInfo &MFFrame = MF.getFrameInfo(); MachineFrameInfo &MFFrame = MF.getFrameInfo();
auto *ZII = static_cast<const SystemZInstrInfo *>(STI.getInstrInfo()); auto *ZII = static_cast<const SystemZInstrInfo *>(STI.getInstrInfo());
SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>(); SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo(); const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
bool HasFP = hasFP(MF); bool HasFP = hasFP(MF);
// In GHC calling convention C stack space, including the ABI-defined // In GHC calling convention C stack space, including the ABI-defined
// 160-byte base area, is (de)allocated by GHC itself. This stack space may // 160-byte base area, is (de)allocated by GHC itself. This stack space may
// be used by LLVM as spill slots for the tail recursive GHC functions. Thus // be used by LLVM as spill slots for the tail recursive GHC functions. Thus
// do not allocate stack space here, too. // do not allocate stack space here, too.
if (MF.getFunction().getCallingConv() == CallingConv::GHC) { if (MF.getFunction().getCallingConv() == CallingConv::GHC) {
Show All 25 Lines if (ZFI->getSpillGPRRegs().LowGPR) {
// Add CFI for the GPR saves. // Add CFI for the GPR saves.
for (auto &Save : CSI) { for (auto &Save : CSI) {
Register Reg = Save.getReg(); Register Reg = Save.getReg();
if (SystemZ::GR64BitRegClass.contains(Reg)) { if (SystemZ::GR64BitRegClass.contains(Reg)) {
int FI = Save.getFrameIdx(); int FI = Save.getFrameIdx();
int64_t Offset = MFFrame.getObjectOffset(FI); int64_t Offset = MFFrame.getObjectOffset(FI);
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); nullptr, MCRI->getDwarfRegNum(Reg, true), Offset));
BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex); .addCFIIndex(CFIIndex);
} }
} }
} }
uint64_t StackSize = MFFrame.getStackSize(); uint64_t StackSize = MFFrame.getStackSize();
// We need to allocate the ABI-defined 160-byte base area whenever // We need to allocate the ABI-defined 160-byte base area whenever
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines if (SystemZ::FP64BitRegClass.contains(Reg)) {
MBBI->getOpcode() == SystemZ::VST) MBBI->getOpcode() == SystemZ::VST)
++MBBI; ++MBBI;
else else
llvm_unreachable("Couldn't skip over VR save"); llvm_unreachable("Couldn't skip over VR save");
} else } else
continue; continue;
// Add CFI for the this save. // Add CFI for the this save.
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true);
Register IgnoredFrameReg; Register IgnoredFrameReg;
int64_t Offset = int64_t Offset =
getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg) getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg)
.getFixed(); .getFixed();
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
nullptr, DwarfReg, SPOffsetFromCFA + Offset)); nullptr, DwarfReg, SPOffsetFromCFA + Offset));
CFIIndexes.push_back(CFIIndex); CFIIndexes.push_back(CFIIndex);
▲ Show 20 Lines • Show All 720 Lines • Show Last 20 Lines

llvm/lib/Target/TargetMachine.cpp

Show All 27 Lines
// TargetMachine Class // TargetMachine Class
// //
TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString,
const Triple &TT, StringRef CPU, StringRef FS, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options) const TargetOptions &Options)
: TheTarget(T), DL(DataLayoutString), TargetTriple(TT), : TheTarget(T), DL(DataLayoutString), TargetTriple(TT),
TargetCPU(std::string(CPU)), TargetFS(std::string(FS)), AsmInfo(nullptr), TargetCPU(std::string(CPU)), TargetFS(std::string(FS)), AsmInfo(nullptr),
MRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false), MCRI(nullptr), MII(nullptr), STI(nullptr), RequireStructuredCFG(false),
O0WantsFastISel(false), DefaultOptions(Options), Options(Options) {} O0WantsFastISel(false), DefaultOptions(Options), Options(Options) {}
TargetMachine::~TargetMachine() = default; TargetMachine::~TargetMachine() = default;
bool TargetMachine::isPositionIndependent() const { bool TargetMachine::isPositionIndependent() const {
return getRelocationModel() == Reloc::PIC_; return getRelocationModel() == Reloc::PIC_;
} }
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llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines createObjectTargetWriter() const override {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
return createVEELFObjectWriter(OSABI); return createVEELFObjectWriter(OSABI);
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createVEAsmBackend(const Target &T, MCAsmBackend *llvm::createVEAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new ELFVEAsmBackend(T, STI.getTargetTriple().getOS()); return new ELFVEAsmBackend(T, STI.getTargetTriple().getOS());
} }

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h

Show All 15 Lines
#include "VEMCTargetDesc.h" #include "VEMCTargetDesc.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class VEInstPrinter : public MCInstPrinter { class VEInstPrinter : public MCInstPrinter {
public: public:
VEInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, VEInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override; const MCSubtargetInfo &STI, raw_ostream &OS) override;
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
bool printAliasInstr(const MCInst *, uint64_t Address, bool printAliasInstr(const MCInst *, uint64_t Address,
Show All 30 Lines

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

Show All 25 Lines
#define GET_INSTRUCTION_NAME #define GET_INSTRUCTION_NAME
#define PRINT_ALIAS_INSTR #define PRINT_ALIAS_INSTR
#include "VEGenAsmWriter.inc" #include "VEGenAsmWriter.inc"
void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
// Generic registers have identical register name among register classes. // Generic registers have identical register name among register classes.
unsigned AltIdx = VE::AsmName; unsigned AltIdx = VE::AsmName;
// Misc registers have each own name, so no use alt-names. // Misc registers have each own name, so no use alt-names.
if (MRI.getRegClass(VE::MISCRegClassID).contains(Reg)) if (MCRI.getRegClass(VE::MISCRegClassID).contains(Reg))
AltIdx = VE::NoRegAltName; AltIdx = VE::NoRegAltName;
OS << '%' << getRegisterName(Reg, AltIdx); OS << '%' << getRegisterName(Reg, AltIdx);
} }
void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address, void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address,
StringRef Annot, const MCSubtargetInfo &STI, StringRef Annot, const MCSubtargetInfo &STI,
raw_ostream &OS) { raw_ostream &OS) {
if (!printAliasInstr(MI, Address, STI, OS)) if (!printAliasInstr(MI, Address, STI, OS))
▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h

Show All 24 Lines
class MCObjectTargetWriter; class MCObjectTargetWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
MCCodeEmitter *createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCCodeEmitter *createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx);
MCAsmBackend *createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI, MCAsmBackend *createVEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> createVEELFObjectWriter(uint8_t OSABI); std::unique_ptr<MCObjectTargetWriter> createVEELFObjectWriter(uint8_t OSABI);
} // namespace llvm } // namespace llvm
// Defines symbolic names for VE registers. This defines a mapping from // Defines symbolic names for VE registers. This defines a mapping from
// register name to register number. // register name to register number.
// //
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
Show All 12 Lines

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp

Show All 27 Lines
#include "VEGenInstrInfo.inc" #include "VEGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "VEGenSubtargetInfo.inc" #include "VEGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "VEGenRegisterInfo.inc" #include "VEGenRegisterInfo.inc"
static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, static MCAsmInfo *createVEMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new VEELFMCAsmInfo(TT); MCAsmInfo *MAI = new VEELFMCAsmInfo(TT);
unsigned Reg = MRI.getDwarfRegNum(VE::SX11, true); unsigned Reg = MCRI.getDwarfRegNum(VE::SX11, true);
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstrInfo *createVEMCInstrInfo() { static MCInstrInfo *createVEMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitVEMCInstrInfo(X); InitVEMCInstrInfo(X);
Show All 24 Linesstatic MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
bool isVerboseAsm) { bool isVerboseAsm) {
return new VETargetAsmStreamer(S, OS); return new VETargetAsmStreamer(S, OS);
} }
static MCInstPrinter *createVEMCInstPrinter(const Triple &T, static MCInstPrinter *createVEMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new VEInstPrinter(MAI, MII, MRI); return new VEInstPrinter(MAI, MII, MCRI);
} }
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETargetMC() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETargetMC() {
// Register the MC asm info. // Register the MC asm info.
RegisterMCAsmInfoFn X(getTheVETarget(), createVEMCAsmInfo); RegisterMCAsmInfoFn X(getTheVETarget(), createVEMCAsmInfo);
for (Target *T : {&getTheVETarget()}) { for (Target *T : {&getTheVETarget()}) {
// Register the MC instruction info. // Register the MC instruction info.
Show All 25 Lines

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h

Show All 27 Linesclass WebAssemblyInstPrinter final : public MCInstPrinter {
SmallVector<std::pair<uint64_t, bool>, 4> ControlFlowStack; SmallVector<std::pair<uint64_t, bool>, 4> ControlFlowStack;
SmallVector<uint64_t, 4> TryStack; SmallVector<uint64_t, 4> TryStack;
enum EHInstKind { TRY, CATCH, CATCH_ALL }; enum EHInstKind { TRY, CATCH, CATCH_ALL };
SmallVector<EHInstKind, 4> EHInstStack; SmallVector<EHInstKind, 4> EHInstStack;
public: public:
WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI); const MCRegisterInfo &MCRI);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override; const MCSubtargetInfo &STI, raw_ostream &OS) override;
// Used by tblegen code. // Used by tblegen code.
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
bool IsVariadicDef = false); bool IsVariadicDef = false);
Show All 15 Lines

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp

Show All 29 Lines
using namespace llvm; using namespace llvm;
#define DEBUG_TYPE "asm-printer" #define DEBUG_TYPE "asm-printer"
#include "WebAssemblyGenAsmWriter.inc" #include "WebAssemblyGenAsmWriter.inc"
WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, void WebAssemblyInstPrinter::printRegName(raw_ostream &OS,
MCRegister Reg) const { MCRegister Reg) const {
assert(Reg.id() != WebAssemblyFunctionInfo::UnusedReg); assert(Reg.id() != WebAssemblyFunctionInfo::UnusedReg);
// Note that there's an implicit local.get/local.set here! // Note that there's an implicit local.get/local.set here!
OS << "$" << Reg.id(); OS << "$" << Reg.id();
} }
▲ Show 20 Lines • Show All 321 Lines • Show Last 20 Lines

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

Show All 29 Lines
#include "WebAssemblyGenInstrInfo.inc" #include "WebAssemblyGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "WebAssemblyGenSubtargetInfo.inc" #include "WebAssemblyGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "WebAssemblyGenRegisterInfo.inc" #include "WebAssemblyGenRegisterInfo.inc"
static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MRI*/, static MCAsmInfo *createMCAsmInfo(const MCRegisterInfo & /*MCRI*/,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new WebAssemblyMCAsmInfo(TT, Options); return new WebAssemblyMCAsmInfo(TT, Options);
} }
static MCInstrInfo *createMCInstrInfo() { static MCInstrInfo *createMCInstrInfo() {
auto *X = new MCInstrInfo(); auto *X = new MCInstrInfo();
InitWebAssemblyMCInstrInfo(X); InitWebAssemblyMCInstrInfo(X);
return X; return X;
} }
static MCRegisterInfo *createMCRegisterInfo(const Triple & /*T*/) { static MCRegisterInfo *createMCRegisterInfo(const Triple & /*T*/) {
auto *X = new MCRegisterInfo(); auto *X = new MCRegisterInfo();
InitWebAssemblyMCRegisterInfo(X, 0); InitWebAssemblyMCRegisterInfo(X, 0);
return X; return X;
} }
static MCInstPrinter *createMCInstPrinter(const Triple & /*T*/, static MCInstPrinter *createMCInstPrinter(const Triple & /*T*/,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
assert(SyntaxVariant == 0 && "WebAssembly only has one syntax variant"); assert(SyntaxVariant == 0 && "WebAssembly only has one syntax variant");
return new WebAssemblyInstPrinter(MAI, MII, MRI); return new WebAssemblyInstPrinter(MAI, MII, MCRI);
} }
static MCCodeEmitter *createCodeEmitter(const MCInstrInfo &MCII, static MCCodeEmitter *createCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx) { MCContext &Ctx) {
return createWebAssemblyMCCodeEmitter(MCII); return createWebAssemblyMCCodeEmitter(MCII);
} }
static MCAsmBackend *createAsmBackend(const Target & /*T*/, static MCAsmBackend *createAsmBackend(const Target & /*T*/,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo & /*MRI*/, const MCRegisterInfo & /*MCRI*/,
const MCTargetOptions & /*Options*/) { const MCTargetOptions & /*Options*/) {
return createWebAssemblyAsmBackend(STI.getTargetTriple()); return createWebAssemblyAsmBackend(STI.getTargetTriple());
} }
static MCSubtargetInfo *createMCSubtargetInfo(const Triple &TT, StringRef CPU, static MCSubtargetInfo *createMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS) { StringRef FS) {
return createWebAssemblyMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createWebAssemblyMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Show First 20 Lines • Show All 3,626 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
} }
if (Flags) if (Flags)
Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc)); Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
return false; return false;
} }
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: return false; default: return false;
case X86::JMP_1: case X86::JMP_1:
// {disp32} forces a larger displacement as if the instruction was relaxed. // {disp32} forces a larger displacement as if the instruction was relaxed.
// NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}. // NOTE: 16-bit mode uses 16-bit displacement even though it says {disp32}.
// This matches GNU assembler. // This matches GNU assembler.
if (ForcedDispEncoding == DispEncoding_Disp32) { if (ForcedDispEncoding == DispEncoding_Disp32) {
Show All 23 Linesbool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
case X86::VMOVDQUYrr: case X86::VMOVDQUYrr:
case X86::VMOVUPDrr: case X86::VMOVUPDrr:
case X86::VMOVUPDYrr: case X86::VMOVUPDYrr:
case X86::VMOVUPSrr: case X86::VMOVUPSrr:
case X86::VMOVUPSYrr: { case X86::VMOVUPSYrr: {
// We can get a smaller encoding by using VEX.R instead of VEX.B if one of // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
// the registers is extended, but other isn't. // the registers is extended, but other isn't.
if (ForcedVEXEncoding == VEXEncoding_VEX3 || if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || MCRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8) MCRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8)
return false; return false;
unsigned NewOpc; unsigned NewOpc;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: llvm_unreachable("Invalid opcode"); default: llvm_unreachable("Invalid opcode");
case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
Show All 11 Lines case X86::VMOVUPSYrr: {
Inst.setOpcode(NewOpc); Inst.setOpcode(NewOpc);
return true; return true;
} }
case X86::VMOVSDrr: case X86::VMOVSDrr:
case X86::VMOVSSrr: { case X86::VMOVSSrr: {
// We can get a smaller encoding by using VEX.R instead of VEX.B if one of // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
// the registers is extended, but other isn't. // the registers is extended, but other isn't.
if (ForcedVEXEncoding == VEXEncoding_VEX3 || if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 || MCRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8) MCRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8)
return false; return false;
unsigned NewOpc; unsigned NewOpc;
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: llvm_unreachable("Invalid opcode"); default: llvm_unreachable("Invalid opcode");
case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
} }
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines case X86::INT: {
Inst = TmpInst; Inst = TmpInst;
return true; return true;
} }
} }
} }
bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
using namespace X86; using namespace X86;
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
unsigned Opcode = Inst.getOpcode(); unsigned Opcode = Inst.getOpcode();
uint64_t TSFlags = MII.get(Opcode).TSFlags; uint64_t TSFlags = MII.get(Opcode).TSFlags;
if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) || if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) ||
isVFMADDCSH(Opcode)) { isVFMADDCSH(Opcode)) {
unsigned Dest = Inst.getOperand(0).getReg(); unsigned Dest = Inst.getOperand(0).getReg();
for (unsigned i = 2; i < Inst.getNumOperands(); i++) for (unsigned i = 2; i < Inst.getNumOperands(); i++)
if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
return Warning(Ops[0]->getStartLoc(), "Destination register should be " return Warning(Ops[0]->getStartLoc(), "Destination register should be "
Show All 11 Lines for (unsigned i = TSFlags & X86II::EVEX_K ? 2 : 1;
if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
return Warning(Ops[0]->getStartLoc(), "Destination register should be " return Warning(Ops[0]->getStartLoc(), "Destination register should be "
"distinct from source registers"); "distinct from source registers");
} else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) || } else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) ||
isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) || isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) ||
isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) { isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) {
unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
X86::AddrNumOperands - 1).getReg(); X86::AddrNumOperands - 1).getReg();
unsigned Src2Enc = MRI->getEncodingValue(Src2); unsigned Src2Enc = MCRI->getEncodingValue(Src2);
if (Src2Enc % 4 != 0) { if (Src2Enc % 4 != 0) {
StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2); StringRef RegName = X86IntelInstPrinter::getRegisterName(Src2);
unsigned GroupStart = (Src2Enc / 4) * 4; unsigned GroupStart = (Src2Enc / 4) * 4;
unsigned GroupEnd = GroupStart + 3; unsigned GroupEnd = GroupStart + 3;
return Warning(Ops[0]->getStartLoc(), return Warning(Ops[0]->getStartLoc(),
"source register '" + RegName + "' implicitly denotes '" + "source register '" + RegName + "' implicitly denotes '" +
RegName.take_front(3) + Twine(GroupStart) + "' to '" + RegName.take_front(3) + Twine(GroupStart) + "' to '" +
RegName.take_front(3) + Twine(GroupEnd) + RegName.take_front(3) + Twine(GroupEnd) +
"' source group"); "' source group");
} }
} else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) || } else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) ||
isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) || isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) ||
isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) || isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) ||
isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) { isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) {
bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
if (HasEVEX) { if (HasEVEX) {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); unsigned Dest = MCRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Index = MRI->getEncodingValue( unsigned Index = MCRI->getEncodingValue(
Inst.getOperand(4 + X86::AddrIndexReg).getReg()); Inst.getOperand(4 + X86::AddrIndexReg).getReg());
if (Dest == Index) if (Dest == Index)
return Warning(Ops[0]->getStartLoc(), "index and destination registers " return Warning(Ops[0]->getStartLoc(), "index and destination registers "
"should be distinct"); "should be distinct");
} else { } else {
unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); unsigned Dest = MCRI->getEncodingValue(Inst.getOperand(0).getReg());
unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); unsigned Mask = MCRI->getEncodingValue(Inst.getOperand(1).getReg());
unsigned Index = MRI->getEncodingValue( unsigned Index = MCRI->getEncodingValue(
Inst.getOperand(3 + X86::AddrIndexReg).getReg()); Inst.getOperand(3 + X86::AddrIndexReg).getReg());
if (Dest == Mask || Dest == Index || Mask == Index) if (Dest == Mask || Dest == Index || Mask == Index)
return Warning(Ops[0]->getStartLoc(), "mask, index, and destination " return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
"registers should be distinct"); "registers should be distinct");
} }
} }
// Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to
▲ Show 20 Lines • Show All 939 Lines • ▼ Show 20 Linesbool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
if (Parser.parseEOL()) if (Parser.parseEOL())
return true; return true;
return getTargetStreamer().emitFPOEndProc(L); return getTargetStreamer().emitFPOEndProc(L);
} }
bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID,
MCRegister &RegNo) { MCRegister &RegNo) {
SMLoc startLoc = getLexer().getLoc(); SMLoc startLoc = getLexer().getLoc();
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = getContext().getRegisterInfo();
// Try parsing the argument as a register first. // Try parsing the argument as a register first.
if (getLexer().getTok().isNot(AsmToken::Integer)) { if (getLexer().getTok().isNot(AsmToken::Integer)) {
SMLoc endLoc; SMLoc endLoc;
if (parseRegister(RegNo, startLoc, endLoc)) if (parseRegister(RegNo, startLoc, endLoc))
return true; return true;
if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) { if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) {
return Error(startLoc, return Error(startLoc,
"register is not supported for use with this directive"); "register is not supported for use with this directive");
} }
} else { } else {
// Otherwise, an integer number matching the encoding of the desired // Otherwise, an integer number matching the encoding of the desired
// register may appear. // register may appear.
int64_t EncodedReg; int64_t EncodedReg;
if (getParser().parseAbsoluteExpression(EncodedReg)) if (getParser().parseAbsoluteExpression(EncodedReg))
return true; return true;
// The SEH register number is the same as the encoding register number. Map // The SEH register number is the same as the encoding register number. Map
// from the encoding back to the LLVM register number. // from the encoding back to the LLVM register number.
RegNo = 0; RegNo = 0;
for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) { for (MCPhysReg Reg : X86MCRegisterClasses[RegClassID]) {
if (MRI->getEncodingValue(Reg) == EncodedReg) { if (MCRI->getEncodingValue(Reg) == EncodedReg) {
RegNo = Reg; RegNo = Reg;
break; break;
} }
} }
if (RegNo == 0) { if (RegNo == 0) {
return Error(startLoc, return Error(startLoc,
"incorrect register number for use with this directive"); "incorrect register number for use with this directive");
} }
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h

Show All 14 Lines
#include "X86InstPrinterCommon.h" #include "X86InstPrinterCommon.h"
namespace llvm { namespace llvm {
class X86ATTInstPrinter final : public X86InstPrinterCommon { class X86ATTInstPrinter final : public X86InstPrinterCommon {
public: public:
X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {} : X86InstPrinterCommon(MAI, MII, MCRI), HasCustomInstComment(false) {}
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override; const MCSubtargetInfo &STI, raw_ostream &OS) override;
bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
// Autogenerated by tblgen, returns true if we successfully printed an // Autogenerated by tblgen, returns true if we successfully printed an
// alias. // alias.
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Show First 20 Lines • Show All 1,180 Lines • ▼ Show 20 Lines enum CompactUnwindEncodings {
/// Mask for encoding the frameless registers. /// Mask for encoding the frameless registers.
UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
}; };
} // namespace CU } // namespace CU
class DarwinX86AsmBackend : public X86AsmBackend { class DarwinX86AsmBackend : public X86AsmBackend {
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
/// Number of registers that can be saved in a compact unwind encoding. /// Number of registers that can be saved in a compact unwind encoding.
enum { CU_NUM_SAVED_REGS = 6 }; enum { CU_NUM_SAVED_REGS = 6 };
mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
Triple TT; Triple TT;
bool Is64Bit; bool Is64Bit;
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
} }
assert((permutationEncoding & 0x3FF) == permutationEncoding && assert((permutationEncoding & 0x3FF) == permutationEncoding &&
"Invalid compact register encoding!"); "Invalid compact register encoding!");
return permutationEncoding; return permutationEncoding;
} }
public: public:
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MCRI,
const MCSubtargetInfo &STI) const MCSubtargetInfo &STI)
: X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()), : X86AsmBackend(T, STI), MCRI(MCRI), TT(STI.getTargetTriple()),
Is64Bit(TT.isArch64Bit()) { Is64Bit(TT.isArch64Bit()) {
memset(SavedRegs, 0, sizeof(SavedRegs)); memset(SavedRegs, 0, sizeof(SavedRegs));
OffsetSize = Is64Bit ? 8 : 4; OffsetSize = Is64Bit ? 8 : 4;
MoveInstrSize = Is64Bit ? 3 : 2; MoveInstrSize = Is64Bit ? 3 : 2;
StackDivide = Is64Bit ? 8 : 4; StackDivide = Is64Bit ? 8 : 4;
} }
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
Show All 36 Lines for (const MCCFIInstruction &Inst : Instrs) {
// movq %rsp, %rbp // movq %rsp, %rbp
// L0: // L0:
// .cfi_def_cfa_register %rbp // .cfi_def_cfa_register %rbp
// //
HasFP = true; HasFP = true;
// If the frame pointer is other than esp/rsp, we do not have a way to // If the frame pointer is other than esp/rsp, we do not have a way to
// generate a compact unwinding representation, so bail out. // generate a compact unwinding representation, so bail out.
if (*MRI.getLLVMRegNum(Inst.getRegister(), true) != if (*MCRI.getLLVMRegNum(Inst.getRegister(), true) !=
(Is64Bit ? X86::RBP : X86::EBP)) (Is64Bit ? X86::RBP : X86::EBP))
return CU::UNWIND_MODE_DWARF; return CU::UNWIND_MODE_DWARF;
// Reset the counts. // Reset the counts.
memset(SavedRegs, 0, sizeof(SavedRegs)); memset(SavedRegs, 0, sizeof(SavedRegs));
StackAdjust = 0; StackAdjust = 0;
SavedRegIdx = 0; SavedRegIdx = 0;
MinAbsOffset = std::numeric_limits<int>::max(); MinAbsOffset = std::numeric_limits<int>::max();
Show All 31 Lines for (const MCCFIInstruction &Inst : Instrs) {
// .cfi_offset %r14, -32 // .cfi_offset %r14, -32
// .cfi_offset %r15, -24 // .cfi_offset %r15, -24
// //
if (SavedRegIdx == CU_NUM_SAVED_REGS) if (SavedRegIdx == CU_NUM_SAVED_REGS)
// If there are too many saved registers, we cannot use a compact // If there are too many saved registers, we cannot use a compact
// unwind encoding. // unwind encoding.
return CU::UNWIND_MODE_DWARF; return CU::UNWIND_MODE_DWARF;
unsigned Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); unsigned Reg = *MCRI.getLLVMRegNum(Inst.getRegister(), true);
SavedRegs[SavedRegIdx++] = Reg; SavedRegs[SavedRegIdx++] = Reg;
StackAdjust += OffsetSize; StackAdjust += OffsetSize;
MinAbsOffset = std::min(MinAbsOffset, abs(Inst.getOffset())); MinAbsOffset = std::min(MinAbsOffset, abs(Inst.getOffset()));
InstrOffset += PushInstrSize(Reg); InstrOffset += PushInstrSize(Reg);
break; break;
} }
} }
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const override {
return CompactUnwindEncoding; return CompactUnwindEncoding;
} }
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
return new DarwinX86AsmBackend(T, MRI, STI); return new DarwinX86AsmBackend(T, MCRI, STI);
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
return new WindowsX86AsmBackend(T, false, STI); return new WindowsX86AsmBackend(T, false, STI);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
if (TheTriple.isOSIAMCU()) if (TheTriple.isOSIAMCU())
return new ELFX86_IAMCUAsmBackend(T, OSABI, STI); return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
return new ELFX86_32AsmBackend(T, OSABI, STI); return new ELFX86_32AsmBackend(T, OSABI, STI);
} }
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple(); const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
return new DarwinX86AsmBackend(T, MRI, STI); return new DarwinX86AsmBackend(T, MCRI, STI);
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF()) if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
return new WindowsX86AsmBackend(T, true, STI); return new WindowsX86AsmBackend(T, true, STI);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
if (TheTriple.isX32()) if (TheTriple.isX32())
return new ELFX86_X32AsmBackend(T, OSABI, STI); return new ELFX86_X32AsmBackend(T, OSABI, STI);
return new ELFX86_64AsmBackend(T, OSABI, STI); return new ELFX86_64AsmBackend(T, OSABI, STI);
} }

llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h

Show All 15 Lines
#include "X86InstPrinterCommon.h" #include "X86InstPrinterCommon.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
namespace llvm { namespace llvm {
class X86IntelInstPrinter final : public X86InstPrinterCommon { class X86IntelInstPrinter final : public X86InstPrinterCommon {
public: public:
X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: X86InstPrinterCommon(MAI, MII, MRI) {} : X86InstPrinterCommon(MAI, MII, MCRI) {}
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &OS) override; const MCSubtargetInfo &STI, raw_ostream &OS) override;
bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
// Autogenerated by tblgen, returns true if we successfully printed an // Autogenerated by tblgen, returns true if we successfully printed an
// alias. // alias.
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesnamespace N86 {
}; };
} }
namespace X86_MC { namespace X86_MC {
std::string ParseX86Triple(const Triple &TT); std::string ParseX86Triple(const Triple &TT);
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MCRI);
/// Returns true if this instruction has a LOCK prefix. /// Returns true if this instruction has a LOCK prefix.
bool hasLockPrefix(const MCInst &MI); bool hasLockPrefix(const MCInst &MI);
/// \param Op operand # of the memory operand. /// \param Op operand # of the memory operand.
/// ///
/// \returns true if the specified instruction has a 16-bit memory operand. /// \returns true if the specified instruction has a 16-bit memory operand.
bool is16BitMemOperand(const MCInst &MI, unsigned Op, bool is16BitMemOperand(const MCInst &MI, unsigned Op,
Show All 21 LinesMCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS); StringRef FS);
} }
MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, MCAsmBackend *createX86_32AsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createX86_64AsmBackend(const Target &T, MCAsmBackend *createX86_64AsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
/// Implements X86-only directives for assembly emission. /// Implements X86-only directives for assembly emission.
MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S, MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
formatted_raw_ostream &OS, formatted_raw_ostream &OS,
MCInstPrinter *InstPrinter, MCInstPrinter *InstPrinter,
bool IsVerboseAsm); bool IsVerboseAsm);
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines if (STI.hasFeature(X86::Is32Bit)) {
assert(!is64BitMemOperand(MI, MemoryOperand)); assert(!is64BitMemOperand(MI, MemoryOperand));
return is16BitMemOperand(MI, MemoryOperand, STI); return is16BitMemOperand(MI, MemoryOperand, STI);
} }
assert(STI.hasFeature(X86::Is16Bit)); assert(STI.hasFeature(X86::Is16Bit));
assert(!is64BitMemOperand(MI, MemoryOperand)); assert(!is64BitMemOperand(MI, MemoryOperand));
return !is16BitMemOperand(MI, MemoryOperand, STI); return !is16BitMemOperand(MI, MemoryOperand, STI);
} }
void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MCRI) {
// FIXME: TableGen these. // FIXME: TableGen these.
for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
unsigned SEH = MRI->getEncodingValue(Reg); unsigned SEH = MCRI->getEncodingValue(Reg);
MRI->mapLLVMRegToSEHReg(Reg, SEH); MCRI->mapLLVMRegToSEHReg(Reg, SEH);
} }
// Mapping from CodeView to MC register id. // Mapping from CodeView to MC register id.
static const struct { static const struct {
codeview::RegisterId CVReg; codeview::RegisterId CVReg;
MCPhysReg Reg; MCPhysReg Reg;
} RegMap[] = { } RegMap[] = {
{codeview::RegisterId::AL, X86::AL}, {codeview::RegisterId::AL, X86::AL},
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines MCPhysReg Reg;
{codeview::RegisterId::AMD64_XMM27, X86::XMM27}, {codeview::RegisterId::AMD64_XMM27, X86::XMM27},
{codeview::RegisterId::AMD64_XMM28, X86::XMM28}, {codeview::RegisterId::AMD64_XMM28, X86::XMM28},
{codeview::RegisterId::AMD64_XMM29, X86::XMM29}, {codeview::RegisterId::AMD64_XMM29, X86::XMM29},
{codeview::RegisterId::AMD64_XMM30, X86::XMM30}, {codeview::RegisterId::AMD64_XMM30, X86::XMM30},
{codeview::RegisterId::AMD64_XMM31, X86::XMM31}, {codeview::RegisterId::AMD64_XMM31, X86::XMM31},
}; };
for (const auto &I : RegMap) for (const auto &I : RegMap)
MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); MCRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
} }
MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) { StringRef CPU, StringRef FS) {
std::string ArchFS = X86_MC::ParseX86Triple(TT); std::string ArchFS = X86_MC::ParseX86Triple(TT);
assert(!ArchFS.empty() && "Failed to parse X86 triple"); assert(!ArchFS.empty() && "Failed to parse X86 triple");
if (!FS.empty()) if (!FS.empty())
ArchFS = (Twine(ArchFS) + "," + FS).str(); ArchFS = (Twine(ArchFS) + "," + FS).str();
Show All 17 Linesstatic MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
X86_MC::getDwarfRegFlavour(TT, true), RA); X86_MC::getDwarfRegFlavour(TT, true), RA);
X86_MC::initLLVMToSEHAndCVRegMapping(X); X86_MC::initLLVMToSEHAndCVRegMapping(X);
return X; return X;
} }
static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TheTriple, const Triple &TheTriple,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
bool is64Bit = TheTriple.getArch() == Triple::x86_64; bool is64Bit = TheTriple.getArch() == Triple::x86_64;
MCAsmInfo *MAI; MCAsmInfo *MAI;
if (TheTriple.isOSBinFormatMachO()) { if (TheTriple.isOSBinFormatMachO()) {
if (is64Bit) if (is64Bit)
MAI = new X86_64MCAsmInfoDarwin(TheTriple); MAI = new X86_64MCAsmInfoDarwin(TheTriple);
Show All 18 Linesstatic MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MCRI,
// Initialize initial frame state. // Initialize initial frame state.
// Calculate amount of bytes used for return address storing // Calculate amount of bytes used for return address storing
int stackGrowth = is64Bit ? -8 : -4; int stackGrowth = is64Bit ? -8 : -4;
// Initial state of the frame pointer is esp+stackGrowth. // Initial state of the frame pointer is esp+stackGrowth.
unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); nullptr, MCRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
// Add return address to move list // Add return address to move list
unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); nullptr, MCRI.getDwarfRegNum(InstPtr, true), stackGrowth);
MAI->addInitialFrameState(Inst2); MAI->addInitialFrameState(Inst2);
return MAI; return MAI;
} }
static MCInstPrinter *createX86MCInstPrinter(const Triple &T, static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
if (SyntaxVariant == 0) if (SyntaxVariant == 0)
return new X86ATTInstPrinter(MAI, MII, MRI); return new X86ATTInstPrinter(MAI, MII, MCRI);
if (SyntaxVariant == 1) if (SyntaxVariant == 1)
return new X86IntelInstPrinter(MAI, MII, MRI); return new X86IntelInstPrinter(MAI, MII, MCRI);
return nullptr; return nullptr;
} }
static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
MCContext &Ctx) { MCContext &Ctx) {
// Default to the stock relocation info. // Default to the stock relocation info.
return llvm::createMCRelocationInfo(TheTriple, Ctx); return llvm::createMCRelocationInfo(TheTriple, Ctx);
} }
namespace llvm { namespace llvm {
namespace X86_MC { namespace X86_MC {
class X86MCInstrAnalysis : public MCInstrAnalysis { class X86MCInstrAnalysis : public MCInstrAnalysis {
X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete; X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete; X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
virtual ~X86MCInstrAnalysis() = default; virtual ~X86MCInstrAnalysis() = default;
public: public:
X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {} X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
#define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#include "X86GenSubtargetInfo.inc" #include "X86GenSubtargetInfo.inc"
bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, bool clearsSuperRegisters(const MCRegisterInfo &MCRI, const MCInst &Inst,
APInt &Mask) const override; APInt &Mask) const override;
std::vector<std::pair<uint64_t, uint64_t>> std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
uint64_t GotSectionVA, uint64_t GotSectionVA,
const Triple &TargetTriple) const override; const Triple &TargetTriple) const override;
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const override; uint64_t &Target) const override;
std::optional<uint64_t> std::optional<uint64_t>
evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI,
uint64_t Addr, uint64_t Size) const override; uint64_t Addr, uint64_t Size) const override;
std::optional<uint64_t> std::optional<uint64_t>
getMemoryOperandRelocationOffset(const MCInst &Inst, getMemoryOperandRelocationOffset(const MCInst &Inst,
uint64_t Size) const override; uint64_t Size) const override;
}; };
#define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#include "X86GenSubtargetInfo.inc" #include "X86GenSubtargetInfo.inc"
bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MCRI,
const MCInst &Inst, const MCInst &Inst,
APInt &Mask) const { APInt &Mask) const {
const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
unsigned NumDefs = Desc.getNumDefs(); unsigned NumDefs = Desc.getNumDefs();
unsigned NumImplicitDefs = Desc.getNumImplicitDefs(); unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
"Unexpected number of bits in the mask!"); "Unexpected number of bits in the mask!");
bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); const MCRegisterClass &GR32RC = MCRI.getRegClass(X86::GR32RegClassID);
const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); const MCRegisterClass &VR128XRC = MCRI.getRegClass(X86::VR128XRegClassID);
const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); const MCRegisterClass &VR256XRC = MCRI.getRegClass(X86::VR256XRegClassID);
auto ClearsSuperReg = [=](unsigned RegID) { auto ClearsSuperReg = [=](unsigned RegID) {
// On X86-64, a general purpose integer register is viewed as a 64-bit // On X86-64, a general purpose integer register is viewed as a 64-bit
// register internal to the processor. // register internal to the processor.
// An update to the lower 32 bits of a 64 bit integer register is // An update to the lower 32 bits of a 64 bit integer register is
// architecturally defined to zero extend the upper 32 bits. // architecturally defined to zero extend the upper 32 bits.
if (GR32RC.contains(RegID)) if (GR32RC.contains(RegID))
return true; return true;
▲ Show 20 Lines • Show All 381 Lines • Show Last 20 Lines

llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Linesstruct FPOStateMachine {
SmallString<128> FrameFunc; SmallString<128> FrameFunc;
SmallVector<RegSaveOffset, 4> RegSaveOffsets; SmallVector<RegSaveOffset, 4> RegSaveOffsets;
void emitFrameDataRecord(MCStreamer &OS, MCSymbol *Label); void emitFrameDataRecord(MCStreamer &OS, MCSymbol *Label);
}; };
} // end namespace } // end namespace
static Printable printFPOReg(const MCRegisterInfo *MRI, unsigned LLVMReg) { static Printable printFPOReg(const MCRegisterInfo *MCRI, unsigned LLVMReg) {
return Printable([MRI, LLVMReg](raw_ostream &OS) { return Printable([MCRI, LLVMReg](raw_ostream &OS) {
switch (LLVMReg) { switch (LLVMReg) {
// MSVC only seems to emit symbolic register names for EIP, EBP, and ESP, // MSVC only seems to emit symbolic register names for EIP, EBP, and ESP,
// but the format seems to support more than that, so we emit them. // but the format seems to support more than that, so we emit them.
case X86::EAX: OS << "$eax"; break; case X86::EAX:
case X86::EBX: OS << "$ebx"; break; OS << "$eax";
case X86::ECX: OS << "$ecx"; break; break;
case X86::EDX: OS << "$edx"; break; case X86::EBX:
case X86::EDI: OS << "$edi"; break; OS << "$ebx";
case X86::ESI: OS << "$esi"; break; break;
case X86::ESP: OS << "$esp"; break; case X86::ECX:
case X86::EBP: OS << "$ebp"; break; OS << "$ecx";
case X86::EIP: OS << "$eip"; break; break;
case X86::EDX:
OS << "$edx";
break;
case X86::EDI:
OS << "$edi";
break;
case X86::ESI:
OS << "$esi";
break;
case X86::ESP:
OS << "$esp";
break;
case X86::EBP:
OS << "$ebp";
break;
case X86::EIP:
OS << "$eip";
break;
// Otherwise, get the codeview register number and print $N. // Otherwise, get the codeview register number and print $N.
default: default:
OS << '$' << MRI->getCodeViewRegNum(LLVMReg); OS << '$' << MCRI->getCodeViewRegNum(LLVMReg);
break; break;
} }
}); });
} }
void FPOStateMachine::emitFrameDataRecord(MCStreamer &OS, MCSymbol *Label) { void FPOStateMachine::emitFrameDataRecord(MCStreamer &OS, MCSymbol *Label) {
unsigned CurFlags = Flags; unsigned CurFlags = Flags;
if (Label == FPO->Begin) if (Label == FPO->Begin)
CurFlags |= FrameData::IsFunctionStart; CurFlags |= FrameData::IsFunctionStart;
// Compute the new FrameFunc string. // Compute the new FrameFunc string.
FrameFunc.clear(); FrameFunc.clear();
raw_svector_ostream FuncOS(FrameFunc); raw_svector_ostream FuncOS(FrameFunc);
const MCRegisterInfo *MRI = OS.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = OS.getContext().getRegisterInfo();
assert((StackAlign == 0 || FrameReg != 0) && assert((StackAlign == 0 || FrameReg != 0) &&
"cannot align stack without frame reg"); "cannot align stack without frame reg");
StringRef CFAVar = StackAlign == 0 ? "$T0" : "$T1"; StringRef CFAVar = StackAlign == 0 ? "$T0" : "$T1";
if (FrameReg) { if (FrameReg) {
// CFA is FrameReg + FrameRegOff. // CFA is FrameReg + FrameRegOff.
FuncOS << CFAVar << ' ' << printFPOReg(MRI, FrameReg) << ' ' << FrameRegOff FuncOS << CFAVar << ' ' << printFPOReg(MCRI, FrameReg) << ' ' << FrameRegOff
<< " + = "; << " + = ";
// Assign $T0, the VFRAME register, the value of ESP after it is aligned. // Assign $T0, the VFRAME register, the value of ESP after it is aligned.
// Starting from the CFA, we subtract the size of all pushed registers, and // Starting from the CFA, we subtract the size of all pushed registers, and
// align the result. While we don't store any CSRs in this area, $T0 is used // align the result. While we don't store any CSRs in this area, $T0 is used
// by S_DEFRANGE_FRAMEPOINTER_REL records to find local variables. // by S_DEFRANGE_FRAMEPOINTER_REL records to find local variables.
if (StackAlign) { if (StackAlign) {
FuncOS << "$T0 " << CFAVar << ' ' << StackOffsetBeforeAlign << " - " FuncOS << "$T0 " << CFAVar << ' ' << StackOffsetBeforeAlign << " - "
<< StackAlign << " @ = "; << StackAlign << " @ = ";
} }
} else { } else {
// The address of return address is ESP + CurOffset, but we use .raSearch to // The address of return address is ESP + CurOffset, but we use .raSearch to
// match MSVC. This seems to ask the debugger to subtract some combination // match MSVC. This seems to ask the debugger to subtract some combination
// of LocalSize and SavedRegSize from ESP and grovel around in that memory // of LocalSize and SavedRegSize from ESP and grovel around in that memory
// to find the address of a plausible return address. // to find the address of a plausible return address.
FuncOS << CFAVar << " .raSearch = "; FuncOS << CFAVar << " .raSearch = ";
} }
// Caller's $eip should be dereferenced CFA, and $esp should be CFA plus 4. // Caller's $eip should be dereferenced CFA, and $esp should be CFA plus 4.
FuncOS << "$eip " << CFAVar << " ^ = "; FuncOS << "$eip " << CFAVar << " ^ = ";
FuncOS << "$esp " << CFAVar << " 4 + = "; FuncOS << "$esp " << CFAVar << " 4 + = ";
// Each saved register is stored at an unchanging negative CFA offset. // Each saved register is stored at an unchanging negative CFA offset.
for (RegSaveOffset RO : RegSaveOffsets) for (RegSaveOffset RO : RegSaveOffsets)
FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset FuncOS << printFPOReg(MCRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset
<< " - ^ = "; << " - ^ = ";
// Add it to the CV string table. // Add it to the CV string table.
CodeViewContext &CVCtx = OS.getContext().getCVContext(); CodeViewContext &CVCtx = OS.getContext().getCVContext();
unsigned FrameFuncStrTabOff = CVCtx.addToStringTable(FuncOS.str()).second; unsigned FrameFuncStrTabOff = CVCtx.addToStringTable(FuncOS.str()).second;
// MSVC has only ever been observed to emit a MaxStackSize of zero. // MSVC has only ever been observed to emit a MaxStackSize of zero.
unsigned MaxStackSize = 0; unsigned MaxStackSize = 0;
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86FrameLowering.cpp

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
void X86FrameLowering::emitCalleeSavedFrameMovesFullCFA( void X86FrameLowering::emitCalleeSavedFrameMovesFullCFA(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const { MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
if (!hasFP(MF)) { if (!hasFP(MF)) {
emitCalleeSavedFrameMoves(MBB, MBBI, DebugLoc{}, true); emitCalleeSavedFrameMoves(MBB, MBBI, DebugLoc{}, true);
return; return;
} }
const MachineModuleInfo &MMI = MF.getMMI(); const MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
const Register FramePtr = TRI->getFrameRegister(MF); const Register FramePtr = TRI->getFrameRegister(MF);
const Register MachineFramePtr = const Register MachineFramePtr =
STI.isTarget64BitILP32() ? Register(getX86SubSuperRegister(FramePtr, 64)) STI.isTarget64BitILP32() ? Register(getX86SubSuperRegister(FramePtr, 64))
: FramePtr; : FramePtr;
unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true); unsigned DwarfReg = MCRI->getDwarfRegNum(MachineFramePtr, true);
// Offset = space for return address + size of the frame pointer itself. // Offset = space for return address + size of the frame pointer itself.
unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4); unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
BuildCFI(MBB, MBBI, DebugLoc{}, BuildCFI(MBB, MBBI, DebugLoc{},
MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset)); MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset));
emitCalleeSavedFrameMoves(MBB, MBBI, DebugLoc{}, true); emitCalleeSavedFrameMoves(MBB, MBBI, DebugLoc{}, true);
} }
void X86FrameLowering::emitCalleeSavedFrameMoves( void X86FrameLowering::emitCalleeSavedFrameMoves(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, bool IsPrologue) const { const DebugLoc &DL, bool IsPrologue) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
MachineModuleInfo &MMI = MF.getMMI(); MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI.getContext().getRegisterInfo();
// Add callee saved registers to move list. // Add callee saved registers to move list.
const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
// Calculate offsets. // Calculate offsets.
for (const CalleeSavedInfo &I : CSI) { for (const CalleeSavedInfo &I : CSI) {
int64_t Offset = MFI.getObjectOffset(I.getFrameIdx()); int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
Register Reg = I.getReg(); Register Reg = I.getReg();
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true); unsigned DwarfReg = MCRI->getDwarfRegNum(Reg, true);
if (IsPrologue) { if (IsPrologue) {
BuildCFI(MBB, MBBI, DL, BuildCFI(MBB, MBBI, DL,
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset)); MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
} else { } else {
BuildCFI(MBB, MBBI, DL, BuildCFI(MBB, MBBI, DL,
MCCFIInstruction::createRestore(nullptr, DwarfReg)); MCCFIInstruction::createRestore(nullptr, DwarfReg));
} }
▲ Show 20 Lines • Show All 3,387 Lines • Show Last 20 Lines

llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h

Show All 17 Lines
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class StringRef; class StringRef;
class XCoreInstPrinter : public MCInstPrinter { class XCoreInstPrinter : public MCInstPrinter {
public: public:
XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Autogenerated by tblgen. // Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
void printRegName(raw_ostream &OS, MCRegister Reg) const override; void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
Show All 11 Lines

llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesstatic MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
return X; return X;
} }
static MCSubtargetInfo * static MCSubtargetInfo *
createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createXCoreMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); return createXCoreMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
} }
static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); MCAsmInfo *MAI = new XCoreMCAsmInfo(TT);
// Initial state of the frame pointer is SP. // Initial state of the frame pointer is SP.
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, XCore::SP, 0); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, XCore::SP, 0);
MAI->addInitialFrameState(Inst); MAI->addInitialFrameState(Inst);
return MAI; return MAI;
} }
static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T, static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new XCoreInstPrinter(MAI, MII, MRI); return new XCoreInstPrinter(MAI, MII, MCRI);
} }
XCoreTargetStreamer::XCoreTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} XCoreTargetStreamer::XCoreTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
XCoreTargetStreamer::~XCoreTargetStreamer() = default; XCoreTargetStreamer::~XCoreTargetStreamer() = default;
namespace { namespace {
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/lib/Target/XCore/XCoreFrameLowering.cpp

Show First 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
} }
void XCoreFrameLowering::emitPrologue(MachineFunction &MF, void XCoreFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
MachineBasicBlock::iterator MBBI = MBB.begin(); MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
MachineModuleInfo *MMI = &MF.getMMI(); MachineModuleInfo *MMI = &MF.getMMI();
const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); const MCRegisterInfo *MCRI = MMI->getContext().getRegisterInfo();
const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo(); const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
// Debug location must be unknown since the first debug location is used // Debug location must be unknown since the first debug location is used
// to determine the end of the prologue. // to determine the end of the prologue.
DebugLoc dl; DebugLoc dl;
if (MFI.getMaxAlign() > getStackAlign()) if (MFI.getMaxAlign() > getStackAlign())
report_fatal_error("emitPrologue unsupported alignment: " + report_fatal_error("emitPrologue unsupported alignment: " +
Show All 24 Lines if (UseENTSP) {
int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
MBB.addLiveIn(XCore::LR); MBB.addLiveIn(XCore::LR);
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)); MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
MIB.addImm(Adjusted); MIB.addImm(Adjusted);
MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(), MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
true); true);
if (emitFrameMoves) { if (emitFrameMoves) {
EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); unsigned DRegNum = MCRI->getDwarfRegNum(XCore::LR, true);
EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0); EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0);
} }
} }
// If necessary, save LR and FP to the stack, as we EXTSP. // If necessary, save LR and FP to the stack, as we EXTSP.
SmallVector<StackSlotInfo,2> SpillList; SmallVector<StackSlotInfo,2> SpillList;
GetSpillList(SpillList, MFI, XFI, saveLR, FP); GetSpillList(SpillList, MFI, XFI, saveLR, FP);
// We want the nearest (negative) offsets first, so reverse list. // We want the nearest (negative) offsets first, so reverse list.
std::reverse(SpillList.begin(), SpillList.end()); std::reverse(SpillList.begin(), SpillList.end());
for (unsigned i = 0, e = SpillList.size(); i != e; ++i) { for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset"); assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset"); assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
int OffsetFromTop = - SpillList[i].Offset/4; int OffsetFromTop = - SpillList[i].Offset/4;
IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize, IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize,
emitFrameMoves); emitFrameMoves);
int Offset = Adjusted - OffsetFromTop; int Offset = Adjusted - OffsetFromTop;
int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
MBB.addLiveIn(SpillList[i].Reg); MBB.addLiveIn(SpillList[i].Reg);
BuildMI(MBB, MBBI, dl, TII.get(Opcode)) BuildMI(MBB, MBBI, dl, TII.get(Opcode))
.addReg(SpillList[i].Reg, RegState::Kill) .addReg(SpillList[i].Reg, RegState::Kill)
.addImm(Offset) .addImm(Offset)
.addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI, .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
MachineMemOperand::MOStore)); MachineMemOperand::MOStore));
if (emitFrameMoves) { if (emitFrameMoves) {
unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); unsigned DRegNum = MCRI->getDwarfRegNum(SpillList[i].Reg, true);
EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset); EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset);
} }
} }
// Complete any remaining Stack adjustment. // Complete any remaining Stack adjustment.
IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize, IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize,
emitFrameMoves); emitFrameMoves);
assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment"); assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
if (FP) { if (FP) {
// Set the FP from the SP. // Set the FP from the SP.
BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0); BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
if (emitFrameMoves) if (emitFrameMoves)
EmitDefCfaRegister(MBB, MBBI, dl, TII, MF, EmitDefCfaRegister(MBB, MBBI, dl, TII, MF,
MRI->getDwarfRegNum(FramePtr, true)); MCRI->getDwarfRegNum(FramePtr, true));
} }
if (emitFrameMoves) { if (emitFrameMoves) {
// Frame moves for callee saved. // Frame moves for callee saved.
for (const auto &SpillLabel : XFI->getSpillLabels()) { for (const auto &SpillLabel : XFI->getSpillLabels()) {
MachineBasicBlock::iterator Pos = SpillLabel.first; MachineBasicBlock::iterator Pos = SpillLabel.first;
++Pos; ++Pos;
const CalleeSavedInfo &CSI = SpillLabel.second; const CalleeSavedInfo &CSI = SpillLabel.second;
int Offset = MFI.getObjectOffset(CSI.getFrameIdx()); int Offset = MFI.getObjectOffset(CSI.getFrameIdx());
unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true); unsigned DRegNum = MCRI->getDwarfRegNum(CSI.getReg(), true);
EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset); EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset);
} }
if (XFI->hasEHSpillSlot()) { if (XFI->hasEHSpillSlot()) {
// The unwinder requires stack slot & CFI offsets for the exception info. // The unwinder requires stack slot & CFI offsets for the exception info.
// We do not save/spill these registers. // We do not save/spill these registers.
const Function *Fn = &MF.getFunction(); const Function *Fn = &MF.getFunction();
const Constant *PersonalityFn = const Constant *PersonalityFn =
Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr; Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr;
SmallVector<StackSlotInfo, 2> SpillList; SmallVector<StackSlotInfo, 2> SpillList;
GetEHSpillList(SpillList, MFI, XFI, PersonalityFn, GetEHSpillList(SpillList, MFI, XFI, PersonalityFn,
MF.getSubtarget().getTargetLowering()); MF.getSubtarget().getTargetLowering());
assert(SpillList.size()==2 && "Unexpected SpillList size"); assert(SpillList.size()==2 && "Unexpected SpillList size");
EmitCfiOffset(MBB, MBBI, dl, TII, EmitCfiOffset(MBB, MBBI, dl, TII,
MRI->getDwarfRegNum(SpillList[0].Reg, true), MCRI->getDwarfRegNum(SpillList[0].Reg, true),
SpillList[0].Offset); SpillList[0].Offset);
EmitCfiOffset(MBB, MBBI, dl, TII, EmitCfiOffset(MBB, MBBI, dl, TII,
MRI->getDwarfRegNum(SpillList[1].Reg, true), MCRI->getDwarfRegNum(SpillList[1].Reg, true),
SpillList[1].Offset); SpillList[1].Offset);
} }
} }
} }
void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const { MachineBasicBlock &MBB) const {
MachineFrameInfo &MFI = MF.getFrameInfo(); MachineFrameInfo &MFI = MF.getFrameInfo();
▲ Show 20 Lines • Show All 240 Lines • Show Last 20 Lines

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Lines case 2:
break; break;
} }
return true; return true;
} }
MCAsmBackend *llvm::createXtensaMCAsmBackend(const Target &T, MCAsmBackend *llvm::createXtensaMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
uint8_t OSABI = uint8_t OSABI =
MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS()); MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
return new llvm::XtensaMCAsmBackend(OSABI, true); return new llvm::XtensaMCAsmBackend(OSABI, true);
} }

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h

Show All 18 Lines
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
namespace llvm { namespace llvm {
class MCOperand; class MCOperand;
class XtensaInstPrinter : public MCInstPrinter { class XtensaInstPrinter : public MCInstPrinter {
public: public:
XtensaInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, XtensaInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MCRI) {}
// Automatically generated by tblgen. // Automatically generated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
static const char *getRegisterName(MCRegister Reg); static const char *getRegisterName(MCRegister Reg);
// Print the given operand. // Print the given operand.
static void printOperand(const MCOperand &MO, raw_ostream &O); static void printOperand(const MCOperand &MO, raw_ostream &O);
Show All 33 Lines

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h

Show All 33 Lines
extern Target TheXtensaTarget; extern Target TheXtensaTarget;
MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createXtensaMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createXtensaMCAsmBackend(const Target &T, MCAsmBackend *createXtensaMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MCRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectTargetWriter> std::unique_ptr<MCObjectTargetWriter>
createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian); createXtensaObjectWriter(uint8_t OSABI, bool IsLittleEndian);
} // end namespace llvm } // end namespace llvm
// Defines symbolic names for Xtensa registers. // Defines symbolic names for Xtensa registers.
// This defines a mapping from register name to register number. // This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM #define GET_REGINFO_ENUM
Show All 10 Lines

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

Show All 25 Lines
#define GET_REGINFO_MC_DESC #define GET_REGINFO_MC_DESC
#include "XtensaGenRegisterInfo.inc" #include "XtensaGenRegisterInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_MC_DESC
#include "XtensaGenSubtargetInfo.inc" #include "XtensaGenSubtargetInfo.inc"
using namespace llvm; using namespace llvm;
static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI, static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MCRI,
const Triple &TT, const Triple &TT,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
MCAsmInfo *MAI = new XtensaMCAsmInfo(TT); MCAsmInfo *MAI = new XtensaMCAsmInfo(TT);
return MAI; return MAI;
} }
static MCInstrInfo *createXtensaMCInstrInfo() { static MCInstrInfo *createXtensaMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo(); MCInstrInfo *X = new MCInstrInfo();
InitXtensaMCInstrInfo(X); InitXtensaMCInstrInfo(X);
return X; return X;
} }
static MCInstPrinter *createXtensaMCInstPrinter(const Triple &TT, static MCInstPrinter *createXtensaMCInstPrinter(const Triple &TT,
unsigned SyntaxVariant, unsigned SyntaxVariant,
const MCAsmInfo &MAI, const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) { const MCRegisterInfo &MCRI) {
return new XtensaInstPrinter(MAI, MII, MRI); return new XtensaInstPrinter(MAI, MII, MCRI);
} }
static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) { static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo(); MCRegisterInfo *X = new MCRegisterInfo();
InitXtensaMCRegisterInfo(X, Xtensa::SP); InitXtensaMCRegisterInfo(X, Xtensa::SP);
return X; return X;
} }
Show All 32 Lines

llvm/tools/llvm-dwp/llvm-dwp.cpp

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Linesint main(int argc, char **argv) {
// Get the target. // Get the target.
const Target *TheTarget = const Target *TheTarget =
TargetRegistry::lookupTarget("", *ErrOrTriple, ErrorStr); TargetRegistry::lookupTarget("", *ErrOrTriple, ErrorStr);
if (!TheTarget) if (!TheTarget)
return error(ErrorStr, Context); return error(ErrorStr, Context);
std::string TripleName = ErrOrTriple->getTriple(); std::string TripleName = ErrOrTriple->getTriple();
// Create all the MC Objects. // Create all the MC Objects.
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
return error(Twine("no register info for target ") + TripleName, Context); return error(Twine("no register info for target ") + TripleName, Context);
MCTargetOptions MCOptions = llvm::mc::InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = llvm::mc::InitMCTargetOptionsFromFlags();
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) if (!MAI)
return error("no asm info for target " + TripleName, Context); return error("no asm info for target " + TripleName, Context);
std::unique_ptr<MCSubtargetInfo> MSTI( std::unique_ptr<MCSubtargetInfo> MSTI(
TheTarget->createMCSubtargetInfo(TripleName, "", "")); TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI) if (!MSTI)
return error("no subtarget info for target " + TripleName, Context); return error("no subtarget info for target " + TripleName, Context);
MCContext MC(*ErrOrTriple, MAI.get(), MRI.get(), MSTI.get()); MCContext MC(*ErrOrTriple, MAI.get(), MCRI.get(), MSTI.get());
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(MC, /*PIC=*/false)); TheTarget->createMCObjectFileInfo(MC, /*PIC=*/false));
MC.setObjectFileInfo(MOFI.get()); MC.setObjectFileInfo(MOFI.get());
MCTargetOptions Options; MCTargetOptions Options;
auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options); auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, Options);
if (!MAB) if (!MAB)
return error("no asm backend for target " + TripleName, Context); return error("no asm backend for target " + TripleName, Context);
std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
return error("no instr info info for target " + TripleName, Context); return error("no instr info info for target " + TripleName, Context);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, MC); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, MC);
Show All 34 Lines

llvm/tools/llvm-jitlink/llvm-jitlink.cpp

Show First 20 Lines • Show All 294 Lines • ▼ Show 20 Lines handleAllErrors(
ConditionalPrintErr<orc::FailedToMaterialize>(ShowErrFailedToMaterialize), ConditionalPrintErr<orc::FailedToMaterialize>(ShowErrFailedToMaterialize),
ConditionalPrintErr<ErrorInfoBase>(true)); ConditionalPrintErr<ErrorInfoBase>(true));
} }
} // end anonymous namespace } // end anonymous namespace
namespace llvm { namespace llvm {
static raw_ostream & static raw_ostream &operator<<(raw_ostream &OS,
operator<<(raw_ostream &OS, const Session::MemoryRegionInfo &MRI) { const Session::MemoryRegionInfo &MCRI) {
return OS << "target addr = " return OS << "target addr = "
<< format("0x%016" PRIx64, MRI.getTargetAddress()) << format("0x%016" PRIx64, MCRI.getTargetAddress())
<< ", content: " << (const void *)MRI.getContent().data() << " -- " << ", content: " << (const void *)MCRI.getContent().data() << " -- "
<< (const void *)(MRI.getContent().data() + MRI.getContent().size()) << (const void *)(MCRI.getContent().data() +
<< " (" << MRI.getContent().size() << " bytes)"; MCRI.getContent().size())
<< " (" << MCRI.getContent().size() << " bytes)";
} }
static raw_ostream & static raw_ostream &
operator<<(raw_ostream &OS, const Session::SymbolInfoMap &SIM) { operator<<(raw_ostream &OS, const Session::SymbolInfoMap &SIM) {
OS << "Symbols:\n"; OS << "Symbols:\n";
for (auto &SKV : SIM) for (auto &SKV : SIM)
OS << " \"" << SKV.first() << "\" " << SKV.second << "\n"; OS << " \"" << SKV.first() << "\" " << SKV.second << "\n";
return OS; return OS;
▲ Show 20 Lines • Show All 1,467 Lines • ▼ Show 20 Linesstatic Error addSessionInputs(Session &S) {
return Error::success(); return Error::success();
} }
namespace { namespace {
struct TargetInfo { struct TargetInfo {
const Target *TheTarget; const Target *TheTarget;
std::unique_ptr<MCSubtargetInfo> STI; std::unique_ptr<MCSubtargetInfo> STI;
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<MCDisassembler> Disassembler; std::unique_ptr<MCDisassembler> Disassembler;
std::unique_ptr<MCInstrInfo> MII; std::unique_ptr<MCInstrInfo> MII;
std::unique_ptr<MCInstrAnalysis> MIA; std::unique_ptr<MCInstrAnalysis> MIA;
std::unique_ptr<MCInstPrinter> InstPrinter; std::unique_ptr<MCInstPrinter> InstPrinter;
}; };
} // anonymous namespace } // anonymous namespace
Show All 9 Linesstatic TargetInfo getTargetInfo(const Triple &TT) {
std::unique_ptr<MCSubtargetInfo> STI( std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, "", "")); TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!STI) if (!STI)
ExitOnErr( ExitOnErr(
make_error<StringError>("Unable to create subtarget for " + TripleName, make_error<StringError>("Unable to create subtarget for " + TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
ExitOnErr(make_error<StringError>("Unable to create target register info " ExitOnErr(make_error<StringError>("Unable to create target register info "
"for " + "for " +
TripleName, TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) if (!MAI)
ExitOnErr(make_error<StringError>("Unable to create target asm info " + ExitOnErr(make_error<StringError>("Unable to create target asm info " +
TripleName, TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
auto Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(), auto Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(),
MRI.get(), STI.get()); MCRI.get(), STI.get());
std::unique_ptr<MCDisassembler> Disassembler( std::unique_ptr<MCDisassembler> Disassembler(
TheTarget->createMCDisassembler(*STI, *Ctx)); TheTarget->createMCDisassembler(*STI, *Ctx));
if (!Disassembler) if (!Disassembler)
ExitOnErr(make_error<StringError>("Unable to create disassembler for " + ExitOnErr(make_error<StringError>("Unable to create disassembler for " +
TripleName, TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
ExitOnErr(make_error<StringError>("Unable to create instruction info for" + ExitOnErr(make_error<StringError>("Unable to create instruction info for" +
TripleName, TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
std::unique_ptr<MCInstrAnalysis> MIA( std::unique_ptr<MCInstrAnalysis> MIA(
TheTarget->createMCInstrAnalysis(MII.get())); TheTarget->createMCInstrAnalysis(MII.get()));
if (!MIA) if (!MIA)
ExitOnErr(make_error<StringError>( ExitOnErr(make_error<StringError>(
"Unable to create instruction analysis for" + TripleName, "Unable to create instruction analysis for" + TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
std::unique_ptr<MCInstPrinter> InstPrinter( std::unique_ptr<MCInstPrinter> InstPrinter(
TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI)); TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MCRI));
if (!InstPrinter) if (!InstPrinter)
ExitOnErr(make_error<StringError>( ExitOnErr(make_error<StringError>(
"Unable to create instruction printer for" + TripleName, "Unable to create instruction printer for" + TripleName,
inconvertibleErrorCode())); inconvertibleErrorCode()));
return {TheTarget, std::move(STI), std::move(MRI), return {TheTarget, std::move(STI), std::move(MCRI),
std::move(MAI), std::move(Ctx), std::move(Disassembler), std::move(MAI), std::move(Ctx), std::move(Disassembler),
std::move(MII), std::move(MIA), std::move(InstPrinter)}; std::move(MII), std::move(MIA), std::move(InstPrinter)};
} }
static Error runChecks(Session &S) { static Error runChecks(Session &S) {
const auto &TT = S.ES.getExecutorProcessControl().getTargetTriple(); const auto &TT = S.ES.getExecutorProcessControl().getTargetTriple();
if (CheckFiles.empty()) if (CheckFiles.empty())
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines

llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines const Target *TheTarget = TargetRegistry::lookupTarget(ArchName, TheTriple,
Error); Error);
if (!TheTarget) { if (!TheTarget) {
errs() << "error: this target '" << TheTriple.normalize() errs() << "error: this target '" << TheTriple.normalize()
<< "/" << ArchName << "', was not found: '" << Error << "'\n"; << "/" << ArchName << "', was not found: '" << Error << "'\n";
abort(); abort();
} }
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) { if (!MCRI) {
errs() << "Unable to create target register info!"; errs() << "Unable to create target register info!";
abort(); abort();
} }
MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) { if (!MAI) {
errs() << "Unable to create target asm info!"; errs() << "Unable to create target asm info!";
abort(); abort();
} }
std::unique_ptr<MCSubtargetInfo> STI( std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr);
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
const unsigned OutputAsmVariant = 0; const unsigned OutputAsmVariant = 0;
std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
MCInstPrinter *IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant, MCInstPrinter *IP = TheTarget->createMCInstPrinter(
*MAI, *MCII, *MRI); Triple(TripleName), OutputAsmVariant, *MAI, *MCII, *MCRI);
if (!IP) { if (!IP) {
errs() errs()
<< "error: unable to create instruction printer for target triple '" << "error: unable to create instruction printer for target triple '"
<< TheTriple.normalize() << "' with assembly variant " << TheTriple.normalize() << "' with assembly variant "
<< OutputAsmVariant << ".\n"; << OutputAsmVariant << ".\n";
abort(); abort();
} }
Show All 30 Lines if (FileType == OFT_AssemblyFile) {
std::unique_ptr<buffer_ostream> BOS; std::unique_ptr<buffer_ostream> BOS;
raw_pwrite_stream *OS = &Out->os(); raw_pwrite_stream *OS = &Out->os();
if (!Out->os().supportsSeeking()) { if (!Out->os().supportsSeeking()) {
BOS = std::make_unique<buffer_ostream>(Out->os()); BOS = std::make_unique<buffer_ostream>(Out->os());
OS = BOS.get(); OS = BOS.get();
} }
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer( Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),
MAB->createObjectWriter(*OS), std::unique_ptr<MCCodeEmitter>(CE), *STI, MAB->createObjectWriter(*OS), std::unique_ptr<MCCodeEmitter>(CE), *STI,
MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible, MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible,
/*DWARFMustBeAtTheEnd*/ false)); /*DWARFMustBeAtTheEnd*/ false));
} }
const int Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI, const int Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI,
*MCII, MCOptions); *MCII, MCOptions);
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/tools/llvm-mc/Disassembler.cpp

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
} }
int Disassembler::disassemble(const Target &T, const std::string &Triple, int Disassembler::disassemble(const Target &T, const std::string &Triple,
MCSubtargetInfo &STI, MCStreamer &Streamer, MCSubtargetInfo &STI, MCStreamer &Streamer,
MemoryBuffer &Buffer, SourceMgr &SM, MemoryBuffer &Buffer, SourceMgr &SM,
MCContext &Ctx, raw_ostream &Out, MCContext &Ctx, raw_ostream &Out,
const MCTargetOptions &MCOptions) { const MCTargetOptions &MCOptions) {
std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple)); std::unique_ptr<const MCRegisterInfo> MCRI(T.createMCRegInfo(Triple));
if (!MRI) { if (!MCRI) {
errs() << "error: no register info for target " << Triple << "\n"; errs() << "error: no register info for target " << Triple << "\n";
return -1; return -1;
} }
std::unique_ptr<const MCAsmInfo> MAI( std::unique_ptr<const MCAsmInfo> MAI(
T.createMCAsmInfo(*MRI, Triple, MCOptions)); T.createMCAsmInfo(*MCRI, Triple, MCOptions));
if (!MAI) { if (!MAI) {
errs() << "error: no assembly info for target " << Triple << "\n"; errs() << "error: no assembly info for target " << Triple << "\n";
return -1; return -1;
} }
std::unique_ptr<const MCDisassembler> DisAsm( std::unique_ptr<const MCDisassembler> DisAsm(
T.createMCDisassembler(STI, Ctx)); T.createMCDisassembler(STI, Ctx));
if (!DisAsm) { if (!DisAsm) {
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/tools/llvm-mc/llvm-mc.cpp

Show First 20 Lines • Show All 385 Lines • ▼ Show 20 Linesint main(int argc, char **argv) {
// Tell SrcMgr about this buffer, which is what the parser will pick up. // Tell SrcMgr about this buffer, which is what the parser will pick up.
SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc()); SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
// Record the location of the include directories so that the lexer can find // Record the location of the include directories so that the lexer can find
// it later. // it later.
SrcMgr.setIncludeDirs(IncludeDirs); SrcMgr.setIncludeDirs(IncludeDirs);
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
assert(MRI && "Unable to create target register info!"); assert(MCRI && "Unable to create target register info!");
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
assert(MAI && "Unable to create target asm info!"); assert(MAI && "Unable to create target asm info!");
MAI->setRelaxELFRelocations(RelaxELFRel); MAI->setRelaxELFRelocations(RelaxELFRel);
if (CompressDebugSections != DebugCompressionType::None) { if (CompressDebugSections != DebugCompressionType::None) {
if (const char *Reason = compression::getReasonIfUnsupported( if (const char *Reason = compression::getReasonIfUnsupported(
compression::formatFor(CompressDebugSections))) { compression::formatFor(CompressDebugSections))) {
WithColor::error(errs(), ProgName) WithColor::error(errs(), ProgName)
<< "--compress-debug-sections: " << Reason; << "--compress-debug-sections: " << Reason;
Show All 13 Linesint main(int argc, char **argv) {
} }
std::unique_ptr<MCSubtargetInfo> STI( std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
assert(STI && "Unable to create subtarget info!"); assert(STI && "Unable to create subtarget info!");
// FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
// MCObjectFileInfo needs a MCContext reference in order to initialize itself. // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr, MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr,
&MCOptions); &MCOptions);
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(Ctx, PIC, LargeCodeModel)); TheTarget->createMCObjectFileInfo(Ctx, PIC, LargeCodeModel));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
if (SaveTempLabels) if (SaveTempLabels)
Ctx.setAllowTemporaryLabels(false); Ctx.setAllowTemporaryLabels(false);
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesint main(int argc, char **argv) {
std::unique_ptr<MCStreamer> Str; std::unique_ptr<MCStreamer> Str;
std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
assert(MCII && "Unable to create instruction info!"); assert(MCII && "Unable to create instruction info!");
MCInstPrinter *IP = nullptr; MCInstPrinter *IP = nullptr;
if (FileType == OFT_AssemblyFile) { if (FileType == OFT_AssemblyFile) {
IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant, IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant,
*MAI, *MCII, *MRI); *MAI, *MCII, *MCRI);
if (!IP) { if (!IP) {
WithColor::error() WithColor::error()
<< "unable to create instruction printer for target triple '" << "unable to create instruction printer for target triple '"
<< TheTriple.normalize() << "' with assembly variant " << TheTriple.normalize() << "' with assembly variant "
<< OutputAsmVariant << ".\n"; << OutputAsmVariant << ".\n";
return 1; return 1;
} }
for (StringRef Opt : DisassemblerOptions) for (StringRef Opt : DisassemblerOptions)
if (!IP->applyTargetSpecificCLOption(Opt)) { if (!IP->applyTargetSpecificCLOption(Opt)) {
WithColor::error() << "invalid disassembler option '" << Opt << "'\n"; WithColor::error() << "invalid disassembler option '" << Opt << "'\n";
return 1; return 1;
} }
// Set the display preference for hex vs. decimal immediates. // Set the display preference for hex vs. decimal immediates.
IP->setPrintImmHex(PrintImmHex); IP->setPrintImmHex(PrintImmHex);
// Set up the AsmStreamer. // Set up the AsmStreamer.
std::unique_ptr<MCCodeEmitter> CE; std::unique_ptr<MCCodeEmitter> CE;
if (ShowEncoding) if (ShowEncoding)
CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx)); CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB( std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions)); TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions));
auto FOut = std::make_unique<formatted_raw_ostream>(*OS); auto FOut = std::make_unique<formatted_raw_ostream>(*OS);
Str.reset( Str.reset(
TheTarget->createAsmStreamer(Ctx, std::move(FOut), /*asmverbose*/ true, TheTarget->createAsmStreamer(Ctx, std::move(FOut), /*asmverbose*/ true,
/*useDwarfDirectory*/ true, IP, /*useDwarfDirectory*/ true, IP,
std::move(CE), std::move(MAB), ShowInst)); std::move(CE), std::move(MAB), ShowInst));
} else if (FileType == OFT_Null) { } else if (FileType == OFT_Null) {
Str.reset(TheTarget->createNullStreamer(Ctx)); Str.reset(TheTarget->createNullStreamer(Ctx));
} else { } else {
assert(FileType == OFT_ObjectFile && "Invalid file type!"); assert(FileType == OFT_ObjectFile && "Invalid file type!");
if (!Out->os().supportsSeeking()) { if (!Out->os().supportsSeeking()) {
BOS = std::make_unique<buffer_ostream>(Out->os()); BOS = std::make_unique<buffer_ostream>(Out->os());
OS = BOS.get(); OS = BOS.get();
} }
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer( Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),
DwoOut ? MAB->createDwoObjectWriter(*OS, DwoOut->os()) DwoOut ? MAB->createDwoObjectWriter(*OS, DwoOut->os())
: MAB->createObjectWriter(*OS), : MAB->createObjectWriter(*OS),
std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll, std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll,
MCOptions.MCIncrementalLinkerCompatible, MCOptions.MCIncrementalLinkerCompatible,
/*DWARFMustBeAtTheEnd*/ false)); /*DWARFMustBeAtTheEnd*/ false));
if (NoExecStack) if (NoExecStack)
Show All 37 Lines

llvm/tools/llvm-mca/llvm-mca.cpp

Show First 20 Lines • Show All 382 Lines • ▼ Show 20 Lines if (STI->getSchedModel().InstrItineraries)
<< "instruction itineraries are currently unsupported.\n"; << "instruction itineraries are currently unsupported.\n";
return 1; return 1;
} }
// Apply overrides to llvm-mca specific options. // Apply overrides to llvm-mca specific options.
bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder(); bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder();
processViewOptions(IsOutOfOrder); processViewOptions(IsOutOfOrder);
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
assert(MRI && "Unable to create target register info!"); assert(MCRI && "Unable to create target register info!");
MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
assert(MAI && "Unable to create target asm info!"); assert(MAI && "Unable to create target asm info!");
SourceMgr SrcMgr; SourceMgr SrcMgr;
// Tell SrcMgr about this buffer, which is what the parser will pick up. // Tell SrcMgr about this buffer, which is what the parser will pick up.
SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc()); SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), SMLoc());
MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr);
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
std::unique_ptr<buffer_ostream> BOS; std::unique_ptr<buffer_ostream> BOS;
std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
assert(MCII && "Unable to create instruction info!"); assert(MCII && "Unable to create instruction info!");
std::unique_ptr<MCInstrAnalysis> MCIA( std::unique_ptr<MCInstrAnalysis> MCIA(
TheTarget->createMCInstrAnalysis(MCII.get())); TheTarget->createMCInstrAnalysis(MCII.get()));
// Need to initialize an MCInstPrinter as it is // Need to initialize an MCInstPrinter as it is
// required for initializing the MCTargetStreamer // required for initializing the MCTargetStreamer
// which needs to happen within the CRG.parseAnalysisRegions() call below. // which needs to happen within the CRG.parseAnalysisRegions() call below.
// Without an MCTargetStreamer, certain assembly directives can trigger a // Without an MCTargetStreamer, certain assembly directives can trigger a
// segfault. (For example, the .cv_fpo_proc directive on x86 will segfault if // segfault. (For example, the .cv_fpo_proc directive on x86 will segfault if
// we don't initialize the MCTargetStreamer.) // we don't initialize the MCTargetStreamer.)
unsigned IPtempOutputAsmVariant = unsigned IPtempOutputAsmVariant =
OutputAsmVariant == -1 ? 0 : OutputAsmVariant; OutputAsmVariant == -1 ? 0 : OutputAsmVariant;
std::unique_ptr<MCInstPrinter> IPtemp(TheTarget->createMCInstPrinter( std::unique_ptr<MCInstPrinter> IPtemp(TheTarget->createMCInstPrinter(
Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MCRI));
if (!IPtemp) { if (!IPtemp) {
WithColor::error() WithColor::error()
<< "unable to create instruction printer for target triple '" << "unable to create instruction printer for target triple '"
<< TheTriple.normalize() << "' with assembly variant " << TheTriple.normalize() << "' with assembly variant "
<< IPtempOutputAsmVariant << ".\n"; << IPtempOutputAsmVariant << ".\n";
return 1; return 1;
} }
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines if (std::error_code EC = OF.getError()) {
WithColor::error() << EC.message() << '\n'; WithColor::error() << EC.message() << '\n';
return 1; return 1;
} }
unsigned AssemblerDialect = CRG.getAssemblerDialect(); unsigned AssemblerDialect = CRG.getAssemblerDialect();
if (OutputAsmVariant >= 0) if (OutputAsmVariant >= 0)
AssemblerDialect = static_cast<unsigned>(OutputAsmVariant); AssemblerDialect = static_cast<unsigned>(OutputAsmVariant);
std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter( std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MCRI));
if (!IP) { if (!IP) {
WithColor::error() WithColor::error()
<< "unable to create instruction printer for target triple '" << "unable to create instruction printer for target triple '"
<< TheTriple.normalize() << "' with assembly variant " << TheTriple.normalize() << "' with assembly variant "
<< AssemblerDialect << ".\n"; << AssemblerDialect << ".\n";
return 1; return 1;
} }
Show All 15 Linesint main(int argc, char **argv) {
} }
if (!IPP) { if (!IPP) {
// If the target doesn't have its own IPP implemented (or the -disable-cb // If the target doesn't have its own IPP implemented (or the -disable-cb
// flag is set) then we use the base class (which does nothing). // flag is set) then we use the base class (which does nothing).
IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII); IPP = std::make_unique<mca::InstrPostProcess>(*STI, *MCII);
} }
// Create an instruction builder. // Create an instruction builder.
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM);
// Create a context to control ownership of the pipeline hardware. // Create a context to control ownership of the pipeline hardware.
mca::Context MCA(*MRI, *STI); mca::Context MCA(*MCRI, *STI);
mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth, mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth,
RegisterFileSize, LoadQueueSize, StoreQueueSize, RegisterFileSize, LoadQueueSize, StoreQueueSize,
AssumeNoAlias, EnableBottleneckAnalysis); AssumeNoAlias, EnableBottleneckAnalysis);
// Number each region in the sequence. // Number each region in the sequence.
unsigned RegionIdx = 0; unsigned RegionIdx = 0;
std::unique_ptr<MCCodeEmitter> MCE( std::unique_ptr<MCCodeEmitter> MCE(
TheTarget->createMCCodeEmitter(*MCII, Ctx)); TheTarget->createMCCodeEmitter(*MCII, Ctx));
assert(MCE && "Unable to create code emitter!"); assert(MCE && "Unable to create code emitter!");
std::unique_ptr<MCAsmBackend> MAB(TheTarget->createMCAsmBackend( std::unique_ptr<MCAsmBackend> MAB(TheTarget->createMCAsmBackend(
*STI, *MRI, mc::InitMCTargetOptionsFromFlags())); *STI, *MCRI, mc::InitMCTargetOptionsFromFlags()));
assert(MAB && "Unable to create asm backend!"); assert(MAB && "Unable to create asm backend!");
json::Object JSONOutput; json::Object JSONOutput;
for (const std::unique_ptr<mca::AnalysisRegion> &Region : Regions) { for (const std::unique_ptr<mca::AnalysisRegion> &Region : Regions) {
// Skip empty code regions. // Skip empty code regions.
if (Region->empty()) if (Region->empty())
continue; continue;
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/tools/llvm-ml/Disassembler.cpp

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Linesstatic bool ByteArrayFromString(ByteArrayTy &ByteArray, StringRef &Str,
return false; return false;
} }
int Disassembler::disassemble(const Target &T, const std::string &TripleName, int Disassembler::disassemble(const Target &T, const std::string &TripleName,
MCSubtargetInfo &STI, MCStreamer &Streamer, MCSubtargetInfo &STI, MCStreamer &Streamer,
MemoryBuffer &Buffer, SourceMgr &SM, MemoryBuffer &Buffer, SourceMgr &SM,
raw_ostream &Out) { raw_ostream &Out) {
std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(TripleName)); std::unique_ptr<const MCRegisterInfo> MCRI(T.createMCRegInfo(TripleName));
if (!MRI) { if (!MCRI) {
errs() << "error: no register info for target " << TripleName << "\n"; errs() << "error: no register info for target " << TripleName << "\n";
return -1; return -1;
} }
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<const MCAsmInfo> MAI( std::unique_ptr<const MCAsmInfo> MAI(
T.createMCAsmInfo(*MRI, TripleName, MCOptions)); T.createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) { if (!MAI) {
errs() << "error: no assembly info for target " << TripleName << "\n"; errs() << "error: no assembly info for target " << TripleName << "\n";
return -1; return -1;
} }
// Set up the MCContext for creating symbols and MCExpr's. // Set up the MCContext for creating symbols and MCExpr's.
MCContext Ctx(Triple(TripleName), MAI.get(), MRI.get(), &STI); MCContext Ctx(Triple(TripleName), MAI.get(), MCRI.get(), &STI);
std::unique_ptr<const MCDisassembler> DisAsm( std::unique_ptr<const MCDisassembler> DisAsm(
T.createMCDisassembler(STI, Ctx)); T.createMCDisassembler(STI, Ctx));
if (!DisAsm) { if (!DisAsm) {
errs() << "error: no disassembler for target " << TripleName << "\n"; errs() << "error: no disassembler for target " << TripleName << "\n";
return -1; return -1;
} }
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/tools/llvm-ml/llvm-ml.cpp

Show First 20 Lines • Show All 313 Lines • ▼ Show 20 Lines if (std::optional<std::string> IncludeEnvVar =
.split(Dirs, ";", /*MaxSplit=*/-1, /*KeepEmpty=*/false); .split(Dirs, ";", /*MaxSplit=*/-1, /*KeepEmpty=*/false);
IncludeDirs.reserve(IncludeDirs.size() + Dirs.size()); IncludeDirs.reserve(IncludeDirs.size() + Dirs.size());
for (StringRef Dir : Dirs) for (StringRef Dir : Dirs)
IncludeDirs.push_back(Dir.str()); IncludeDirs.push_back(Dir.str());
} }
} }
SrcMgr.setIncludeDirs(IncludeDirs); SrcMgr.setIncludeDirs(IncludeDirs);
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
assert(MRI && "Unable to create target register info!"); assert(MCRI && "Unable to create target register info!");
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
assert(MAI && "Unable to create target asm info!"); assert(MAI && "Unable to create target asm info!");
MAI->setPreserveAsmComments(InputArgs.hasArg(OPT_preserve_comments)); MAI->setPreserveAsmComments(InputArgs.hasArg(OPT_preserve_comments));
std::unique_ptr<MCSubtargetInfo> STI(TheTarget->createMCSubtargetInfo( std::unique_ptr<MCSubtargetInfo> STI(TheTarget->createMCSubtargetInfo(
TripleName, /*CPU=*/"", /*Features=*/"")); TripleName, /*CPU=*/"", /*Features=*/""));
assert(STI && "Unable to create subtarget info!"); assert(STI && "Unable to create subtarget info!");
// FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
// MCObjectFileInfo needs a MCContext reference in order to initialize itself. // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
MCContext Ctx(TheTriple, MAI.get(), MRI.get(), STI.get(), &SrcMgr); MCContext Ctx(TheTriple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr);
std::unique_ptr<MCObjectFileInfo> MOFI(TheTarget->createMCObjectFileInfo( std::unique_ptr<MCObjectFileInfo> MOFI(TheTarget->createMCObjectFileInfo(
Ctx, /*PIC=*/false, /*LargeCodeModel=*/true)); Ctx, /*PIC=*/false, /*LargeCodeModel=*/true));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
if (InputArgs.hasArg(OPT_save_temp_labels)) if (InputArgs.hasArg(OPT_save_temp_labels))
Ctx.setAllowTemporaryLabels(false); Ctx.setAllowTemporaryLabels(false);
// Set compilation information. // Set compilation information.
Show All 24 Linesint main(int Argc, char **Argv) {
assert(MCII && "Unable to create instruction info!"); assert(MCII && "Unable to create instruction info!");
MCInstPrinter *IP = nullptr; MCInstPrinter *IP = nullptr;
if (FileType == "s") { if (FileType == "s") {
const bool OutputATTAsm = InputArgs.hasArg(OPT_output_att_asm); const bool OutputATTAsm = InputArgs.hasArg(OPT_output_att_asm);
const unsigned OutputAsmVariant = OutputATTAsm ? 0U // ATT dialect const unsigned OutputAsmVariant = OutputATTAsm ? 0U // ATT dialect
: 1U; // Intel dialect : 1U; // Intel dialect
IP = TheTarget->createMCInstPrinter(TheTriple, OutputAsmVariant, *MAI, IP = TheTarget->createMCInstPrinter(TheTriple, OutputAsmVariant, *MAI,
*MCII, *MRI); *MCII, *MCRI);
if (!IP) { if (!IP) {
WithColor::error() WithColor::error()
<< "unable to create instruction printer for target triple '" << "unable to create instruction printer for target triple '"
<< TheTriple.normalize() << "' with " << TheTriple.normalize() << "' with "
<< (OutputATTAsm ? "ATT" : "Intel") << " assembly variant.\n"; << (OutputATTAsm ? "ATT" : "Intel") << " assembly variant.\n";
return 1; return 1;
} }
// Set the display preference for hex vs. decimal immediates. // Set the display preference for hex vs. decimal immediates.
IP->setPrintImmHex(InputArgs.hasArg(OPT_print_imm_hex)); IP->setPrintImmHex(InputArgs.hasArg(OPT_print_imm_hex));
// Set up the AsmStreamer. // Set up the AsmStreamer.
std::unique_ptr<MCCodeEmitter> CE; std::unique_ptr<MCCodeEmitter> CE;
if (InputArgs.hasArg(OPT_show_encoding)) if (InputArgs.hasArg(OPT_show_encoding))
CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx)); CE.reset(TheTarget->createMCCodeEmitter(*MCII, Ctx));
std::unique_ptr<MCAsmBackend> MAB( std::unique_ptr<MCAsmBackend> MAB(
TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions)); TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions));
auto FOut = std::make_unique<formatted_raw_ostream>(*OS); auto FOut = std::make_unique<formatted_raw_ostream>(*OS);
Str.reset(TheTarget->createAsmStreamer( Str.reset(TheTarget->createAsmStreamer(
Ctx, std::move(FOut), /*asmverbose*/ true, Ctx, std::move(FOut), /*asmverbose*/ true,
/*useDwarfDirectory*/ true, IP, std::move(CE), std::move(MAB), /*useDwarfDirectory*/ true, IP, std::move(CE), std::move(MAB),
InputArgs.hasArg(OPT_show_inst))); InputArgs.hasArg(OPT_show_inst)));
} else if (FileType == "null") { } else if (FileType == "null") {
Str.reset(TheTarget->createNullStreamer(Ctx)); Str.reset(TheTarget->createNullStreamer(Ctx));
} else if (FileType == "obj") { } else if (FileType == "obj") {
if (!Out->os().supportsSeeking()) { if (!Out->os().supportsSeeking()) {
BOS = std::make_unique<buffer_ostream>(Out->os()); BOS = std::make_unique<buffer_ostream>(Out->os());
OS = BOS.get(); OS = BOS.get();
} }
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx); MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions); MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MCRI, MCOptions);
Str.reset(TheTarget->createMCObjectStreamer( Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB),
MAB->createObjectWriter(*OS), std::unique_ptr<MCCodeEmitter>(CE), *STI, MAB->createObjectWriter(*OS), std::unique_ptr<MCCodeEmitter>(CE), *STI,
MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible, MCOptions.MCRelaxAll, MCOptions.MCIncrementalLinkerCompatible,
/*DWARFMustBeAtTheEnd*/ false)); /*DWARFMustBeAtTheEnd*/ false));
} else { } else {
llvm_unreachable("Invalid file type!"); llvm_unreachable("Invalid file type!");
} }
Show All 35 Lines

llvm/tools/llvm-objdump/MachODump.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,572 Lines • ▼ Show 20 Lines if (!MAttrs.empty()) {
SubtargetFeatures Features; SubtargetFeatures Features;
for (unsigned i = 0; i != MAttrs.size(); ++i) for (unsigned i = 0; i != MAttrs.size(); ++i)
Features.AddFeature(MAttrs[i]); Features.AddFeature(MAttrs[i]);
FeaturesStr = Features.getString(); FeaturesStr = Features.getString();
} }
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
// Set up disassembler. // Set up disassembler.
std::unique_ptr<const MCRegisterInfo> MRI( std::unique_ptr<const MCRegisterInfo> MCRI(
TheTarget->createMCRegInfo(TripleName)); TheTarget->createMCRegInfo(TripleName));
CHECK_TARGET_INFO_CREATION(MRI); CHECK_TARGET_INFO_CREATION(MCRI);
std::unique_ptr<const MCAsmInfo> AsmInfo( std::unique_ptr<const MCAsmInfo> AsmInfo(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
CHECK_TARGET_INFO_CREATION(AsmInfo); CHECK_TARGET_INFO_CREATION(AsmInfo);
std::unique_ptr<const MCSubtargetInfo> STI( std::unique_ptr<const MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, MachOMCPU, FeaturesStr)); TheTarget->createMCSubtargetInfo(TripleName, MachOMCPU, FeaturesStr));
CHECK_TARGET_INFO_CREATION(STI); CHECK_TARGET_INFO_CREATION(STI);
MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get());
std::unique_ptr<MCDisassembler> DisAsm( std::unique_ptr<MCDisassembler> DisAsm(
TheTarget->createMCDisassembler(*STI, Ctx)); TheTarget->createMCDisassembler(*STI, Ctx));
CHECK_TARGET_INFO_CREATION(DisAsm); CHECK_TARGET_INFO_CREATION(DisAsm);
std::unique_ptr<MCSymbolizer> Symbolizer; std::unique_ptr<MCSymbolizer> Symbolizer;
struct DisassembleInfo SymbolizerInfo(nullptr, nullptr, nullptr, false); struct DisassembleInfo SymbolizerInfo(nullptr, nullptr, nullptr, false);
std::unique_ptr<MCRelocationInfo> RelInfo( std::unique_ptr<MCRelocationInfo> RelInfo(
TheTarget->createMCRelocationInfo(TripleName, Ctx)); TheTarget->createMCRelocationInfo(TripleName, Ctx));
if (RelInfo) { if (RelInfo) {
Symbolizer.reset(TheTarget->createMCSymbolizer( Symbolizer.reset(TheTarget->createMCSymbolizer(
TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp, TripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
&SymbolizerInfo, &Ctx, std::move(RelInfo))); &SymbolizerInfo, &Ctx, std::move(RelInfo)));
DisAsm->setSymbolizer(std::move(Symbolizer)); DisAsm->setSymbolizer(std::move(Symbolizer));
} }
int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter( std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MCRI));
CHECK_TARGET_INFO_CREATION(IP); CHECK_TARGET_INFO_CREATION(IP);
// Set the display preference for hex vs. decimal immediates. // Set the display preference for hex vs. decimal immediates.
IP->setPrintImmHex(PrintImmHex); IP->setPrintImmHex(PrintImmHex);
// Comment stream and backing vector. // Comment stream and backing vector.
SmallString<128> CommentsToEmit; SmallString<128> CommentsToEmit;
raw_svector_ostream CommentStream(CommentsToEmit); raw_svector_ostream CommentStream(CommentsToEmit);
// FIXME: Setting the CommentStream in the InstPrinter is problematic in that // FIXME: Setting the CommentStream in the InstPrinter is problematic in that
// if it is done then arm64 comments for string literals don't get printed // if it is done then arm64 comments for string literals don't get printed
// and some constant get printed instead and not setting it causes intel // and some constant get printed instead and not setting it causes intel
// (32-bit and 64-bit) comments printed with different spacing before the // (32-bit and 64-bit) comments printed with different spacing before the
// comment causing different diffs with the 'C' disassembler library API. // comment causing different diffs with the 'C' disassembler library API.
// IP->setCommentStream(CommentStream); // IP->setCommentStream(CommentStream);
// Set up separate thumb disassembler if needed. // Set up separate thumb disassembler if needed.
std::unique_ptr<const MCRegisterInfo> ThumbMRI; std::unique_ptr<const MCRegisterInfo> ThumbMCRI;
std::unique_ptr<const MCAsmInfo> ThumbAsmInfo; std::unique_ptr<const MCAsmInfo> ThumbAsmInfo;
std::unique_ptr<const MCSubtargetInfo> ThumbSTI; std::unique_ptr<const MCSubtargetInfo> ThumbSTI;
std::unique_ptr<MCDisassembler> ThumbDisAsm; std::unique_ptr<MCDisassembler> ThumbDisAsm;
std::unique_ptr<MCInstPrinter> ThumbIP; std::unique_ptr<MCInstPrinter> ThumbIP;
std::unique_ptr<MCContext> ThumbCtx; std::unique_ptr<MCContext> ThumbCtx;
std::unique_ptr<MCSymbolizer> ThumbSymbolizer; std::unique_ptr<MCSymbolizer> ThumbSymbolizer;
struct DisassembleInfo ThumbSymbolizerInfo(nullptr, nullptr, nullptr, false); struct DisassembleInfo ThumbSymbolizerInfo(nullptr, nullptr, nullptr, false);
std::unique_ptr<MCRelocationInfo> ThumbRelInfo; std::unique_ptr<MCRelocationInfo> ThumbRelInfo;
if (ThumbTarget) { if (ThumbTarget) {
ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); ThumbMCRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName));
CHECK_THUMB_TARGET_INFO_CREATION(ThumbMRI); CHECK_THUMB_TARGET_INFO_CREATION(ThumbMCRI);
ThumbAsmInfo.reset( ThumbAsmInfo.reset(
ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName, MCOptions)); ThumbTarget->createMCAsmInfo(*ThumbMCRI, ThumbTripleName, MCOptions));
CHECK_THUMB_TARGET_INFO_CREATION(ThumbAsmInfo); CHECK_THUMB_TARGET_INFO_CREATION(ThumbAsmInfo);
ThumbSTI.reset( ThumbSTI.reset(
ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MachOMCPU, ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MachOMCPU,
FeaturesStr)); FeaturesStr));
CHECK_THUMB_TARGET_INFO_CREATION(ThumbSTI); CHECK_THUMB_TARGET_INFO_CREATION(ThumbSTI);
ThumbCtx.reset(new MCContext(Triple(ThumbTripleName), ThumbAsmInfo.get(), ThumbCtx.reset(new MCContext(Triple(ThumbTripleName), ThumbAsmInfo.get(),
ThumbMRI.get(), ThumbSTI.get())); ThumbMCRI.get(), ThumbSTI.get()));
ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx)); ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx));
CHECK_THUMB_TARGET_INFO_CREATION(ThumbDisAsm); CHECK_THUMB_TARGET_INFO_CREATION(ThumbDisAsm);
MCContext *PtrThumbCtx = ThumbCtx.get(); MCContext *PtrThumbCtx = ThumbCtx.get();
ThumbRelInfo.reset( ThumbRelInfo.reset(
ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx)); ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx));
if (ThumbRelInfo) { if (ThumbRelInfo) {
ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer( ThumbSymbolizer.reset(ThumbTarget->createMCSymbolizer(
ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp, ThumbTripleName, SymbolizerGetOpInfo, SymbolizerSymbolLookUp,
&ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo))); &ThumbSymbolizerInfo, PtrThumbCtx, std::move(ThumbRelInfo)));
ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer)); ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer));
} }
int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect(); int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect();
ThumbIP.reset(ThumbTarget->createMCInstPrinter( ThumbIP.reset(ThumbTarget->createMCInstPrinter(
Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo, Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo,
*ThumbInstrInfo, *ThumbMRI)); *ThumbInstrInfo, *ThumbMCRI));
CHECK_THUMB_TARGET_INFO_CREATION(ThumbIP); CHECK_THUMB_TARGET_INFO_CREATION(ThumbIP);
// Set the display preference for hex vs. decimal immediates. // Set the display preference for hex vs. decimal immediates.
ThumbIP->setPrintImmHex(PrintImmHex); ThumbIP->setPrintImmHex(PrintImmHex);
} }
#undef CHECK_TARGET_INFO_CREATION #undef CHECK_TARGET_INFO_CREATION
#undef CHECK_THUMB_TARGET_INFO_CREATION #undef CHECK_THUMB_TARGET_INFO_CREATION
▲ Show 20 Lines • Show All 3,164 Lines • Show Last 20 Lines

llvm/tools/llvm-objdump/SourcePrinter.h

Show All 30 Linesstruct LiveVariable {
const DWARFDie FuncDie; const DWARFDie FuncDie;
LiveVariable(const DWARFLocationExpression &LocExpr, const char *VarName, LiveVariable(const DWARFLocationExpression &LocExpr, const char *VarName,
DWARFUnit *Unit, const DWARFDie FuncDie) DWARFUnit *Unit, const DWARFDie FuncDie)
: LocExpr(LocExpr), VarName(VarName), Unit(Unit), FuncDie(FuncDie) {} : LocExpr(LocExpr), VarName(VarName), Unit(Unit), FuncDie(FuncDie) {}
bool liveAtAddress(object::SectionedAddress Addr); bool liveAtAddress(object::SectionedAddress Addr);
void print(raw_ostream &OS, const MCRegisterInfo &MRI) const; void print(raw_ostream &OS, const MCRegisterInfo &MCRI) const;
}; };
/// Helper class for printing source variable locations alongside disassembly. /// Helper class for printing source variable locations alongside disassembly.
class LiveVariablePrinter { class LiveVariablePrinter {
// Information we want to track about one column in which we are printing a // Information we want to track about one column in which we are printing a
// variable live range. // variable live range.
struct Column { struct Column {
unsigned VarIdx = NullVarIdx; unsigned VarIdx = NullVarIdx;
bool LiveIn = false; bool LiveIn = false;
bool LiveOut = false; bool LiveOut = false;
bool MustDrawLabel = false; bool MustDrawLabel = false;
bool isActive() const { return VarIdx != NullVarIdx; } bool isActive() const { return VarIdx != NullVarIdx; }
static constexpr unsigned NullVarIdx = std::numeric_limits<unsigned>::max(); static constexpr unsigned NullVarIdx = std::numeric_limits<unsigned>::max();
}; };
// All live variables we know about in the object/image file. // All live variables we know about in the object/image file.
std::vector<LiveVariable> LiveVariables; std::vector<LiveVariable> LiveVariables;
// The columns we are currently drawing. // The columns we are currently drawing.
IndexedMap<Column> ActiveCols; IndexedMap<Column> ActiveCols;
const MCRegisterInfo &MRI; const MCRegisterInfo &MCRI;
const MCSubtargetInfo &STI; const MCSubtargetInfo &STI;
void addVariable(DWARFDie FuncDie, DWARFDie VarDie); void addVariable(DWARFDie FuncDie, DWARFDie VarDie);
void addFunction(DWARFDie D); void addFunction(DWARFDie D);
// Get the column number (in characters) at which the first live variable // Get the column number (in characters) at which the first live variable
// line should be printed. // line should be printed.
unsigned getIndentLevel() const; unsigned getIndentLevel() const;
// Indent to the first live-range column to the right of the currently // Indent to the first live-range column to the right of the currently
// printed line, and return the index of that column. // printed line, and return the index of that column.
// TODO: formatted_raw_ostream uses "column" to mean a number of characters // TODO: formatted_raw_ostream uses "column" to mean a number of characters
// since the last \n, and we use it to mean the number of slots in which we // since the last \n, and we use it to mean the number of slots in which we
// put live variable lines. Pick a less overloaded word. // put live variable lines. Pick a less overloaded word.
unsigned moveToFirstVarColumn(formatted_raw_ostream &OS); unsigned moveToFirstVarColumn(formatted_raw_ostream &OS);
unsigned findFreeColumn(); unsigned findFreeColumn();
public: public:
LiveVariablePrinter(const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) LiveVariablePrinter(const MCRegisterInfo &MCRI, const MCSubtargetInfo &STI)
: ActiveCols(Column()), MRI(MRI), STI(STI) {} : ActiveCols(Column()), MCRI(MCRI), STI(STI) {}
void dump() const; void dump() const;
void addCompileUnit(DWARFDie D); void addCompileUnit(DWARFDie D);
/// Update to match the state of the instruction between ThisAddr and /// Update to match the state of the instruction between ThisAddr and
/// NextAddr. In the common case, any live range active at ThisAddr is /// NextAddr. In the common case, any live range active at ThisAddr is
/// live-in to the instruction, and any live range active at NextAddr is /// live-in to the instruction, and any live range active at NextAddr is
▲ Show 20 Lines • Show All 75 Lines • Show Last 20 Lines

llvm/tools/llvm-objdump/SourcePrinter.cpp

Show All 32 Lines
bool LiveVariable::liveAtAddress(object::SectionedAddress Addr) { bool LiveVariable::liveAtAddress(object::SectionedAddress Addr) {
if (LocExpr.Range == std::nullopt) if (LocExpr.Range == std::nullopt)
return false; return false;
return LocExpr.Range->SectionIndex == Addr.SectionIndex && return LocExpr.Range->SectionIndex == Addr.SectionIndex &&
LocExpr.Range->LowPC <= Addr.Address && LocExpr.Range->LowPC <= Addr.Address &&
LocExpr.Range->HighPC > Addr.Address; LocExpr.Range->HighPC > Addr.Address;
} }
void LiveVariable::print(raw_ostream &OS, const MCRegisterInfo &MRI) const { void LiveVariable::print(raw_ostream &OS, const MCRegisterInfo &MCRI) const {
DataExtractor Data({LocExpr.Expr.data(), LocExpr.Expr.size()}, DataExtractor Data({LocExpr.Expr.data(), LocExpr.Expr.size()},
Unit->getContext().isLittleEndian(), 0); Unit->getContext().isLittleEndian(), 0);
DWARFExpression Expression(Data, Unit->getAddressByteSize()); DWARFExpression Expression(Data, Unit->getAddressByteSize());
auto GetRegName = [&MRI, &OS](uint64_t DwarfRegNum, bool IsEH) -> StringRef { auto GetRegName = [&MCRI, &OS](uint64_t DwarfRegNum, bool IsEH) -> StringRef {
if (std::optional<unsigned> LLVMRegNum = if (std::optional<unsigned> LLVMRegNum =
MRI.getLLVMRegNum(DwarfRegNum, IsEH)) MCRI.getLLVMRegNum(DwarfRegNum, IsEH))
if (const char *RegName = MRI.getName(*LLVMRegNum)) if (const char *RegName = MCRI.getName(*LLVMRegNum))
return StringRef(RegName); return StringRef(RegName);
OS << "<unknown register " << DwarfRegNum << ">"; OS << "<unknown register " << DwarfRegNum << ">";
return {}; return {};
}; };
Expression.printCompact(OS, GetRegName); Expression.printCompact(OS, GetRegName);
} }
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesunsigned LiveVariablePrinter::findFreeColumn() {
size_t OldSize = ActiveCols.size(); size_t OldSize = ActiveCols.size();
ActiveCols.grow(std::max<size_t>(OldSize * 2, 1)); ActiveCols.grow(std::max<size_t>(OldSize * 2, 1));
return OldSize; return OldSize;
} }
void LiveVariablePrinter::dump() const { void LiveVariablePrinter::dump() const {
for (const LiveVariable &LV : LiveVariables) { for (const LiveVariable &LV : LiveVariables) {
dbgs() << LV.VarName << " @ " << LV.LocExpr.Range << ": "; dbgs() << LV.VarName << " @ " << LV.LocExpr.Range << ": ";
LV.print(dbgs(), MRI); LV.print(dbgs(), MCRI);
dbgs() << "\n"; dbgs() << "\n";
} }
} }
void LiveVariablePrinter::addCompileUnit(DWARFDie D) { void LiveVariablePrinter::addCompileUnit(DWARFDie D) {
if (D.getTag() == dwarf::DW_TAG_subprogram) if (D.getTag() == dwarf::DW_TAG_subprogram)
addFunction(D); addFunction(D);
else else
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines if (ActiveCols[ColIdx].isActive() && ActiveCols[ColIdx].MustDrawLabel) {
OS << getLineChar(ActiveCols[ColIdx].LiveIn ? LineChar::LabelCornerActive OS << getLineChar(ActiveCols[ColIdx].LiveIn ? LineChar::LabelCornerActive
: LineChar::LabelCornerNew) : LineChar::LabelCornerNew)
<< getLineChar(LineChar::LabelHoriz) << " "; << getLineChar(LineChar::LabelHoriz) << " ";
WithColor(OS, raw_ostream::GREEN) WithColor(OS, raw_ostream::GREEN)
<< LiveVariables[ActiveCols[ColIdx].VarIdx].VarName; << LiveVariables[ActiveCols[ColIdx].VarIdx].VarName;
OS << " = "; OS << " = ";
{ {
WithColor ExprColor(OS, raw_ostream::CYAN); WithColor ExprColor(OS, raw_ostream::CYAN);
LiveVariables[ActiveCols[ColIdx].VarIdx].print(OS, MRI); LiveVariables[ActiveCols[ColIdx].VarIdx].print(OS, MCRI);
} }
// If there are any columns to the right of the expression we just // If there are any columns to the right of the expression we just
// printed, then continue their live range lines. // printed, then continue their live range lines.
unsigned FirstUnprintedColumn = moveToFirstVarColumn(OS); unsigned FirstUnprintedColumn = moveToFirstVarColumn(OS);
for (unsigned ColIdx2 = FirstUnprintedColumn, End = ActiveCols.size(); for (unsigned ColIdx2 = FirstUnprintedColumn, End = ActiveCols.size();
ColIdx2 < End; ++ColIdx2) { ColIdx2 < End; ++ColIdx2) {
if (ActiveCols[ColIdx2].isActive() && ActiveCols[ColIdx2].LiveIn) if (ActiveCols[ColIdx2].isActive() && ActiveCols[ColIdx2].LiveIn)
▲ Show 20 Lines • Show All 191 Lines • Show Last 20 Lines

llvm/tools/llvm-objdump/llvm-objdump.cpp

Show First 20 Lines • Show All 2,014 Lines • ▼ Show 20 Linesstatic void disassembleObject(ObjectFile *Obj, bool InlineRelocs) {
SubtargetFeatures Features = *FeaturesValue; SubtargetFeatures Features = *FeaturesValue;
if (!MAttrs.empty()) { if (!MAttrs.empty()) {
for (unsigned I = 0; I != MAttrs.size(); ++I) for (unsigned I = 0; I != MAttrs.size(); ++I)
Features.AddFeature(MAttrs[I]); Features.AddFeature(MAttrs[I]);
} else if (MCPU.empty() && Obj->getArch() == llvm::Triple::aarch64) { } else if (MCPU.empty() && Obj->getArch() == llvm::Triple::aarch64) {
Features.AddFeature("+all"); Features.AddFeature("+all");
} }
std::unique_ptr<const MCRegisterInfo> MRI( std::unique_ptr<const MCRegisterInfo> MCRI(
TheTarget->createMCRegInfo(TripleName)); TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
reportError(Obj->getFileName(), reportError(Obj->getFileName(),
"no register info for target " + TripleName); "no register info for target " + TripleName);
// Set up disassembler. // Set up disassembler.
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<const MCAsmInfo> AsmInfo( std::unique_ptr<const MCAsmInfo> AsmInfo(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!AsmInfo) if (!AsmInfo)
reportError(Obj->getFileName(), reportError(Obj->getFileName(),
"no assembly info for target " + TripleName); "no assembly info for target " + TripleName);
if (MCPU.empty()) if (MCPU.empty())
MCPU = Obj->tryGetCPUName().value_or("").str(); MCPU = Obj->tryGetCPUName().value_or("").str();
if (isArmElf(*Obj)) { if (isArmElf(*Obj)) {
Show All 23 Lines std::unique_ptr<const MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, MCPU, Features.getString())); TheTarget->createMCSubtargetInfo(TripleName, MCPU, Features.getString()));
if (!STI) if (!STI)
reportError(Obj->getFileName(), reportError(Obj->getFileName(),
"no subtarget info for target " + TripleName); "no subtarget info for target " + TripleName);
std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
reportError(Obj->getFileName(), reportError(Obj->getFileName(),
"no instruction info for target " + TripleName); "no instruction info for target " + TripleName);
MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get());
// FIXME: for now initialize MCObjectFileInfo with default values // FIXME: for now initialize MCObjectFileInfo with default values
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
std::unique_ptr<MCDisassembler> DisAsm( std::unique_ptr<MCDisassembler> DisAsm(
TheTarget->createMCDisassembler(*STI, Ctx)); TheTarget->createMCDisassembler(*STI, Ctx));
if (!DisAsm) if (!DisAsm)
Show All 15 Lines if (isArmElf(*Obj) && !STI->checkFeatures("+mclass")) {
SecondaryDisAsm.reset(TheTarget->createMCDisassembler(*SecondarySTI, Ctx)); SecondaryDisAsm.reset(TheTarget->createMCDisassembler(*SecondarySTI, Ctx));
} }
std::unique_ptr<const MCInstrAnalysis> MIA( std::unique_ptr<const MCInstrAnalysis> MIA(
TheTarget->createMCInstrAnalysis(MII.get())); TheTarget->createMCInstrAnalysis(MII.get()));
int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter( std::unique_ptr<MCInstPrinter> IP(TheTarget->createMCInstPrinter(
Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MCRI));
if (!IP) if (!IP)
reportError(Obj->getFileName(), reportError(Obj->getFileName(),
"no instruction printer for target " + TripleName); "no instruction printer for target " + TripleName);
IP->setPrintImmHex(PrintImmHex); IP->setPrintImmHex(PrintImmHex);
IP->setPrintBranchImmAsAddress(true); IP->setPrintBranchImmAsAddress(true);
IP->setSymbolizeOperands(SymbolizeOperands); IP->setSymbolizeOperands(SymbolizeOperands);
IP->setMCInstrAnalysis(MIA.get()); IP->setMCInstrAnalysis(MIA.get());
▲ Show 20 Lines • Show All 1,145 Lines • Show Last 20 Lines

llvm/tools/llvm-profgen/ProfiledBinary.h

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Linesclass ProfiledBinary {
// The runtime base address that the first loadabe segment is loaded at. // The runtime base address that the first loadabe segment is loaded at.
uint64_t FirstLoadableAddress = 0; uint64_t FirstLoadableAddress = 0;
// The preferred load address of each executable segment. // The preferred load address of each executable segment.
std::vector<uint64_t> PreferredTextSegmentAddresses; std::vector<uint64_t> PreferredTextSegmentAddresses;
// The file offset of each executable segment. // The file offset of each executable segment.
std::vector<uint64_t> TextSegmentOffsets; std::vector<uint64_t> TextSegmentOffsets;
// Mutiple MC component info // Mutiple MC component info
std::unique_ptr<const MCRegisterInfo> MRI; std::unique_ptr<const MCRegisterInfo> MCRI;
std::unique_ptr<const MCAsmInfo> AsmInfo; std::unique_ptr<const MCAsmInfo> AsmInfo;
std::unique_ptr<const MCSubtargetInfo> STI; std::unique_ptr<const MCSubtargetInfo> STI;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<MCDisassembler> DisAsm; std::unique_ptr<MCDisassembler> DisAsm;
std::unique_ptr<const MCInstrAnalysis> MIA; std::unique_ptr<const MCInstrAnalysis> MIA;
std::unique_ptr<MCInstPrinter> IPrinter; std::unique_ptr<MCInstPrinter> IPrinter;
// A list of text sections sorted by start RVA and size. Used to check // A list of text sections sorted by start RVA and size. Used to check
// if a given RVA is a valid code address. // if a given RVA is a valid code address.
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llvm/tools/llvm-profgen/ProfiledBinary.cpp

Show First 20 Lines • Show All 596 Lines • ▼ Show 20 Linesbool ProfiledBinary::dissassembleSymbol(std::size_t SI, ArrayRef<uint8_t> Bytes,
return true; return true;
} }
void ProfiledBinary::setUpDisassembler(const ELFObjectFileBase *Obj) { void ProfiledBinary::setUpDisassembler(const ELFObjectFileBase *Obj) {
const Target *TheTarget = getTarget(Obj); const Target *TheTarget = getTarget(Obj);
std::string TripleName = TheTriple.getTriple(); std::string TripleName = TheTriple.getTriple();
StringRef FileName = Obj->getFileName(); StringRef FileName = Obj->getFileName();
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
exitWithError("no register info for target " + TripleName, FileName); exitWithError("no register info for target " + TripleName, FileName);
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
AsmInfo.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); AsmInfo.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!AsmInfo) if (!AsmInfo)
exitWithError("no assembly info for target " + TripleName, FileName); exitWithError("no assembly info for target " + TripleName, FileName);
Expected<SubtargetFeatures> Features = Obj->getFeatures(); Expected<SubtargetFeatures> Features = Obj->getFeatures();
if (!Features) if (!Features)
exitWithError(Features.takeError(), FileName); exitWithError(Features.takeError(), FileName);
STI.reset( STI.reset(
TheTarget->createMCSubtargetInfo(TripleName, "", Features->getString())); TheTarget->createMCSubtargetInfo(TripleName, "", Features->getString()));
if (!STI) if (!STI)
exitWithError("no subtarget info for target " + TripleName, FileName); exitWithError("no subtarget info for target " + TripleName, FileName);
MII.reset(TheTarget->createMCInstrInfo()); MII.reset(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
exitWithError("no instruction info for target " + TripleName, FileName); exitWithError("no instruction info for target " + TripleName, FileName);
MCContext Ctx(Triple(TripleName), AsmInfo.get(), MRI.get(), STI.get()); MCContext Ctx(Triple(TripleName), AsmInfo.get(), MCRI.get(), STI.get());
std::unique_ptr<MCObjectFileInfo> MOFI( std::unique_ptr<MCObjectFileInfo> MOFI(
TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false)); TheTarget->createMCObjectFileInfo(Ctx, /*PIC=*/false));
Ctx.setObjectFileInfo(MOFI.get()); Ctx.setObjectFileInfo(MOFI.get());
DisAsm.reset(TheTarget->createMCDisassembler(*STI, Ctx)); DisAsm.reset(TheTarget->createMCDisassembler(*STI, Ctx));
if (!DisAsm) if (!DisAsm)
exitWithError("no disassembler for target " + TripleName, FileName); exitWithError("no disassembler for target " + TripleName, FileName);
MIA.reset(TheTarget->createMCInstrAnalysis(MII.get())); MIA.reset(TheTarget->createMCInstrAnalysis(MII.get()));
int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
IPrinter.reset(TheTarget->createMCInstPrinter( IPrinter.reset(TheTarget->createMCInstPrinter(
Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MCRI));
IPrinter->setPrintBranchImmAsAddress(true); IPrinter->setPrintBranchImmAsAddress(true);
} }
void ProfiledBinary::disassemble(const ELFObjectFileBase *Obj) { void ProfiledBinary::disassemble(const ELFObjectFileBase *Obj) {
// Set up disassembler and related components. // Set up disassembler and related components.
setUpDisassembler(Obj); setUpDisassembler(Obj);
// Create a mapping from virtual address to symbol name. The symbols in text // Create a mapping from virtual address to symbol name. The symbols in text
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llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp

Show First 20 Lines • Show All 791 Lines • ▼ Show 20 Linesstatic int linkAndVerify() {
TripleName = TheTriple.getTriple(); TripleName = TheTriple.getTriple();
std::unique_ptr<MCSubtargetInfo> STI( std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, MCPU, "")); TheTarget->createMCSubtargetInfo(TripleName, MCPU, ""));
if (!STI) if (!STI)
ErrorAndExit("Unable to create subtarget info!"); ErrorAndExit("Unable to create subtarget info!");
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); std::unique_ptr<MCRegisterInfo> MCRI(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
ErrorAndExit("Unable to create target register info!"); ErrorAndExit("Unable to create target register info!");
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<MCAsmInfo> MAI( std::unique_ptr<MCAsmInfo> MAI(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) if (!MAI)
ErrorAndExit("Unable to create target asm info!"); ErrorAndExit("Unable to create target asm info!");
MCContext Ctx(Triple(TripleName), MAI.get(), MRI.get(), STI.get()); MCContext Ctx(Triple(TripleName), MAI.get(), MCRI.get(), STI.get());
std::unique_ptr<MCDisassembler> Disassembler( std::unique_ptr<MCDisassembler> Disassembler(
TheTarget->createMCDisassembler(*STI, Ctx)); TheTarget->createMCDisassembler(*STI, Ctx));
if (!Disassembler) if (!Disassembler)
ErrorAndExit("Unable to create disassembler!"); ErrorAndExit("Unable to create disassembler!");
std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<MCInstrInfo> MII(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
ErrorAndExit("Unable to create target instruction info!"); ErrorAndExit("Unable to create target instruction info!");
std::unique_ptr<MCInstPrinter> InstPrinter( std::unique_ptr<MCInstPrinter> InstPrinter(
TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI)); TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MCRI));
// Load any dylibs requested on the command line. // Load any dylibs requested on the command line.
loadDylibs(); loadDylibs();
// Instantiate a dynamic linker. // Instantiate a dynamic linker.
TrivialMemoryManager MemMgr; TrivialMemoryManager MemMgr;
doPreallocation(MemMgr); doPreallocation(MemMgr);
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llvm/tools/sancov/sancov.cpp

Show First 20 Lines • Show All 723 Lines • ▼ Show 20 Linesstatic void getObjectCoveragePoints(const object::ObjectFile &O,
std::string Error; std::string Error;
const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error); const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error);
failIfNotEmpty(Error); failIfNotEmpty(Error);
std::unique_ptr<const MCSubtargetInfo> STI( std::unique_ptr<const MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, "", "")); TheTarget->createMCSubtargetInfo(TripleName, "", ""));
failIfEmpty(STI, "no subtarget info for target " + TripleName); failIfEmpty(STI, "no subtarget info for target " + TripleName);
std::unique_ptr<const MCRegisterInfo> MRI( std::unique_ptr<const MCRegisterInfo> MCRI(
TheTarget->createMCRegInfo(TripleName)); TheTarget->createMCRegInfo(TripleName));
failIfEmpty(MRI, "no register info for target " + TripleName); failIfEmpty(MCRI, "no register info for target " + TripleName);
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
std::unique_ptr<const MCAsmInfo> AsmInfo( std::unique_ptr<const MCAsmInfo> AsmInfo(
TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
failIfEmpty(AsmInfo, "no asm info for target " + TripleName); failIfEmpty(AsmInfo, "no asm info for target " + TripleName);
MCContext Ctx(TheTriple, AsmInfo.get(), MRI.get(), STI.get()); MCContext Ctx(TheTriple, AsmInfo.get(), MCRI.get(), STI.get());
std::unique_ptr<MCDisassembler> DisAsm( std::unique_ptr<MCDisassembler> DisAsm(
TheTarget->createMCDisassembler(*STI, Ctx)); TheTarget->createMCDisassembler(*STI, Ctx));
failIfEmpty(DisAsm, "no disassembler info for target " + TripleName); failIfEmpty(DisAsm, "no disassembler info for target " + TripleName);
std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo()); std::unique_ptr<const MCInstrInfo> MII(TheTarget->createMCInstrInfo());
failIfEmpty(MII, "no instruction info for target " + TripleName); failIfEmpty(MII, "no instruction info for target " + TripleName);
std::unique_ptr<const MCInstrAnalysis> MIA( std::unique_ptr<const MCInstrAnalysis> MIA(
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llvm/unittests/DebugInfo/DWARF/DWARFExpressionCompactPrinterTest.cpp

Show All 19 Lines
#include "gtest/gtest.h" #include "gtest/gtest.h"
using namespace llvm; using namespace llvm;
using namespace dwarf; using namespace dwarf;
namespace { namespace {
class DWARFExpressionCompactPrinterTest : public ::testing::Test { class DWARFExpressionCompactPrinterTest : public ::testing::Test {
public: public:
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
DWARFExpressionCompactPrinterTest() { DWARFExpressionCompactPrinterTest() {
InitializeAllTargets(); InitializeAllTargets();
InitializeAllTargetMCs(); InitializeAllTargetMCs();
InitializeAllAsmPrinters(); InitializeAllAsmPrinters();
std::string TripleName = "armv8a-linux-gnueabi"; std::string TripleName = "armv8a-linux-gnueabi";
std::string ErrorStr; std::string ErrorStr;
const Target *TheTarget = const Target *TheTarget =
TargetRegistry::lookupTarget(TripleName, ErrorStr); TargetRegistry::lookupTarget(TripleName, ErrorStr);
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
} }
void TestExprPrinter(ArrayRef<uint8_t> ExprData, StringRef Expected); void TestExprPrinter(ArrayRef<uint8_t> ExprData, StringRef Expected);
}; };
} // namespace } // namespace
void DWARFExpressionCompactPrinterTest::TestExprPrinter( void DWARFExpressionCompactPrinterTest::TestExprPrinter(
ArrayRef<uint8_t> ExprData, StringRef Expected) { ArrayRef<uint8_t> ExprData, StringRef Expected) {
// If we didn't build ARM, do not run the test. // If we didn't build ARM, do not run the test.
if (!MRI) if (!MCRI)
GTEST_SKIP(); GTEST_SKIP();
// Print the expression, passing in the subprogram DIE, and check that the // Print the expression, passing in the subprogram DIE, and check that the
// result is as expected. // result is as expected.
std::string Result; std::string Result;
raw_string_ostream OS(Result); raw_string_ostream OS(Result);
DataExtractor DE(ExprData, true, 8); DataExtractor DE(ExprData, true, 8);
DWARFExpression Expr(DE, 8); DWARFExpression Expr(DE, 8);
auto GetRegName = [&](uint64_t DwarfRegNum, bool IsEH) -> StringRef { auto GetRegName = [&](uint64_t DwarfRegNum, bool IsEH) -> StringRef {
if (std::optional<unsigned> LLVMRegNum = if (std::optional<unsigned> LLVMRegNum =
this->MRI->getLLVMRegNum(DwarfRegNum, IsEH)) this->MCRI->getLLVMRegNum(DwarfRegNum, IsEH))
if (const char *RegName = this->MRI->getName(*LLVMRegNum)) if (const char *RegName = this->MCRI->getName(*LLVMRegNum))
return llvm::StringRef(RegName); return llvm::StringRef(RegName);
OS << "<unknown register " << DwarfRegNum << ">"; OS << "<unknown register " << DwarfRegNum << ">";
return {}; return {};
}; };
Expr.printCompact(OS, GetRegName); Expr.printCompact(OS, GetRegName);
EXPECT_EQ(OS.str(), Expected); EXPECT_EQ(OS.str(), Expected);
} }
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llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp

Show All 40 Lines
/// Tests that a client of DebugInfo/DWARF is able to read raw data bytes of a /// Tests that a client of DebugInfo/DWARF is able to read raw data bytes of a
/// DWARFExpression parsed from CFI with the intent of writing them back as is /// DWARFExpression parsed from CFI with the intent of writing them back as is
/// via MC layer / cfi_escape. /// via MC layer / cfi_escape.
/// This is relevant for binary tools that need to rewrite/copy unwind and /// This is relevant for binary tools that need to rewrite/copy unwind and
/// debug info from input to output binary. /// debug info from input to output binary.
class DWARFExpressionCopyBytesTest : public ::testing::Test { class DWARFExpressionCopyBytesTest : public ::testing::Test {
public: public:
const char *TripleName = "x86_64-pc-linux"; const char *TripleName = "x86_64-pc-linux";
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<const MCSubtargetInfo> STI; std::unique_ptr<const MCSubtargetInfo> STI;
const Target *TheTarget; const Target *TheTarget;
DWARFExpressionCopyBytesTest() { DWARFExpressionCopyBytesTest() {
InitializeAllTargets(); InitializeAllTargets();
InitializeAllTargetMCs(); InitializeAllTargetMCs();
InitializeAllAsmPrinters(); InitializeAllAsmPrinters();
std::string ErrorStr; std::string ErrorStr;
TheTarget = TargetRegistry::lookupTarget(TripleName, ErrorStr); TheTarget = TargetRegistry::lookupTarget(TripleName, ErrorStr);
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCTargetOptions())); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCTargetOptions()));
STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
} }
struct StreamerContext { struct StreamerContext {
std::unique_ptr<MCObjectFileInfo> MOFI; std::unique_ptr<MCObjectFileInfo> MOFI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<MCStreamer> Streamer; std::unique_ptr<MCStreamer> Streamer;
Show All 20 Lines
}; };
} // namespace } // namespace
DWARFExpressionCopyBytesTest::StreamerContext DWARFExpressionCopyBytesTest::StreamerContext
DWARFExpressionCopyBytesTest::createStreamer(raw_pwrite_stream &OS) { DWARFExpressionCopyBytesTest::createStreamer(raw_pwrite_stream &OS) {
StreamerContext Res; StreamerContext Res;
Res.Ctx = Res.Ctx =
std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MRI.get(), std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MCRI.get(),
/*MSTI=*/nullptr); /*MSTI=*/nullptr);
Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(), Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(),
/*PIC=*/false)); /*PIC=*/false));
Res.Ctx->setObjectFileInfo(Res.MOFI.get()); Res.Ctx->setObjectFileInfo(Res.MOFI.get());
Res.MII.reset(TheTarget->createMCInstrInfo()); Res.MII.reset(TheTarget->createMCInstrInfo());
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
MCAsmBackend *MAB = MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions()); TheTarget->createMCAsmBackend(*STI, *MCRI, MCTargetOptions());
std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS); std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS);
Res.Streamer.reset(TheTarget->createMCObjectStreamer( Res.Streamer.reset(TheTarget->createMCObjectStreamer(
Triple(TripleName), *Res.Ctx, std::unique_ptr<MCAsmBackend>(MAB), Triple(TripleName), *Res.Ctx, std::unique_ptr<MCAsmBackend>(MAB),
std::move(OW), std::unique_ptr<MCCodeEmitter>(MCE), *STI, std::move(OW), std::unique_ptr<MCCodeEmitter>(MCE), *STI,
/* RelaxAll */ false, /* RelaxAll */ false,
/* IncrementalLinkerCompatible */ false, /* IncrementalLinkerCompatible */ false,
/* DWARFMustBeAtTheEnd */ false)); /* DWARFMustBeAtTheEnd */ false));
return Res; return Res;
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines std::unique_ptr<object::Binary> Bin =
cantFail(llvm::object::createBinary(MB->getMemBufferRef())); cantFail(llvm::object::createBinary(MB->getMemBufferRef()));
if (auto *E = dyn_cast<llvm::object::ELFObjectFileBase>(&*Bin)) { if (auto *E = dyn_cast<llvm::object::ELFObjectFileBase>(&*Bin)) {
parseCFIsAndCheckExpression(*E, Expected); parseCFIsAndCheckExpression(*E, Expected);
} }
} }
void DWARFExpressionCopyBytesTest::testExpr(ArrayRef<uint8_t> ExprData) { void DWARFExpressionCopyBytesTest::testExpr(ArrayRef<uint8_t> ExprData) {
// If we didn't build x86, do not run the test. // If we didn't build x86, do not run the test.
if (!MRI) if (!MCRI)
GTEST_SKIP(); GTEST_SKIP();
DataExtractor DE(ExprData, true, 8); DataExtractor DE(ExprData, true, 8);
DWARFExpression Expr(DE, 8); DWARFExpression Expr(DE, 8);
// Copy this expression into the CFI of a binary and check that we are able to // Copy this expression into the CFI of a binary and check that we are able to
// get it back correctly from this binary. // get it back correctly from this binary.
const SmallString<0> EmittedBinContents = emitObjFile(Expr.getData()); const SmallString<0> EmittedBinContents = emitObjFile(Expr.getData());
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llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h

Show First 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
}; };
/// A DWARF generator. /// A DWARF generator.
/// ///
/// Generate DWARF for unit tests by creating any instance of this class and /// Generate DWARF for unit tests by creating any instance of this class and
/// calling Generator::addCompileUnit(), and then getting the dwarfgen::DIE from /// calling Generator::addCompileUnit(), and then getting the dwarfgen::DIE from
/// the returned compile unit and adding attributes and children to each DIE. /// the returned compile unit and adding attributes and children to each DIE.
class Generator { class Generator {
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCContext> MC; std::unique_ptr<MCContext> MC;
MCAsmBackend *MAB; // Owned by MCStreamer MCAsmBackend *MAB; // Owned by MCStreamer
std::unique_ptr<MCInstrInfo> MII; std::unique_ptr<MCInstrInfo> MII;
std::unique_ptr<MCSubtargetInfo> MSTI; std::unique_ptr<MCSubtargetInfo> MSTI;
MCCodeEmitter *MCE; // Owned by MCStreamer MCCodeEmitter *MCE; // Owned by MCStreamer
MCStreamer *MS; // Owned by AsmPrinter MCStreamer *MS; // Owned by AsmPrinter
std::unique_ptr<TargetMachine> TM; std::unique_ptr<TargetMachine> TM;
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp

Show First 20 Lines • Show All 419 Lines • ▼ Show 20 Linesllvm::Error dwarfgen::Generator::init(Triple TheTriple, uint16_t V) {
const Target *TheTarget = const Target *TheTarget =
TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr); TargetRegistry::lookupTarget(TripleName, TheTriple, ErrorStr);
if (!TheTarget) if (!TheTarget)
return make_error<StringError>(ErrorStr, inconvertibleErrorCode()); return make_error<StringError>(ErrorStr, inconvertibleErrorCode());
TripleName = TheTriple.getTriple(); TripleName = TheTriple.getTriple();
// Create all the MC Objects. // Create all the MC Objects.
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
if (!MRI) if (!MCRI)
return make_error<StringError>(Twine("no register info for target ") + return make_error<StringError>(Twine("no register info for target ") +
TripleName, TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags();
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
if (!MAI) if (!MAI)
return make_error<StringError>("no asm info for target " + TripleName, return make_error<StringError>("no asm info for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI) if (!MSTI)
return make_error<StringError>("no subtarget info for target " + TripleName, return make_error<StringError>("no subtarget info for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions); MAB = TheTarget->createMCAsmBackend(*MSTI, *MCRI, MCOptions);
if (!MAB) if (!MAB)
return make_error<StringError>("no asm backend for target " + TripleName, return make_error<StringError>("no asm backend for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MII.reset(TheTarget->createMCInstrInfo()); MII.reset(TheTarget->createMCInstrInfo());
if (!MII) if (!MII)
return make_error<StringError>("no instr info info for target " + return make_error<StringError>("no instr info info for target " +
TripleName, TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions(), TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions(),
std::nullopt)); std::nullopt));
if (!TM) if (!TM)
return make_error<StringError>("no target machine for target " + TripleName, return make_error<StringError>("no target machine for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MC.reset(new MCContext(TheTriple, MAI.get(), MRI.get(), MSTI.get())); MC.reset(new MCContext(TheTriple, MAI.get(), MCRI.get(), MSTI.get()));
TLOF = TM->getObjFileLowering(); TLOF = TM->getObjFileLowering();
TLOF->Initialize(*MC, *TM); TLOF->Initialize(*MC, *TM);
MC->setObjectFileInfo(TLOF); MC->setObjectFileInfo(TLOF);
MCE = TheTarget->createMCCodeEmitter(*MII, *MC); MCE = TheTarget->createMCCodeEmitter(*MII, *MC);
if (!MCE) if (!MCE)
return make_error<StringError>("no code emitter for target " + TripleName, return make_error<StringError>("no code emitter for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
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llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines return std::unique_ptr<LLVMTargetMachine>(
TStr, CPU, FS, Options, std::nullopt, std::nullopt))); TStr, CPU, FS, Options, std::nullopt, std::nullopt)));
} }
TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) { TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
for (auto Triple : for (auto Triple :
{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64"); auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
if (TM && TM->getMCRegisterInfo()) { if (TM && TM->getMCRegisterInfo()) {
auto MRI = TM->getMCRegisterInfo(); auto MCRI = TM->getMCRegisterInfo();
// Wave64 Dwarf register mapping test numbers // Wave64 Dwarf register mapping test numbers
// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95, // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815, // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
// A0 => 3072, A255 => 3327 // A0 => 3072, A255 => 3327
for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) { for (int llvmReg : {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); MCRegister PCReg(*MCRI->getLLVMRegNum(llvmReg, false));
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); EXPECT_EQ(llvmReg, MCRI->getDwarfRegNum(PCReg, false));
} }
} }
} }
} }
TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) { TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
for (auto Triple : for (auto Triple :
{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) { {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32"); auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
if (TM && TM->getMCRegisterInfo()) { if (TM && TM->getMCRegisterInfo()) {
auto MRI = TM->getMCRegisterInfo(); auto MCRI = TM->getMCRegisterInfo();
// Wave32 Dwarf register mapping test numbers // Wave32 Dwarf register mapping test numbers
// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95, // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791, // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
// A0 => 2048, A255 => 2303 // A0 => 2048, A255 => 2303
for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) { for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false)); MCRegister PCReg(*MCRI->getLLVMRegNum(llvmReg, false));
EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false)); EXPECT_EQ(llvmReg, MCRI->getDwarfRegNum(PCReg, false));
} }
} }
} }
} }

llvm/unittests/MC/DwarfLineTableHeaders.cpp

Show All 31 Lines
using namespace llvm; using namespace llvm;
namespace { namespace {
class DwarfLineTableHeaders : public ::testing::Test { class DwarfLineTableHeaders : public ::testing::Test {
public: public:
const char *TripleName = "x86_64-pc-linux"; const char *TripleName = "x86_64-pc-linux";
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<const MCSubtargetInfo> STI; std::unique_ptr<const MCSubtargetInfo> STI;
const Target *TheTarget; const Target *TheTarget;
struct StreamerContext { struct StreamerContext {
std::unique_ptr<MCObjectFileInfo> MOFI; std::unique_ptr<MCObjectFileInfo> MOFI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<MCStreamer> Streamer; std::unique_ptr<MCStreamer> Streamer;
}; };
DwarfLineTableHeaders() { DwarfLineTableHeaders() {
llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetInfos();
llvm::InitializeAllTargetMCs(); llvm::InitializeAllTargetMCs();
llvm::InitializeAllDisassemblers(); llvm::InitializeAllDisassemblers();
// If we didn't build x86, do not run the test. // If we didn't build x86, do not run the test.
std::string Error; std::string Error;
TheTarget = TargetRegistry::lookupTarget(TripleName, Error); TheTarget = TargetRegistry::lookupTarget(TripleName, Error);
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
} }
/// Create all data structures necessary to operate an assembler /// Create all data structures necessary to operate an assembler
StreamerContext createStreamer(raw_pwrite_stream &OS) { StreamerContext createStreamer(raw_pwrite_stream &OS) {
StreamerContext Res; StreamerContext Res;
Res.Ctx = Res.Ctx =
std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MRI.get(), std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MCRI.get(),
/*MSTI=*/nullptr); /*MSTI=*/nullptr);
Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(), Res.MOFI.reset(TheTarget->createMCObjectFileInfo(*Res.Ctx.get(),
/*PIC=*/false)); /*PIC=*/false));
Res.Ctx->setObjectFileInfo(Res.MOFI.get()); Res.Ctx->setObjectFileInfo(Res.MOFI.get());
Res.MII.reset(TheTarget->createMCInstrInfo()); Res.MII.reset(TheTarget->createMCInstrInfo());
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*Res.MII, *Res.Ctx);
MCAsmBackend *MAB = MCAsmBackend *MAB =
TheTarget->createMCAsmBackend(*STI, *MRI, MCTargetOptions()); TheTarget->createMCAsmBackend(*STI, *MCRI, MCTargetOptions());
std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS); std::unique_ptr<MCObjectWriter> OW = MAB->createObjectWriter(OS);
Res.Streamer.reset(TheTarget->createMCObjectStreamer( Res.Streamer.reset(TheTarget->createMCObjectStreamer(
Triple(TripleName), *Res.Ctx, std::unique_ptr<MCAsmBackend>(MAB), Triple(TripleName), *Res.Ctx, std::unique_ptr<MCAsmBackend>(MAB),
std::move(OW), std::unique_ptr<MCCodeEmitter>(MCE), *STI, std::move(OW), std::unique_ptr<MCCodeEmitter>(MCE), *STI,
/* RelaxAll */ false, /* RelaxAll */ false,
/* IncrementalLinkerCompatible */ false, /* IncrementalLinkerCompatible */ false,
/* DWARFMustBeAtTheEnd */ false)); /* DWARFMustBeAtTheEnd */ false));
return Res; return Res;
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines if (auto *E = dyn_cast<llvm::object::ELFObjectFileBase>(&*Bin)) {
return; return;
} }
llvm_unreachable("ELF object file not found"); llvm_unreachable("ELF object file not found");
} }
}; };
} // namespace } // namespace
TEST_F(DwarfLineTableHeaders, TestDWARF4HeaderEmission) { TEST_F(DwarfLineTableHeaders, TestDWARF4HeaderEmission) {
if (!MRI) if (!MCRI)
return; return;
SmallString<0> EmittedBinContents; SmallString<0> EmittedBinContents;
raw_svector_ostream VecOS(EmittedBinContents); raw_svector_ostream VecOS(EmittedBinContents);
StreamerContext C = createStreamer(VecOS); StreamerContext C = createStreamer(VecOS);
constexpr uint8_t DwarfVersion = 4; constexpr uint8_t DwarfVersion = 4;
C.Ctx->setDwarfVersion(DwarfVersion); C.Ctx->setDwarfVersion(DwarfVersion);
emitDebugLineSection(C); emitDebugLineSection(C);
C.Streamer->finish(); C.Streamer->finish();
readAndCheckDebugContents( readAndCheckDebugContents(
EmittedBinContents.str(), EmittedBinContents.str(),
{/* Total length=*/0x30, 0, 0, 0, {/* Total length=*/0x30, 0, 0, 0,
/* DWARF version=*/DwarfVersion, 0, /* DWARF version=*/DwarfVersion, 0,
/* Prologue length=*/0x14, 0, 0, 0, /* Prologue length=*/0x14, 0, 0, 0,
/* min_inst_length=*/1, /* min_inst_length=*/1,
/*max_ops_per_inst=*/1, /*max_ops_per_inst=*/1,
/* default_is_stmt=*/DWARF2_LINE_DEFAULT_IS_STMT, /* default_is_stmt=*/DWARF2_LINE_DEFAULT_IS_STMT,
/* line_base=*/static_cast<uint8_t>(-5), /* line_base=*/static_cast<uint8_t>(-5),
/* line_range=*/14, /* line_range=*/14,
/* opcode_base=*/13}, DwarfVersion); /* opcode_base=*/13}, DwarfVersion);
} }
TEST_F(DwarfLineTableHeaders, TestDWARF5HeaderEmission) { TEST_F(DwarfLineTableHeaders, TestDWARF5HeaderEmission) {
if (!MRI) if (!MCRI)
return; return;
SmallString<0> EmittedBinContents; SmallString<0> EmittedBinContents;
raw_svector_ostream VecOS(EmittedBinContents); raw_svector_ostream VecOS(EmittedBinContents);
StreamerContext C = createStreamer(VecOS); StreamerContext C = createStreamer(VecOS);
constexpr uint8_t DwarfVersion = 5; constexpr uint8_t DwarfVersion = 5;
C.Ctx->setDwarfVersion(DwarfVersion); C.Ctx->setDwarfVersion(DwarfVersion);
emitDebugLineSection(C); emitDebugLineSection(C);
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llvm/unittests/MC/DwarfLineTables.cpp

Show All 16 Lines
#include "llvm/Support/TargetSelect.h" #include "llvm/Support/TargetSelect.h"
#include "gtest/gtest.h" #include "gtest/gtest.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
struct Context { struct Context {
const char *TripleName = "x86_64-pc-linux"; const char *TripleName = "x86_64-pc-linux";
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
Context() { Context() {
llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetInfos();
llvm::InitializeAllTargetMCs(); llvm::InitializeAllTargetMCs();
llvm::InitializeAllDisassemblers(); llvm::InitializeAllDisassemblers();
// If we didn't build x86, do not run the test. // If we didn't build x86, do not run the test.
std::string Error; std::string Error;
const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error); const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error);
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MRI.get(), Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MCRI.get(),
/*MSTI=*/nullptr); /*MSTI=*/nullptr);
} }
operator bool() { return Ctx.get(); } operator bool() { return Ctx.get(); }
operator MCContext &() { return *Ctx; }; operator MCContext &() { return *Ctx; };
}; };
Context &getContext() { Context &getContext() {
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/unittests/MC/MCInstPrinter.cpp

Show All 16 Lines
#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetOptions.h"
#include "gtest/gtest.h" #include "gtest/gtest.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
class MCInstPrinterTest : public ::testing::Test { class MCInstPrinterTest : public ::testing::Test {
public: public:
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<MCInstPrinter> Printer; std::unique_ptr<MCInstPrinter> Printer;
MCInstPrinterTest() { MCInstPrinterTest() {
llvm::InitializeAllTargetInfos(); llvm::InitializeAllTargetInfos();
llvm::InitializeAllTargetMCs(); llvm::InitializeAllTargetMCs();
std::string TripleName = "x86_64-pc-linux"; std::string TripleName = "x86_64-pc-linux";
std::string ErrorStr; std::string ErrorStr;
const Target *TheTarget = const Target *TheTarget =
TargetRegistry::lookupTarget(TripleName, ErrorStr); TargetRegistry::lookupTarget(TripleName, ErrorStr);
// If we didn't build x86, do not run the test. // If we didn't build x86, do not run the test.
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
MCTargetOptions MCOptions; MCTargetOptions MCOptions;
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
MII.reset(TheTarget->createMCInstrInfo()); MII.reset(TheTarget->createMCInstrInfo());
Printer.reset(TheTarget->createMCInstPrinter( Printer.reset(TheTarget->createMCInstPrinter(
Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI)); Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MCRI));
} }
template <typename T> std::string formatHex(T i) { template <typename T> std::string formatHex(T i) {
std::string Buffer; std::string Buffer;
raw_string_ostream OS(Buffer); raw_string_ostream OS(Buffer);
OS << Printer->formatHex(i); OS << Printer->formatHex(i);
OS.flush(); OS.flush();
return Buffer; return Buffer;
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llvm/unittests/MC/SystemZ/SystemZAsmLexerTest.cpp

Show All 29 Lines
class SystemZAsmLexerTest : public ::testing::Test { class SystemZAsmLexerTest : public ::testing::Test {
protected: protected:
static void SetUpTestCase() { static void SetUpTestCase() {
LLVMInitializeSystemZTargetInfo(); LLVMInitializeSystemZTargetInfo();
LLVMInitializeSystemZTargetMC(); LLVMInitializeSystemZTargetMC();
LLVMInitializeSystemZAsmParser(); LLVMInitializeSystemZAsmParser();
} }
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<const MCInstrInfo> MII; std::unique_ptr<const MCInstrInfo> MII;
std::unique_ptr<MCObjectFileInfo> MOFI; std::unique_ptr<MCObjectFileInfo> MOFI;
std::unique_ptr<MCStreamer> Str; std::unique_ptr<MCStreamer> Str;
std::unique_ptr<MCAsmParser> Parser; std::unique_ptr<MCAsmParser> Parser;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<MCSubtargetInfo> STI; std::unique_ptr<MCSubtargetInfo> STI;
std::unique_ptr<MCTargetAsmParser> TargetAsmParser; std::unique_ptr<MCTargetAsmParser> TargetAsmParser;
Show All 12 Lines SystemZAsmLexerTest(std::string SystemZTriple) {
// Object File and Streamer support for the z/OS target. // Object File and Streamer support for the z/OS target.
TripleName = SystemZTriple; TripleName = SystemZTriple;
Triple = llvm::Triple(TripleName); Triple = llvm::Triple(TripleName);
std::string Error; std::string Error;
TheTarget = TargetRegistry::lookupTarget(TripleName, Error); TheTarget = TargetRegistry::lookupTarget(TripleName, Error);
EXPECT_NE(TheTarget, nullptr); EXPECT_NE(TheTarget, nullptr);
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
EXPECT_NE(MRI, nullptr); EXPECT_NE(MCRI, nullptr);
MII.reset(TheTarget->createMCInstrInfo()); MII.reset(TheTarget->createMCInstrInfo());
EXPECT_NE(MII, nullptr); EXPECT_NE(MII, nullptr);
STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "z10", "")); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "z10", ""));
EXPECT_NE(STI, nullptr); EXPECT_NE(STI, nullptr);
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
EXPECT_NE(MAI, nullptr); EXPECT_NE(MAI, nullptr);
} }
void setupCallToAsmParser(StringRef AsmStr) { void setupCallToAsmParser(StringRef AsmStr) {
std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(AsmStr)); std::unique_ptr<MemoryBuffer> Buffer(MemoryBuffer::getMemBuffer(AsmStr));
SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc()); SrcMgr.AddNewSourceBuffer(std::move(Buffer), SMLoc());
EXPECT_EQ(Buffer, nullptr); EXPECT_EQ(Buffer, nullptr);
Ctx.reset(new MCContext(Triple, MAI.get(), MRI.get(), STI.get(), &SrcMgr, Ctx.reset(new MCContext(Triple, MAI.get(), MCRI.get(), STI.get(), &SrcMgr,
&MCOptions)); &MCOptions));
MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false, MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false,
/*LargeCodeModel=*/false)); /*LargeCodeModel=*/false));
Ctx->setObjectFileInfo(MOFI.get()); Ctx->setObjectFileInfo(MOFI.get());
Str.reset(TheTarget->createNullStreamer(*Ctx)); Str.reset(TheTarget->createNullStreamer(*Ctx));
Parser.reset(createMCAsmParser(SrcMgr, *Ctx, *Str, *MAI)); Parser.reset(createMCAsmParser(SrcMgr, *Ctx, *Str, *MAI));
▲ Show 20 Lines • Show All 509 Lines • Show Last 20 Lines

llvm/unittests/MC/X86/X86MCDisassemblerTest.cpp

Show All 18 Lines
#include "gtest/gtest.h" #include "gtest/gtest.h"
using namespace llvm; using namespace llvm;
namespace { namespace {
struct Context { struct Context {
const char *TripleName = "x86_64-unknown-elf"; const char *TripleName = "x86_64-unknown-elf";
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<MCSubtargetInfo> STI; std::unique_ptr<MCSubtargetInfo> STI;
std::unique_ptr<MCDisassembler> DisAsm; std::unique_ptr<MCDisassembler> DisAsm;
Context() { Context() {
LLVMInitializeX86TargetInfo(); LLVMInitializeX86TargetInfo();
LLVMInitializeX86TargetMC(); LLVMInitializeX86TargetMC();
LLVMInitializeX86Disassembler(); LLVMInitializeX86Disassembler();
// If we didn't build x86, do not run the test. // If we didn't build x86, do not run the test.
std::string Error; std::string Error;
const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error); const Target *TheTarget = TargetRegistry::lookupTarget(TripleName, Error);
if (!TheTarget) if (!TheTarget)
return; return;
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCTargetOptions())); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCTargetOptions()));
STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MRI.get(), Ctx = std::make_unique<MCContext>(Triple(TripleName), MAI.get(), MCRI.get(),
STI.get()); STI.get());
DisAsm.reset(TheTarget->createMCDisassembler(*STI, *Ctx)); DisAsm.reset(TheTarget->createMCDisassembler(*STI, *Ctx));
} }
operator MCContext &() { return *Ctx; }; operator MCContext &() { return *Ctx; };
}; };
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/unittests/Target/AArch64/AArch64InstPrinterTest.cpp

Show All 18 Lines
#include "gtest/gtest.h" #include "gtest/gtest.h"
using namespace llvm; using namespace llvm;
class AArch64InstPrinterTest : public AArch64InstPrinter { class AArch64InstPrinterTest : public AArch64InstPrinter {
public: public:
AArch64InstPrinterTest(const MCAsmInfo &MAI, const MCInstrInfo &MII, AArch64InstPrinterTest(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI) const MCRegisterInfo &MCRI)
: AArch64InstPrinter(MAI, MII, MRI) {} : AArch64InstPrinter(MAI, MII, MCRI) {}
void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum, void printAlignedLabel(const MCInst *MI, uint64_t Address, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O) { const MCSubtargetInfo &STI, raw_ostream &O) {
AArch64InstPrinter::printAlignedLabel(MI, Address, OpNum, STI, O); AArch64InstPrinter::printAlignedLabel(MI, Address, OpNum, STI, O);
} }
}; };
static std::string AArch64InstPrinterTestPrintAlignedLabel(uint64_t value) { static std::string AArch64InstPrinterTestPrintAlignedLabel(uint64_t value) {
MCAsmInfo MAI; MCAsmInfo MAI;
MCInstrInfo MII; MCInstrInfo MII;
MCRegisterInfo MRI; MCRegisterInfo MCRI;
MCSubtargetInfo STI(Triple(""), "", "", "", MCSubtargetInfo STI(Triple(""), "", "", "",
ArrayRef((SubtargetFeatureKV *)NULL, (size_t)0), ArrayRef((SubtargetFeatureKV *)NULL, (size_t)0),
ArrayRef((SubtargetSubTypeKV *)NULL, (size_t)0), NULL, ArrayRef((SubtargetSubTypeKV *)NULL, (size_t)0), NULL,
NULL, NULL, NULL, NULL, NULL); NULL, NULL, NULL, NULL, NULL);
MCContext Ctx(Triple(""), &MAI, &MRI, &STI); MCContext Ctx(Triple(""), &MAI, &MCRI, &STI);
MCInst MI; MCInst MI;
MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(value, Ctx))); MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(value, Ctx)));
std::string str; std::string str;
raw_string_ostream O(str); raw_string_ostream O(str);
AArch64InstPrinterTest(MAI, MII, MRI).printAlignedLabel(&MI, 0, 0, STI, O); AArch64InstPrinterTest(MAI, MII, MCRI).printAlignedLabel(&MI, 0, 0, STI, O);
return str; return str;
} }
TEST(AArch64InstPrinterTest, PrintAlignedLabel) { TEST(AArch64InstPrinterTest, PrintAlignedLabel) {
EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0x0), "0x0"); EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0x0), "0x0");
EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0xffffffff001200eb), EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0xffffffff001200eb),
"0xffffffff001200eb"); "0xffffffff001200eb");
EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0x7c01445bcc10f), EXPECT_EQ(AArch64InstPrinterTestPrintAlignedLabel(0x7c01445bcc10f),
"0x7c01445bcc10f"); "0x7c01445bcc10f");
} }

llvm/unittests/tools/llvm-mca/MCATestBase.h

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesprotected:
const Target *TheTarget; const Target *TheTarget;
const Triple TheTriple; const Triple TheTriple;
StringRef CPUName; StringRef CPUName;
StringRef MAttr; StringRef MAttr;
// MC components. // MC components.
std::unique_ptr<MCSubtargetInfo> STI; std::unique_ptr<MCSubtargetInfo> STI;
std::unique_ptr<MCRegisterInfo> MRI; std::unique_ptr<MCRegisterInfo> MCRI;
std::unique_ptr<MCAsmInfo> MAI; std::unique_ptr<MCAsmInfo> MAI;
std::unique_ptr<MCObjectFileInfo> MOFI; std::unique_ptr<MCObjectFileInfo> MOFI;
std::unique_ptr<MCContext> Ctx; std::unique_ptr<MCContext> Ctx;
std::unique_ptr<MCInstrInfo> MCII; std::unique_ptr<MCInstrInfo> MCII;
std::unique_ptr<MCInstrAnalysis> MCIA; std::unique_ptr<MCInstrAnalysis> MCIA;
std::unique_ptr<MCInstPrinter> IP; std::unique_ptr<MCInstPrinter> IP;
static mca::PipelineOptions getDefaultPipelineOptions(); static mca::PipelineOptions getDefaultPipelineOptions();
Show All 14 Lines

llvm/unittests/tools/llvm-mca/MCATestBase.cpp

Show All 31 Linesvoid MCATestBase::SetUp() {
ASSERT_NE(TheTarget, nullptr); ASSERT_NE(TheTarget, nullptr);
StringRef TripleName = TheTriple.getTriple(); StringRef TripleName = TheTriple.getTriple();
STI.reset(TheTarget->createMCSubtargetInfo(TripleName, CPUName, MAttr)); STI.reset(TheTarget->createMCSubtargetInfo(TripleName, CPUName, MAttr));
ASSERT_TRUE(STI); ASSERT_TRUE(STI);
ASSERT_TRUE(STI->isCPUStringValid(CPUName)); ASSERT_TRUE(STI->isCPUStringValid(CPUName));
MRI.reset(TheTarget->createMCRegInfo(TripleName)); MCRI.reset(TheTarget->createMCRegInfo(TripleName));
ASSERT_TRUE(MRI); ASSERT_TRUE(MCRI);
auto MCOptions = getMCTargetOptions(); auto MCOptions = getMCTargetOptions();
MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions)); MAI.reset(TheTarget->createMCAsmInfo(*MCRI, TripleName, MCOptions));
ASSERT_TRUE(MAI); ASSERT_TRUE(MAI);
Ctx = std::make_unique<MCContext>(TheTriple, MAI.get(), MRI.get(), STI.get()); Ctx =
std::make_unique<MCContext>(TheTriple, MAI.get(), MCRI.get(), STI.get());
MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false)); MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false));
Ctx->setObjectFileInfo(MOFI.get()); Ctx->setObjectFileInfo(MOFI.get());
MCII.reset(TheTarget->createMCInstrInfo()); MCII.reset(TheTarget->createMCInstrInfo());
ASSERT_TRUE(MCII); ASSERT_TRUE(MCII);
MCIA.reset(TheTarget->createMCInstrAnalysis(MCII.get())); MCIA.reset(TheTarget->createMCInstrAnalysis(MCII.get()));
ASSERT_TRUE(MCIA); ASSERT_TRUE(MCIA);
IP.reset(TheTarget->createMCInstPrinter(TheTriple, /*AssemblerDialect=*/0, IP.reset(TheTarget->createMCInstPrinter(TheTriple, /*AssemblerDialect=*/0,
*MAI, *MCII, *MRI)); *MAI, *MCII, *MCRI));
ASSERT_TRUE(IP); ASSERT_TRUE(IP);
} }
Error MCATestBase::runBaselineMCA(json::Object &Result, ArrayRef<MCInst> Insts, Error MCATestBase::runBaselineMCA(json::Object &Result, ArrayRef<MCInst> Insts,
ArrayRef<mca::View *> Views, ArrayRef<mca::View *> Views,
const mca::PipelineOptions *PO) { const mca::PipelineOptions *PO) {
mca::Context MCA(*MRI, *STI); mca::Context MCA(*MCRI, *STI);
// Default InstrumentManager // Default InstrumentManager
auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII);
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM);
const SmallVector<mca::SharedInstrument> Instruments; const SmallVector<mca::SharedInstrument> Instruments;
SmallVector<std::unique_ptr<mca::Instruction>> LoweredInsts; SmallVector<std::unique_ptr<mca::Instruction>> LoweredInsts;
for (const auto &MCI : Insts) { for (const auto &MCI : Insts) {
Expected<std::unique_ptr<mca::Instruction>> Inst = Expected<std::unique_ptr<mca::Instruction>> Inst =
IB.createInstruction(MCI, Instruments); IB.createInstruction(MCI, Instruments);
if (!Inst) { if (!Inst) {
if (auto NewE = if (auto NewE =
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llvm/unittests/tools/llvm-mca/X86/TestIncrementalMCA.cpp

#include "Views/SummaryView.h" #include "Views/SummaryView.h"
#include "X86TestBase.h" #include "X86TestBase.h"
#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallPtrSet.h"
#include "llvm/MCA/CustomBehaviour.h" #include "llvm/MCA/CustomBehaviour.h"
#include "llvm/MCA/IncrementalSourceMgr.h" #include "llvm/MCA/IncrementalSourceMgr.h"
#include "llvm/MCA/InstrBuilder.h" #include "llvm/MCA/InstrBuilder.h"
#include "llvm/MCA/Pipeline.h" #include "llvm/MCA/Pipeline.h"
#include "llvm/Support/Format.h" #include "llvm/Support/Format.h"
#include "llvm/Support/JSON.h" #include "llvm/Support/JSON.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include <unordered_map> #include <unordered_map>
using namespace llvm; using namespace llvm;
using namespace mca; using namespace mca;
TEST_F(X86TestBase, TestResumablePipeline) { TEST_F(X86TestBase, TestResumablePipeline) {
mca::Context MCA(*MRI, *STI); mca::Context MCA(*MCRI, *STI);
mca::IncrementalSourceMgr ISM; mca::IncrementalSourceMgr ISM;
// Empty CustomBehaviour. // Empty CustomBehaviour.
auto CB = std::make_unique<mca::CustomBehaviour>(*STI, ISM, *MCII); auto CB = std::make_unique<mca::CustomBehaviour>(*STI, ISM, *MCII);
auto PO = getDefaultPipelineOptions(); auto PO = getDefaultPipelineOptions();
auto P = MCA.createDefaultPipeline(PO, ISM, *CB); auto P = MCA.createDefaultPipeline(PO, ISM, *CB);
ASSERT_TRUE(P); ASSERT_TRUE(P);
SmallVector<MCInst> MCIs; SmallVector<MCInst> MCIs;
getSimpleInsts(MCIs, /*Repeats=*/100); getSimpleInsts(MCIs, /*Repeats=*/100);
// Add views. // Add views.
auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs, auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs,
PO.DispatchWidth); PO.DispatchWidth);
P->addEventListener(SV.get()); P->addEventListener(SV.get());
auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII);
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM);
const SmallVector<mca::SharedInstrument> Instruments; const SmallVector<mca::SharedInstrument> Instruments;
// Tile size = 7 // Tile size = 7
for (unsigned i = 0U, E = MCIs.size(); i < E;) { for (unsigned i = 0U, E = MCIs.size(); i < E;) {
for (unsigned TE = i + 7; i < TE && i < E; ++i) { for (unsigned TE = i + 7; i < TE && i < E; ++i) {
Expected<std::unique_ptr<mca::Instruction>> InstOrErr = Expected<std::unique_ptr<mca::Instruction>> InstOrErr =
IB.createInstruction(MCIs[i], Instruments); IB.createInstruction(MCIs[i], Instruments);
ASSERT_TRUE(bool(InstOrErr)); ASSERT_TRUE(bool(InstOrErr));
Show All 32 Lines for (const auto *F : Fields) {
auto V = ResultObj->getInteger(F); auto V = ResultObj->getInteger(F);
auto BV = BaselineObj->getInteger(F); auto BV = BaselineObj->getInteger(F);
ASSERT_TRUE(V && BV); ASSERT_TRUE(V && BV);
ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match"; ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match";
} }
} }
TEST_F(X86TestBase, TestInstructionRecycling) { TEST_F(X86TestBase, TestInstructionRecycling) {
mca::Context MCA(*MRI, *STI); mca::Context MCA(*MCRI, *STI);
std::unordered_map<const mca::InstrDesc *, SmallPtrSet<mca::Instruction *, 2>> std::unordered_map<const mca::InstrDesc *, SmallPtrSet<mca::Instruction *, 2>>
RecycledInsts; RecycledInsts;
auto GetRecycledInst = [&](const mca::InstrDesc &Desc) -> mca::Instruction * { auto GetRecycledInst = [&](const mca::InstrDesc &Desc) -> mca::Instruction * {
auto It = RecycledInsts.find(&Desc); auto It = RecycledInsts.find(&Desc);
if (It != RecycledInsts.end()) { if (It != RecycledInsts.end()) {
auto &Insts = It->second; auto &Insts = It->second;
if (Insts.size()) { if (Insts.size()) {
Show All 25 LinesTEST_F(X86TestBase, TestInstructionRecycling) {
// Add views. // Add views.
auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs, auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs,
PO.DispatchWidth); PO.DispatchWidth);
P->addEventListener(SV.get()); P->addEventListener(SV.get());
// Default InstrumentManager // Default InstrumentManager
auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); auto IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII);
mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get(), *IM); mca::InstrBuilder IB(*STI, *MCII, *MCRI, MCIA.get(), *IM);
IB.setInstRecycleCallback(GetRecycledInst); IB.setInstRecycleCallback(GetRecycledInst);
const SmallVector<mca::SharedInstrument> Instruments; const SmallVector<mca::SharedInstrument> Instruments;
// Tile size = 7 // Tile size = 7
for (unsigned i = 0U, E = MCIs.size(); i < E;) { for (unsigned i = 0U, E = MCIs.size(); i < E;) {
for (unsigned TE = i + 7; i < TE && i < E; ++i) { for (unsigned TE = i + 7; i < TE && i < E; ++i) {
Expected<std::unique_ptr<mca::Instruction>> InstOrErr = Expected<std::unique_ptr<mca::Instruction>> InstOrErr =
IB.createInstruction(MCIs[i], Instruments); IB.createInstruction(MCIs[i], Instruments);
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