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Differential D142264

[RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL.
ClosedPublic

Authored by craig.topper on Jan 20 2023, 4:15 PM.

Details

Reviewers
reames
frasercrmck
rogfer01
kito-cheng
Commits
rGb7166e252448: [RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL.
Summary

If we're extracting an element and inserting into a undef vector
with the same number of elements, we can use the original vector.

This pattern occurs around reductions that have been cascaded
together.

This can be generalized to wider/narrow vectors by using
insert_subvector/extract_subvector, but we don't have lit tests
for that case currently.

We can also support non-undef before by using a slide or vmv.v.v

Diff Detail

Event Timeline

craig.topper created this revision.Jan 20 2023, 4:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2023, 4:15 PM
Herald added subscribers: luke, VincentWu, vkmr and 25 others. · View Herald Transcript
craig.topper requested review of this revision.Jan 20 2023, 4:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2023, 4:15 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B209093: Diff 491002.Jan 20 2023, 5:56 PM
luke added inline comments.Jan 24 2023, 8:09 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
10580

Do we need to handle the case when VL=0 and the destination register is preserved?

reames accepted this revision.Jan 24 2023, 8:57 AM

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
10580

We checked the passthru result was undef above, so if VL=0 the result is fully undef.

This revision is now accepted and ready to land.Jan 24 2023, 8:57 AM
This revision was landed with ongoing or failed builds.Jan 24 2023, 5:16 PM
Closed by commit rGb7166e252448: [RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGb7166e252448: [RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
19 lines
test/
CodeGen/
RISCV/
rvv/
14 lines
51 lines
64 lines

Diff 491973

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,556 Lines • ▼ Show 20 Lines case RISCVISD::VMV_V_X_VL: {
unsigned ScalarSize = N->getOperand(1).getValueSizeInBits(); unsigned ScalarSize = N->getOperand(1).getValueSizeInBits();
unsigned EltWidth = N->getValueType(0).getScalarSizeInBits(); unsigned EltWidth = N->getValueType(0).getScalarSizeInBits();
if (ScalarSize > EltWidth && N->getOperand(0).isUndef()) if (ScalarSize > EltWidth && N->getOperand(0).isUndef())
if (SimplifyDemandedLowBitsHelper(1, EltWidth)) if (SimplifyDemandedLowBitsHelper(1, EltWidth))
return SDValue(N, 0); return SDValue(N, 0);
break; break;
} }
case RISCVISD::VFMV_S_F_VL: {
SDValue Src = N->getOperand(1);
// Try to remove vector->scalar->vector if the scalar->vector is inserting
// into an undef vector.
// TODO: Could use a vslide or vmv.v.v for non-undef.
if (N->getOperand(0).isUndef() &&
Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
isNullConstant(Src.getOperand(1)) &&
Src.getOperand(0).getValueType().isScalableVector()) {
EVT VT = N->getValueType(0);
EVT SrcVT = Src.getOperand(0).getValueType();
assert(SrcVT.getVectorElementType() == VT.getVectorElementType());
// Widths match, just return the original vector.
if (SrcVT == VT)
return Src.getOperand(0);
// TODO: Use insert_subvector/extract_subvector to change widen/narrow?
lukeUnsubmitted
Not Done
ReplyInline Actions

Do we need to handle the case when VL=0 and the destination register is preserved?

luke: Do we need to handle the case when VL=0 and the destination register is preserved?
reamesUnsubmitted
Not Done
ReplyInline Actions

We checked the passthru result was undef above, so if VL=0 the result is fully undef.

reames: We checked the passthru result was undef above, so if VL=0 the result is fully undef.
}
break;
}
case ISD::INTRINSIC_WO_CHAIN: { case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = N->getConstantOperandVal(0); unsigned IntNo = N->getConstantOperandVal(0);
switch (IntNo) { switch (IntNo) {
// By default we do not combine any intrinsic. // By default we do not combine any intrinsic.
default: default:
return SDValue(); return SDValue();
case Intrinsic::riscv_vcpop: case Intrinsic::riscv_vcpop:
case Intrinsic::riscv_vcpop_mask: case Intrinsic::riscv_vcpop_mask:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bltu a0, a2, .LBB8_2 ; CHECK-NEXT: bltu a0, a2, .LBB8_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB8_2: ; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: addi a1, a0, -32 ; CHECK-NEXT: addi a1, a0, -32
; CHECK-NEXT: sltu a0, a0, a1 ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1 ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl) %r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r ret float %r
} }
define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 zeroext %evl) { define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_v64f32: ; CHECK-LABEL: vpreduce_ord_fadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vslidedown.vi v24, v0, 4 ; CHECK-NEXT: vslidedown.vi v24, v0, 4
; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB9_2 ; CHECK-NEXT: bltu a0, a2, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: addi a1, a0, -32 ; CHECK-NEXT: addi a1, a0, -32
; CHECK-NEXT: sltu a0, a0, a1 ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1 ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl) %r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r ret float %r
} }
declare double @llvm.vp.reduce.fadd.v2f64(double, <2 x double>, <2 x i1>, i32) declare double @llvm.vp.reduce.fadd.v2f64(double, <2 x double>, <2 x i1>, i32)
define double @vpreduce_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 zeroext %evl) { define double @vpreduce_fadd_v2f64(double %s, <2 x double> %v, <2 x i1> %m, i32 zeroext %evl) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%v = load <128 x half>, ptr %x %v = load <128 x half>, ptr %x
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) { define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v128f16: ; CHECK-LABEL: vreduce_ord_fadd_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v24 ; CHECK-NEXT: vfredosum.vs v8, v8, v24
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: vfredosum.vs v8, v16, v8 ; CHECK-NEXT: vfredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, ptr %x %v = load <128 x half>, ptr %x
%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) %red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red ret half %red
} }
▲ Show 20 Lines • Show All 407 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%v = load <64 x float>, ptr %x %v = load <64 x float>, ptr %x
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) { define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v64f32: ; CHECK-LABEL: vreduce_ord_fadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: vle32.v v16, (a1)
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v24 ; CHECK-NEXT: vfredosum.vs v8, v8, v24
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: vfredosum.vs v8, v16, v8 ; CHECK-NEXT: vfredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x float>, ptr %x %v = load <64 x float>, ptr %x
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
ret float %red ret float %red
} }
Show All 20 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) { define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
; CHECK-LABEL: vreduce_ord_fwadd_v64f32: ; CHECK-LABEL: vreduce_ord_fwadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v16, a0 ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v16, v16, v24 ; CHECK-NEXT: vfwredosum.vs v8, v8, v24
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; CHECK-NEXT: vfwredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v16, ft0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x half>, ptr %x %v = load <64 x half>, ptr %x
%e = fpext <64 x half> %v to <64 x float> %e = fpext <64 x half> %v to <64 x float>
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e) %red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
ret float %red ret float %red
} }
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%v = load <32 x double>, ptr %x %v = load <32 x double>, ptr %x
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_ord_fadd_v32f64(ptr %x, double %s) { define double @vreduce_ord_fadd_v32f64(ptr %x, double %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f64: ; CHECK-LABEL: vreduce_ord_fadd_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v24 ; CHECK-NEXT: vfredosum.vs v8, v8, v24
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: vfredosum.vs v8, v16, v8 ; CHECK-NEXT: vfredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x double>, ptr %x %v = load <32 x double>, ptr %x
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
ret double %red ret double %red
} }
Show All 18 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) { define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
; CHECK-LABEL: vreduce_ord_fwadd_v32f64: ; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v16, 16 ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v24, fa0 ; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v16, v16, v24 ; CHECK-NEXT: vfwredosum.vs v8, v8, v24
; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma ; CHECK-NEXT: vfwredosum.vs v8, v16, v8
; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: vfmv.s.f v16, ft0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfwredosum.vs v8, v8, v16
; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x float>, ptr %x %v = load <32 x float>, ptr %x
%e = fpext <32 x float> %v to <32 x double> %e = fpext <32 x float> %v to <32 x double>
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e) %red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
ret double %red ret double %red
} }
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llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret half %r ret half %r
} }
declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32) declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32)
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) { define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv64f16: ; CHECK-LABEL: vpreduce_fadd_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a2, 1 ; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v24, v0, a1 ; CHECK-NEXT: vslidedown.vx v24, v0, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: bltu a0, a2, .LBB6_2 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bltu a0, a1, .LBB6_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, tu, ma
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl) %r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r ret half %r
} }
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) { define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16: ; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a2, 1 ; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v24, v0, a1 ; CHECK-NEXT: vslidedown.vx v24, v0, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: bltu a0, a2, .LBB7_2 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a2, e16, m8, tu, ma
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vfmv.f.s ft0, v25 ; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v8, v16, v8, v0.t ; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl) %r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r ret half %r
} }
declare float @llvm.vp.reduce.fadd.nxv1f32(float, <vscale x 1 x float>, <vscale x 1 x i1>, i32) declare float @llvm.vp.reduce.fadd.nxv1f32(float, <vscale x 1 x float>, <vscale x 1 x i1>, i32)
define float @vpreduce_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) { define float @vpreduce_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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