[RISCV] Support vector crypto extension ISA string and assembly

[4vtomat]

Summary

LLVM implements the 0.3 draft specification:
https://github.com/riscv/riscv-crypto/releases/download/v20230206/riscv-crypto-spec-vector.pdf
, and current vector crypto extension version can be found in:
https://github.com/riscv/riscv-crypto.

[4vtomat]

Since there's some accidentally pushed code. The old revision is moved to this one, sorry..

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

882

Line exceeds 80 characters

llvm/lib/Target/RISCV/RISCV.td

473 ↗

(On Diff #488929)

Indented too much

480 ↗

(On Diff #488929)

Indented too much

[4vtomat]

NFC, some indentation fix.

[reames]

This was brought up in today's RISCV sync call; I want to summarize the major points of discussion.

This patch is now behind the current most recent revision on the vector-crypto spec. (https://github.com/riscv/riscv-crypto/releases/download/v20230125/riscv-crypto-spec-vector.pdf) The assumption is that the patch needs to be updated to match most recent. If there's a reason why this assumption is wrong, please explicitly describe the argument.

There was confusion around the versioning scheme used in the vector-crypto spec. It looks like newer version have moved to an internally consistent (and less than 1.0) version scheme, so I think this item is resolved.

There was a mention of another change being made to the spec in the near future and a desire to wait until that had happened. This isn't required by our experimental extension policy. However, in generally trying to minimize churn by delaying a couple days is not unreasonable. I'd welcome comment from someone following spec changes as to whether we should delay here or not, and why.

[craig.topper]

In D141672#4100940, @reames wrote:

This was brought up in today's RISCV sync call; I want to summarize the major points of discussion.

This patch is now behind the current most recent revision on the vector-crypto spec. (https://github.com/riscv/riscv-crypto/releases/download/v20230125/riscv-crypto-spec-vector.pdf) The assumption is that the patch needs to be updated to match most recent. If there's a reason why this assumption is wrong, please explicitly describe the argument.

There was confusion around the versioning scheme used in the vector-crypto spec. It looks like newer version have moved to an internally consistent (and less than 1.0) version scheme, so I think this item is resolved.

There was a mention of another change being made to the spec in the near future and a desire to wait until that had happened. This isn't required by our experimental extension policy. However, in generally trying to minimize churn by delaying a couple days is not unreasonable. I'd welcome comment from someone following spec changes as to whether we should delay here or not, and why.

Here are some key points from today's crypto meeting that someone in attendance shared.

• vghmac.vv
  • a new variant vghacm.vv will be added (xor then mul)
• vandn operands will be reversed to match other insns in RISC-V
• new constraint for vl and element group operations: if VLMAX < EGS (equivalently VLEN * LMUL < EGW): raise an illegal exception (on top of vl % EGS != 0)
• Will define two meta extensions Zvkn and Zvks for the RVA23 profile
• Zvkn = Zvkns + Zvknhb (AES, SHA-256, SHA-512)
• Zvks = Zvksed + Zvksh (SM3, SM4)
• Will ask to add Zvkg + Zvkb as optional for RVA23 profile

[4vtomat]

Update to v20230206

[craig.topper]

@reames and I recently talked and we agreed that vector crypto is far enough along that we'd like to get something committed to LLVM in experimental state. We can do iterative refinement if the spec continues to change. I guess the question is whether we should update to the most recent now or land this first.

llvm/lib/Target/RISCV/RISCVFeatures.td

508

Indent this to line up with "'Zvknhb' on the previous line

537

This is indented 1 space too far.

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

11

Is this version out of date?

16

Can we name this VCLMUL_MV_V_X. That make it consistent with the similar VMUL_MV_V_X, VALU_MV_V_X, etc.

46

VROR_IV_V_X_I seems like a more consistent name.

75

I think this should be something like VAES_MV_V_S based on how the other multiclasses are named.

83

Maybe this should be something like VAESKF_MV_I?

llvm/test/MC/RISCV/rvv/zvkb.s

15

Add {{$}} to the end of the line

llvm/test/MC/RISCV/rvv/zvknh.s

23

Add {{$}} to the end of the line to make sure it checks the whole line. Same for all similar lines in all tests.

[asb]

In D141672#4177044, @craig.topper wrote:

I guess the question is whether we should update to the most recent now or land this first.

I think updating to the most recent would make sense. Review bandwidth is limited, and it doesn't look like a huge amount has been expended on this particular version of the patch already. So it seems most efficient to update to the latest version and then request review. Perhaps there are specifics I'm not aware of that change the balance, but that would be my default view.

[4vtomat]

Resolved Craig's comments and rename *zvkns* files to *zvkned*.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

888

Put single quotes around extension names in the error messages. I fixed the other error messages last week

llvm/lib/Target/RISCV/RISCVFeatures.td

508

Zvknhb implies Zvknha here it needs to imply it in RISCVISAInfo.cpp too.

509

Line 495 has Zvknhb implying Zvknha which would make it sufficient to only check HasStdExtZknha. I'm not sure if this code should be changed or the implies at line 495.

[4vtomat]

Resolved Craig's comments.

[reames]

FYI, zvkb was discussed at the Architectural Review Committee this week and they've asked for some significant changes and expansions. See the notes shared here: https://lists.riscv.org/g/tech-unprivileged/message/450

I actively do not think we need to wait on landing this patch until those expansions have been finalized. I think is fine to land this in experimental state, and then transform zvkb into the requested form. Having a generic vector bitmanip extension pulled out seems to make a lot of sense to me, and I like (most of) the proposed additions as they close holes we've encountered in codegen.

I've skimmed the review and didn't spot anything glaring, but want to leave approval to @craig.topper since he's already done one pass and is generally more familiar with the MC layer than I am.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

893

For consistency with the Zvk* error, use

"'zvknhb' requires 'v' or 'zve64*' extension to also be specified"

[4vtomat]

Resolved Craig's comment.

[craig.topper]

LGTM

clang/test/Preprocessor/riscv-target-features.c

 // CHECK-NOT: __riscv_svpbmt {{.*$}}
 // CHECK-NOT: __riscv_svinval {{.*$}}
 // CHECK-NOT: __riscv_xventanacondops {{.*$}}
 // CHECK-NOT: __riscv_zca {{.*$}}
 // CHECK-NOT: __riscv_zcb {{.*$}}
 // CHECK-NOT: __riscv_zcd {{.*$}}
 // CHECK-NOT: __riscv_zcf {{.*$}}
 // CHECK-NOT: __riscv_h {{.*$}}
+// CHECK-NOT: __riscv_zvkb {{.*$}}
+// CHECK-NOT: __riscv_zvkg {{.*$}}
+// CHECK-NOT: __riscv_zvkn {{.*$}}
+// CHECK-NOT: __riscv_zvknha {{.*$}}
+// CHECK-NOT: __riscv_zvknhb {{.*$}}
+// CHECK-NOT: __riscv_zvkned {{.*$}}
+// CHECK-NOT: __riscv_zvks {{.*$}}
+// CHECK-NOT: __riscv_zvksed {{.*$}}
+// CHECK-NOT: __riscv_zvksh {{.*$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
 // CHECK: __riscv_i 2000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \

 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izfa0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izfa0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s
 // CHECK-ZFA-EXT: __riscv_zfa 1000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvkb0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// CHECK-ZVKB-EXT: __riscv_zvkb  3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkg0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvkg0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
+// CHECK-ZVKG-EXT: __riscv_zvkg  3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvkn0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvkn0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
+// CHECK-ZVKN-EXT: __riscv_zvkn 3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvknha0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvknha0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvknhb0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvknhb0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb  3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkned0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvkned0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
+// CHECK-ZVKNED-EXT: __riscv_zvkned 3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvks0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvks0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
+// CHECK-ZVKS-EXT: __riscv_zvks 3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvksed0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvksed0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
+// CHECK-ZVKSED-EXT: __riscv_zvksed  3000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
+// CHECK-ZVKSH-EXT: __riscv_zvksh  3000{{$}}

llvm/docs/RISCVUsage.rst

``experimental-zihintntl``
   LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
 
 ``experimental-ztso``
   LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25).  The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document.  There are multiple possible mappings, and they are *not* mutually ABI compatible.  The mapping LLVM implements is ABI compatible with the default WMO mapping.  This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status.  User beware.
 
 ``experimental-zvfh``
   LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
 
+``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksh``
+  LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230206/riscv-crypto-spec-vector.pdf>`_. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+
 To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using.  To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`.  Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
 
 Vendor Extensions
 =================
 
 Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor.  The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification.  In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions.
 
 Inclusion of a vendor extension will be considered on a case by case basis.  All proposals should be brought to the bi-weekly RISCV sync calls for discussion.  For a general idea of the factors likely to be considered, please see the `Clang documentation <https://clang.llvm.org/get_involved.html>`_.

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
 
     {"zca", RISCVExtensionVersion{1, 0}},
     {"zcb", RISCVExtensionVersion{1, 0}},
     {"zcd", RISCVExtensionVersion{1, 0}},
     {"zcf", RISCVExtensionVersion{1, 0}},
     {"zfa", RISCVExtensionVersion{0, 1}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
     {"ztso", RISCVExtensionVersion{0, 1}},
+
+    // vector crypto
+    {"zvkb", RISCVExtensionVersion{0, 3}},
+    {"zvkg", RISCVExtensionVersion{0, 3}},
+    {"zvkn", RISCVExtensionVersion{0, 3}},
+    {"zvknha", RISCVExtensionVersion{0, 3}},
+    {"zvknhb", RISCVExtensionVersion{0, 3}},
+    {"zvkned", RISCVExtensionVersion{0, 3}},
+    {"zvks", RISCVExtensionVersion{0, 3}},
+    {"zvksed", RISCVExtensionVersion{0, 3}},
+    {"zvksh", RISCVExtensionVersion{0, 3}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
 
 // This function finds the first character that doesn't belong to a version
 // (e.g. zba1p0 is extension 'zba' of version '1p0'). So the function will
return createStringError(
         "'zvfh' requires 'zfh', 'zfhmin', 'zhinx' or 'zhinxmin' extension to "
         "also be specified");
 
   if (HasZvl && !HasVector)
     return createStringError(
         errc::invalid_argument,
         "'zvl*b' requires 'v' or 'zve*' extension to also be specified");
 
+  if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkn") ||
+       Exts.count("zvknha") || Exts.count("zvkned") || Exts.count("zvks") ||
+       Exts.count("zvksed") || Exts.count("zvksh")) &&
+      !HasVector)
+    return createStringError(
+        errc::invalid_argument,
+        "'zvk*' requires 'v' or 'zve*' extension to also be specified");
+
+  if (Exts.count("zvknhb") && !Exts.count("zve64x"))
+    return createStringError(
+        errc::invalid_argument,
+        "'zvknhb' requires 'v' or 'zve64*' extension to also be specified");
+
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   return Error::success();
 }
 
 static const char *ImpliedExtsD[] = {"f"};

 static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
                                        "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsZvkn[] = {"zvkned", "zvknhb", "zvkb"};
+static const char *ImpliedExtsZvknhb[] = {"zvknha"};
+static const char *ImpliedExtsZvks[] = {"zvksed", "zvksh", "zvkb"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsZcb[] = {"zca"};
 static const char *ImpliedExtsZfa[] = {"f"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"zkn"}, {ImpliedExtsZkn}},
     {{"zks"}, {ImpliedExtsZks}},
     {{"zve32f"}, {ImpliedExtsZve32f}},
     {{"zve32x"}, {ImpliedExtsZve32x}},
     {{"zve64d"}, {ImpliedExtsZve64d}},
     {{"zve64f"}, {ImpliedExtsZve64f}},
     {{"zve64x"}, {ImpliedExtsZve64x}},
     {{"zvfh"}, {ImpliedExtsZvfh}},
+    {{"zvkn"}, {ImpliedExtsZvkn}},
+    {{"zvknhb"}, {ImpliedExtsZvknhb}},
+    {{"zvks"}, {ImpliedExtsZvks}},
     {{"zvl1024b"}, {ImpliedExtsZvl1024b}},
     {{"zvl128b"}, {ImpliedExtsZvl128b}},
     {{"zvl16384b"}, {ImpliedExtsZvl16384b}},
     {{"zvl2048b"}, {ImpliedExtsZvl2048b}},
     {{"zvl256b"}, {ImpliedExtsZvl256b}},
     {{"zvl32768b"}, {ImpliedExtsZvl32768b}},
     {{"zvl4096b"}, {ImpliedExtsZvl4096b}},
     {{"zvl512b"}, {ImpliedExtsZvl512b}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
   bool isUImm2() const { return IsUImm<2>(); }
   bool isUImm3() const { return IsUImm<3>(); }
   bool isUImm5() const { return IsUImm<5>(); }
+  bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
 
   bool isRnumArg() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(10) &&
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isRnumArg_0_7() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && Imm >= INT64_C(0) && Imm <= INT64_C(7) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isRnumArg_1_10() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && Imm >= INT64_C(1) && Imm <= INT64_C(10) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isRnumArg_2_14() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && Imm >= INT64_C(2) && Imm <= INT64_C(14) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isSImm5() const {
     if (!isImm())
       return false;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     int64_t Imm;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isInt<5>(fixImmediateForRV32(Imm, isRV64Imm())) &&
            VK == RISCVMCExpr::VK_RISCV_None;
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSImm5Plus1: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
                                       (1 << 4),
                                       "immediate must be in the range");
   }
   case Match_InvalidRnumArg: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
   }
+  case Match_InvalidRnumArg_0_7: {
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 7);
+  }
+  case Match_InvalidRnumArg_1_10: {
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, 10);
+  }
+  case Match_InvalidRnumArg_2_14: {
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 2, 14);
+  }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
 // failure, returns true and sets RegNo to 0. If IsRV32E then registers

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
+  OPERAND_UIMM6,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,
   OPERAND_UIMM8_LSB000,
   OPERAND_UIMM9_LSB000,
   OPERAND_UIMM10_LSB00_NONZERO,
   OPERAND_UIMM12,
   OPERAND_ZERO,
   OPERAND_SIMM5,
   OPERAND_SIMM5_PLUS1,
   OPERAND_SIMM6,
   OPERAND_SIMM6_NONZERO,
   OPERAND_SIMM10_LSB0000_NONZERO,
   OPERAND_SIMM12,
   OPERAND_SIMM12_LSB00000,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
   OPERAND_UIMMLOG2XLEN_NONZERO,
   OPERAND_CLUI_IMM,
   OPERAND_VTYPEI10,
   OPERAND_VTYPEI11,
   OPERAND_RVKRNUM,
-  OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
+  OPERAND_RVKRNUM_0_7,
+  OPERAND_RVKRNUM_1_10,
+  OPERAND_RVKRNUM_2_14,
+  OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.
   OPERAND_AVL,
 };
 } // namespace RISCVOp
 
 // Describes the predecessor/successor bits used in the FENCE instruction.

llvm/lib/Target/RISCV/RISCVFeatures.td

def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
                               "'Ztso' (Memory Model - Total Store Order)">;
 
 def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
                                           "'Zawrs' (Wait on Reservation Set)">;
 def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
                                AssemblerPredicate<(all_of FeatureStdExtZawrs),
                                "'Zawrs' (Wait on Reservation Set)">;
 
+def FeatureStdExtZvkb
+    : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
+                       "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
+                              AssemblerPredicate<(all_of FeatureStdExtZvkb),
+                              "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+
+def FeatureStdExtZvkg
+    : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
+                       "'Zvkg' (Vector GCM instructions for Cryptography.)">;
+def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
+                              AssemblerPredicate<(all_of FeatureStdExtZvkg),
+                              "'Zvkg' (Vector GCM instructions for Cryptography.)">;
+
+def FeatureStdExtZvkn
+    : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
+                       "This extension is shorthand for the following set of "
+                       "other extensions: Zvkned, Zvknhb and Zvkb.">;
+
+def FeatureStdExtZvknha
+    : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
+                       "'Zvknha' (Vector SHA-2. (SHA-256 only))">;
+
+def FeatureStdExtZvknhb
+    : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
+                       "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))",
+                       [FeatureStdExtZvknha]>;
+def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
+                                AssemblerPredicate<(all_of FeatureStdExtZvknha),
+                                "'Zvknha' (Vector SHA-2. (SHA-256 only))">;
+
+def FeatureStdExtZvkned
+    : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
+                       "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
+                                AssemblerPredicate<(all_of FeatureStdExtZvkned),
+                                "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+
+def FeatureStdExtZvks
+    : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
+                       "This extension is shorthand for the following set of "
+                       "other extensions: Zvksed, Zvksh and Zvkb.">;
+
+def FeatureStdExtZvksed
+    : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
+                       "'Zvksed' (SM4 Block Cipher Instructions.)">;
+def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
+                                AssemblerPredicate<(all_of FeatureStdExtZvksed),
+                                "'Zvksed' (SM4 Block Cipher Instructions.)">;
+
+def FeatureStdExtZvksh
+    : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
+                       "'Zvksh' (SM3 Hash Function Instructions.)">;
+def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
+                               AssemblerPredicate<(all_of FeatureStdExtZvksh),
+                               "'Zvksh' (SM3 Hash Function Instructions.)">;
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 def FeatureVendorXVentanaCondOps
     : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
                        "'XVentanaCondOps' (Ventana Conditional Ops)">;
 def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def OPC_NMADD     : RISCVOpcode<"NMADD",     0b1001111>;
 def OPC_OP_FP     : RISCVOpcode<"OP_FP",     0b1010011>;
 def OPC_OP_V      : RISCVOpcode<"OP_V",      0b1010111>;
 def OPC_CUSTOM_2  : RISCVOpcode<"CUSTOM_2",  0b1011011>;
 def OPC_BRANCH    : RISCVOpcode<"BRANCH",    0b1100011>;
 def OPC_JALR      : RISCVOpcode<"JALR",      0b1100111>;
 def OPC_JAL       : RISCVOpcode<"JAL",       0b1101111>;
 def OPC_SYSTEM    : RISCVOpcode<"SYSTEM",    0b1110011>;
+def OPC_OP_P      : RISCVOpcode<"OP_P",      0b1110111>;
 def OPC_CUSTOM_3  : RISCVOpcode<"CUSTOM_3",  0b1111011>;
 
 class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : Instruction {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

break;
           break;
         case RISCVOp::OPERAND_CLUI_IMM:
           Ok = (isUInt<5>(Imm) && Imm != 0) ||
                (Imm >= 0xfffe0 && Imm <= 0xfffff);
           break;
         case RISCVOp::OPERAND_RVKRNUM:
           Ok = Imm >= 0 && Imm <= 10;
           break;
+        case RISCVOp::OPERAND_RVKRNUM_0_7:
+          Ok = Imm >= 0 && Imm <= 7;
+          break;
+        case RISCVOp::OPERAND_RVKRNUM_1_10:
+          Ok = Imm >= 1 && Imm <= 10;
+          break;
+        case RISCVOp::OPERAND_RVKRNUM_2_14:
+          Ok = Imm >= 2 && Imm <= 14;
+          break;
         }
         if (!Ok) {
           ErrInfo = "Invalid immediate";
           return false;
         }
       }
     }
   }

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 
 def InsnDirectiveOpcode : AsmOperandClass {
   let Name = "InsnDirectiveOpcode";
   let ParserMethod = "parseInsnDirectiveOpcode";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isImm";
 }
 
+def uimm6 : Operand<XLenVT> {
+  let ParserMatchClass = UImmAsmOperand<6>;
+  let DecoderMethod = "decodeUImmOperand<6>";
+  let OperandType = "OPERAND_UIMM6";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm7_opcode : Operand<XLenVT> {
   let ParserMatchClass = InsnDirectiveOpcode;
   let DecoderMethod = "decodeUImmOperand<7>";
   let OperandType = "OPERAND_UIMM7";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm7 : Operand<XLenVT> {

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

: RVInstVX<funct6, opv, (outs VR:$vd),
                 (ins FPR32:$rs1, VR:$vs2, VMaskOp:$vm),
                 opcodestr, "$vd, $rs1, $vs2$vm">;
 
 // op vd, vs2, vm (use vs1 as instruction encoding)
 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
     : RVInstV<funct6, vs1, opv, (outs VR:$vd),
                (ins VR:$vs2, VMaskOp:$vm),
                opcodestr, "$vd, $vs2$vm">;
+
+// op vd, vs2 (use vs1 as instruction encoding)
+class VALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+    : RVInstV<funct6, vs1, opv, (outs VR:$vd),
+              (ins VR:$vs2), opcodestr,
+              "$vd, $vs2"> {
+  let vm = 1;
+}
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//
 
 multiclass VIndexLoadStore<list<int> EEWList> {
def VSUXSEG #nf #EI64_V
           VSXSEGSched<nf, 64, "U", UpperBoundLMUL>;
     def VSOXSEG #nf #EI64_V
         : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
                                "vsoxseg" #nf #"ei64.v">,
           VSXSEGSched<nf, 64, "O", UpperBoundLMUL>;
   }
 } // Predicates = [HasVInstructionsI64, IsRV64]
 
+include "RISCVInstrInfoZvk.td"
 include "RISCVInstrInfoVPseudos.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

+//===-- RISCVInstrInfoZvk.td - RISC-V 'Zvk' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zvk',
+// Vector Cryptography Instructions extension, version 0.3.
+//
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
+  def V  : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
+           Sched<[WriteVIALUV_UpperBound, ReadVIALUV_UpperBound,
+                  ReadVIALUV_UpperBound, ReadVMask]>;
+  def X  : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
+           Sched<[WriteVIALUX_UpperBound, ReadVIALUV_UpperBound,
+                  ReadVIALUX_UpperBound, ReadVMask]>;
+}
+
+class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
+                     string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<6> imm;
+  bits<5> vd;
+  bit vm;
+
+  let Inst{31-27} = funct6{5-1};
+  let Inst{26} = imm{5};
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = imm{4-0};
+  let Inst{14-12} = OPIVI.Value;
+  let Inst{11-7} = vd;
+  let Opcode = OPC_OP_V.Value;
+
+  let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
+}
+
+multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6,
+                              Operand optype = uimm6, string vw = "v">
+    : VALU_IV_V_X<opcodestr, funct6> {
+  def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
+              (ins VR:$vs2, optype:$imm, VMaskOp:$vm),
+              opcodestr # "." # vw # "i", "$vd, $vs2, $imm$vm">,
+         Sched<[WriteVIALUI_UpperBound, ReadVIALUV_UpperBound,
+                ReadVMask]>;
+}
+
+// op vd, vs2, vs1
+class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+    : VALUVVNoVm<funct6, opv, opcodestr> {
+  let Opcode = OPC_OP_P.Value;
+}
+
+// op vd, vs2, imm, vm
+class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
+    : VALUVINoVm<funct6, opcodestr, optype> {
+  let Opcode = OPC_OP_P.Value;
+  let Inst{14-12} = OPMVV.Value;
+}
+
+// op vd, vs2 (use vs1 as instruction encoding)
+class PALUVs2NoVm<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+    : VALUVs2NoVm<funct6, vs1, opv, opcodestr> {
+  let Opcode = OPC_OP_P.Value;
+}
+
+multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
+                         RISCVVFormat opv, string opcodestr> {
+  def NAME # _VV : PALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
+  def NAME # _VS : PALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
+}
+
+// vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need
+// to customize one for them.
+class VAESKF_MV_I<bits<6> funct6, string opcodestr, Operand optype>
+    : VALUVINoVm<funct6, opcodestr, optype> {
+  let Opcode = OPC_OP_P.Value;
+  let Inst{14-12} = OPMVV.Value;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+def RnumArg_0_7 : AsmOperandClass {
+  let Name = "RnumArg_0_7";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidRnumArg_0_7";
+}
+
+def RnumArg_1_10 : AsmOperandClass {
+  let Name = "RnumArg_1_10";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidRnumArg_1_10";
+}
+
+def RnumArg_2_14 : AsmOperandClass {
+  let Name = "RnumArg_2_14";
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = "InvalidRnumArg_2_14";
+}
+
+def rnum_0_7 : Operand<XLenVT>, ImmLeaf<XLenVT,
+                                         [{return (0 <= Imm && Imm <= 7);}]> {
+  let ParserMatchClass = RnumArg_0_7;
+  let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_RVKRNUM_0_7";
+  let OperandNamespace = "RISCVOp";
+}
+
+def rnum_1_10 : Operand<XLenVT>, ImmLeaf<XLenVT,
+                                         [{return (1 <= Imm && Imm <= 10);}]> {
+  let ParserMatchClass = RnumArg_1_10;
+  let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_RVKRNUM_1_10";
+  let OperandNamespace = "RISCVOp";
+}
+
+def rnum_2_14 : Operand<XLenVT>, ImmLeaf<XLenVT,
+                                         [{return (2 <= Imm && Imm <= 14);}]> {
+  let ParserMatchClass = RnumArg_2_14;
+  let DecoderMethod = "decodeUImmOperand<5>";
+  let OperandType = "OPERAND_RVKRNUM_2_14";
+  let OperandNamespace = "RISCVOp";
+}
+
+let Predicates = [HasStdExtZvkb] in {
+  defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;
+  def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
+  defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>;
+  defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>;
+  def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
+  defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
+  defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
+} // Predicates = [HasStdExtZvkb]
+
+let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
+  def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">;
+  def VGMUL_VV : PALUVs2NoVm<0b101000, 0b10001, OPMVV, "vgmul.vv">;
+} // Predicates = [HasStdExtZvkg]
+
+let Predicates = [HasStdExtZvknha], RVVConstraint = NoConstraint in {
+  def VSHA2CH_VV : PALUVVNoVm<0b101110, OPMVV, "vsha2ch.vv">;
+  def VSHA2CL_VV : PALUVVNoVm<0b101111, OPMVV, "vsha2cl.vv">;
+  def VSHA2MS_VV : PALUVVNoVm<0b101101, OPMVV, "vsha2ms.vv">;
+} // Predicates = [HasStdExtZvknha]
+
+let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
+  defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
+  defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
+  defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
+  defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
+  def VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>;
+  def VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>;
+  def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
+} // Predicates = [HasStdExtZvkned]
+
+let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
+  def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
+  defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
+} // Predicates = [HasStdExtZvksed]
+
+let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in {
+  def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
+  def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
+} // Predicates = [HasStdExtZvksh]

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCF %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s

 ; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
 
 ; CHECK: .attribute 4, 16
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
 ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"

 ; RV32XTHEADSYNC: .attribute 5, "rv32i2p0_xtheadsync1p0"
 ; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
 ; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
 ; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
 ; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p0_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p0_zifencei2p0"
 ; RV32ZFA: .attribute 5, "rv32i2p0_f2p0_zfa0p1"
+; RV32ZVKB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNED: .attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
 ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"

 ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
 ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
 ; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
 ; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
 ; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p0_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p0_zifencei2p0"
 ; RV64ZFA: .attribute 5, "rv64i2p0_f2p0_zfa0p1"
+; RV64ZVKB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNED: .attribute 5, "rv64i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_zba1p0"
 
 .attribute arch, "rv32izbb1p0"
 # CHECK: attribute      5, "rv32i2p0_zbb1p0"
 
 .attribute arch, "rv32izbc1p0"
 # CHECK: attribute      5, "rv32i2p0_zbc1p0"
 
+.attribute arch, "rv32i_zve64x_zvkb0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvkg0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+
+.attribute arch, "rv32i_zve64x_zvkn0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvknha0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+
+.attribute arch, "rv32i_zve64x_zvknhb0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvkned0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvks0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksed0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksh0p3"
+# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+
 .attribute arch, "rv32izbs1p0"
 # CHECK: attribute      5, "rv32i2p0_zbs1p0"
 
 .attribute arch, "rv32ifzfhmin1p0"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfhmin1p0"
 
 .attribute arch, "rv32ifzfh1p0"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfh1p0"

llvm/test/MC/RISCV/rvv/zvkb.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 05 94 04   <unknown>
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 45 95 04   <unknown>
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 25 94 48   <unknown>
+
+vclmul.vv v10, v9, v8
+# CHECK-INST: vclmul.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 25 94 32   <unknown>
+                       
+vclmul.vx v10, v9, a0
+# CHECK-INST: vclmul.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 65 95 32   <unknown>
+
+vclmulh.vv v10, v9, v8
+# CHECK-INST: vclmulh.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 25 94 36   <unknown>
+
+vclmulh.vx v10, v9, a0
+# CHECK-INST: vclmulh.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 65 95 36   <unknown>
+                       
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 a5 94 48   <unknown>
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 05 94 54   <unknown>
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 45 95 54   <unknown>
+
+vror.vv v10, v9, v8, v0.t
+# CHECK-INST: vror.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 05 94 50   <unknown>
+
+vror.vx v10, v9, a0, v0.t
+# CHECK-INST: vror.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 45 95 50   <unknown>
+
+vror.vi v10, v9, 33, v0.t
+# CHECK-INST: vror.vi v10, v9, 33, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 57 b5 90 54   <unknown>

llvm/test/MC/RISCV/rvv/zvkg.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkg  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkg %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vghsh.vv v10, v9, v8
+# CHECK-INST: vghsh.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xb2]
+# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 77 25 94 b2   <unknown>

llvm/test/MC/RISCV/rvv/zvkned-invalid.s

+# RUN: not llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]

llvm/test/MC/RISCV/rvv/zvkned.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkned  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkned %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaesdf.vv v10, v9
+# CHECK-INST: vaesdf.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 90 a2   <unknown>
+
+vaesdf.vs v10, v9
+# CHECK-INST: vaesdf.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 90 a6   <unknown>
+
+vaesef.vv v10, v9
+# CHECK-INST: vaesef.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 91 a2   <unknown>
+                       
+vaesef.vs v10, v9
+# CHECK-INST: vaesef.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 91 a6   <unknown>
+
+vaesdm.vv v10, v9
+# CHECK-INST: vaesdm.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x90,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 25 90 a2   <unknown>
+                       
+vaesdm.vs v10, v9
+# CHECK-INST: vaesdm.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x90,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 25 90 a6   <unknown>
+
+vaesem.vv v10, v9
+# CHECK-INST: vaesem.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x91,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 25 91 a2   <unknown>
+                       
+vaesem.vs v10, v9
+# CHECK-INST: vaesem.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x91,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 25 91 a6   <unknown>
+
+vaeskf1.vi v10, v9, 1
+# CHECK-INST: vaeskf1.vi v10, v9, 1
+# CHECK-ENCODING: [0x77,0xa5,0x90,0x8a]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 90 8a   <unknown>
+
+vaeskf2.vi v10, v9, 2
+# CHECK-INST: vaeskf2.vi v10, v9, 2
+# CHECK-ENCODING: [0x77,0x25,0x91,0xaa]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 25 91 aa   <unknown>
+
+vaesz.vs v10, v9
+# CHECK-INST: vaesz.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}}
+# CHECK-UNKNOWN: 77 a5 93 a6   <unknown>

llvm/test/MC/RISCV/rvv/zvknh.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvknha  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:        | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvknhb  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsha2ms.vv v10, v9, v8
+# CHECK-INST: vsha2ms.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xb6]
+# CHECK-UNKNOWN: 77 25 94 b6   <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}}
+
+vsha2ch.vv v10, v9, v8
+# CHECK-INST: vsha2ch.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xba]
+# CHECK-UNKNOWN: 77 25 94 ba   <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}}
+
+vsha2cl.vv v10, v9, v8
+# CHECK-INST: vsha2cl.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0xbe]
+# CHECK-UNKNOWN: 77 25 94 be   <unknown>
+# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}}

llvm/test/MC/RISCV/rvv/zvksed-invalid.s

+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]

llvm/test/MC/RISCV/rvv/zvksed.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 86   <unknown>
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a2   <unknown>
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a6   <unknown>

llvm/test/MC/RISCV/rvv/zvksh.s

+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:        | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 ae   <unknown>
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 94 82   <unknown>