[Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

[kito-cheng]

Summary

RISC-V supports -march, -mtune, and -mcpu: -march provides the
architecture extension information, -mtune provide the pipeline model, and
-mcpu provides both.

What's the priority among those options for now(w/o this patch)?

Pipeline model:

• Take from -mtune if present.
• Take from -mcpu if present
• Use the default pipeline model: generic-rv32 or generic-rv64

Architecture extension has quite complicated behavior now:

• Take union from -march and -mcpu if both are present.
• Take from -march if present.
• Take from -mcpu if present.
• Implied from -mabi if present.
• Use the default architecture depending on the target triple

We treat -mcpu/-mtune and -mcpu/-march differently, and it's
kind of counterintuitive: -march is explicitly specified but ignored.

This patch adjusts the priority between -mcpu/-march, letting it use
architecture extension information from -march if it's present.

So the priority of architecture extension information becomes:

• Take from -march if present.
• Take from -mcpu if present.
• Implied from -mabi if present.
• Use the default architecture depending on the target triple

And this also match what we implement in RISC-V GCC too.

[craig.topper]

So if I read this correctly, the effect of this is that we never pass -target-cpu to the backend after this patch and will only pass -target-feature and -tune-cpu?

[craig.topper]

This doesn't seem correct

What's the priority among those options for now(w/o this patch)?

Pipeline model:

Take from -mtune if present.
Take from -mcpu if present
Use the default pipeline model: generic-rv32 or generic-rv64
Architecture extension:

Take from -mcpu if present.
Take from -march if present.
Use the default architecture depending on the target triple

The code in riscv::getRISCVArch prioritizes -march over -mcpu for architecture extensions for setting -target-features.

But the backend still applies extensions from -target-cpu via the tablegen features from RISCV.td.

So its not even a "priority", we end up with a union.

clang/lib/Driver/ToolChains/Clang.cpp

5457 ↗

(On Diff #485373)

I wonder if we should stop getCPUName from calling getRISCVTargetCPU instead? Have you audited all callers of getCPUName?

[kito-cheng]

So if I read this correctly, the effect of this is that we never pass -target-cpu to the backend after this patch and will only pass -target-feature and -tune-cpu?

Yes, that's prevent us taking any extensions from -target-cpu, so always pass -target-feature and -tune-cpu only.

The code in riscv::getRISCVArch prioritizes -march over -mcpu for architecture extensions for setting -target-features.

But the backend still applies extensions from -target-cpu via the tablegen features from RISCV.td.

So its not even a "priority", we end up with a union.

Damm, you are right, that...even worth than I thought before, let me update the summary.

clang/lib/Driver/ToolChains/Clang.cpp

5457 ↗

(On Diff #485373)

That sounds a better way, that prevent us to auditing every caller of getCPUName.

[kito-cheng]

Changes:

• Stop calling getRISCVTargetCPU in getCPUName.

[craig.topper]

clang/lib/Driver/ToolChains/Clang.cpp

5457 ↗

(On Diff #485373)

I think we need to do the audit either way.

[kito-cheng]

clang/lib/Driver/ToolChains/Clang.cpp

5457 ↗

(On Diff #485373)

28 call site in clang, search by $ grep [^r]getCPUName * -R -n

$ grep [^r]getCPUName * -R -n
Reviewed and seems OK:

• Clang::ConstructJob: lib/Driver/ToolChains/Clang.cpp:5438: getCPUName(D, HostArgs, *TC.getAuxTriple(), /*FromAs*/ false);
• ClangAs::ConstructJob: lib/Driver/ToolChains/Clang.cpp:7880: std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ true);
• -aux-target-cpu: lib/Driver/ToolChains/Clang.cpp:5480: std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);

Should fix:

• tools::addLTOOptions: lib/Driver/ToolChains/CommonArgs.cpp:630: std::string CPU = getCPUName(D, Args, ToolChain.getTriple());

Should fix in future, because we don't really port that part for RISC-V:

• lib/Driver/ToolChains/Flang.cpp:89: std::string CPU = getCPUName(D, Args, Triple);

x86 specific cpu_specific attribute:

• include/clang/Basic/Attr.td:1136: IdentifierInfo *getCPUName(unsigned Index) const {
• lib/CodeGen/CodeGenModule.cpp:1336: Out << getCPUSpecificMangling(CGM, Attr->getCPUName(CPUIndex)->getName());
• lib/CodeGen/CodeGenModule.cpp:2202: SD->getCPUName(GD.getMultiVersionIndex())->getName());
• lib/AST/ASTContext.cpp:13386: SD->getCPUName(GD.getMultiVersionIndex())->getName(), FeaturesTmp);

Target specific:

• lib/Driver/ToolChains/AVR.cpp:372: if (getCPUName(D, Args, Triple).empty())
• lib/Driver/ToolChains/AVR.cpp:445: std::string CPU = getCPUName(D, Args, getToolChain().getTriple());
• lib/Driver/ToolChains/Arch/Mips.cpp:453: return llvm::StringSwitch<bool>(getCPUName(D, Args, Triple))
• lib/Driver/ToolChains/Arch/AArch64.cpp:623: std::string CPU = getCPUName(D, Args, Triple);
• Sparc:
  • lib/Driver/ToolChains/OpenBSD.cpp:64: std::string CPU = getCPUName(D, Args, Triple);
  • lib/Driver/ToolChains/FreeBSD.cpp:103: std::string CPU = getCPUName(D, Args, getToolChain().getTriple());
• aarch64: lib/Driver/ToolChains/Gnu.cpp:461: std::string CPU = getCPUName(D, Args, Triple);
• PPC: lib/Driver/ToolChains/Gnu.cpp:760: getCPUName(D, Args, getToolChain().getTriple())));
• PPCLE: lib/Driver/ToolChains/Gnu.cpp:768: getCPUName(D, Args, getToolChain().getTriple())));
• PPC64: lib/Driver/ToolChains/Gnu.cpp:776: getCPUName(D, Args, getToolChain().getTriple())));
• PPC64LE: lib/Driver/ToolChains/Gnu.cpp:784: getCPUName(D, Args, getToolChain().getTriple())));
• SPARC: lib/Driver/ToolChains/Gnu.cpp:819: std::string CPU = getCPUName(D, Args, getToolChain().getTriple());
• SPARCv9: lib/Driver/ToolChains/Gnu.cpp:827: std::string CPU = getCPUName(D, Args, getToolChain().getTriple());
• ARM: lib/Driver/ToolChains/Clang.cpp:1548: std::string CPU = getCPUName(D, Args, Triple, /*FromAs*/ false);
• AArch64: lib/Driver/ToolChains/Fuchsia.cpp:92: std::string CPU = getCPUName(D, Args, Triple);
• Sparc: lib/Driver/ToolChains/NetBSD.cpp:83: std::string CPU = getCPUName(D, Args, Triple);
• Sparcv9: lib/Driver/ToolChains/NetBSD.cpp:91: std::string CPU = getCPUName(D, Args, Triple);

Declaration:

• lib/Driver/ToolChains/CommonArgs.h:174:std::string getCPUName(const Driver &D, const llvm::opt::ArgList &Args,

Implement

• lib/Driver/ToolChains/CommonArgs.cpp:363:std::string tools::getCPUName(const Driver &D, const ArgList &Args,

[kito-cheng]

• @craig.topper has suggested we could pass all extension with - or + to neutralize the effect of the -target-cpu, that's less intrusive way.
• Add release note to mention the behavior change.

[kito-cheng]

Changes:

• Add release note to mention the behavior change for -march and -mcpu.
• New way to implement this behavior, passing all supported extension with - or +, this way is less RISC-V specific logical around -mcpu.

[kito-cheng]

Changes:

• Trim unexpected change by clang-format

clang/test/Driver/riscv-cpus.c

13

Need to break this into two line since we'll add bunch of negative list of extension here.

clang/test/Driver/riscv-default-features.c

5

Same reason here.

[craig.topper]

clang/docs/ReleaseNotes.rst

806

back-end -> backend

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

47

true -> /*AddAllExtensions*/true

llvm/lib/Support/RISCVISAInfo.cpp

14

Why is this needed?

336

AddAllExtension -> AddAllExtensions

[MaskRay]

(Haven't looked carefully ) but the Pipeline model: matches AArch64 (ideal model in my view https://community.arm.com/arm-community-blogs/b/tools-software-ides-blog/posts/compiler-flags-across-architectures-march-mtune-and-mcpu)
(I probably need to update my https://maskray.me/blog/2022-08-28-march-mcpu-mtune)

"Architecture extension has quite complicated behavior now:" looks too complex.

Take union from -march and -mcpu if both are present.

I'd like that we just take -march= and report an error if it is incompatible with -mcpu=

[kito-cheng]

Changes:

• Address Craig's comment.

[kito-cheng]

(I probably need to update my https://maskray.me/blog/2022-08-28-march-mcpu-mtune)

At least the behavior of RISC-V GCC need to update:

Architecture extension:

• Take from -march if present.
• Take from -mcpu if present.
• Use the default architecture (TARGET_RISCV_DEFAULT_ARCH, set by --with-arch, implementation by spec here)

---

"Architecture extension has quite complicated behavior now:" looks too complex.
Take union from -march and -mcpu if both are present.

Yeah, and actually more like buggy behavior now, it seems like take from -march if both are given from the clang view, because the architecture test macro are only defined the part of -march, but the union behavior will performed by LLVM backend by -target-cpu option.

---

I'd like that we just take -march= and report an error if it is incompatible with -mcpu=

I would prefer using same * behavior as RISC-V GCC, one reason is RISC-V GCC implement that behavior since GCC 11 (and implemented at Oct. 2020).

• Take from -march if present.
• Take from -mcpu if present.
• Implied from -mabi if present.
• Use the default architecture depending on the target triple

* Okay, it's actually not same, it's just similar because GCC won't implied arch from -mabi.

llvm/lib/Support/RISCVISAInfo.cpp

14

Added during my first attempt, apparently I forgot to clean this up.

[craig.topper]

LGTM

[MaskRay]

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

47

The canonical comment is /*AddAllExtensions=*/true

clang/test/Driver/riscv-cpus.c

86

If the two features are adjacent, I suggest you place them one the same line.

[MaskRay]

clang/test/Driver/riscv-march-mcpu-mtune.c

31

This NOT pattern isn't useful as -target-cpu has occurred.

llvm/lib/Support/RISCVISAInfo.cpp

335

Use function_ref (in llvm::)

349

auto const => RISCVSupportedExtension (optional const)

350

for ...
  if (!Exts.count...)
    Features.push_back...

[kito-cheng]

clang/test/Driver/riscv-cpus.c

86

It's not adjacent after this patch.

clang/test/Driver/riscv-march-mcpu-mtune.c

31

Thanks for catch this.

clang/docs/ReleaseNotes.rst

 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
 RISC-V Support in Clang
 -----------------------
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for ``-mcpu``.
   Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
 - Native detections via ``-mcpu=native`` and ``-mtune=native`` are supported.
+- Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the
+  architecture extension union of ``-mcpu`` and ``-march`` before, and now will
+  take architecture extensions from ``-march`` if both are given.
 
 X86 Support in Clang
 --------------------
 - Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk.
 - Fix 32-bit ``__fastcall`` and ``__vectorcall`` ABI mismatch with MSVC.
 - Add ISA of ``AMX-FP16`` which support ``_tile_dpfp16ps``.
 - Switch ``AVX512-BF16`` intrinsics types from ``short`` to ``__bf16``.
 - Add support for ``PREFETCHI`` instructions.

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
       D.Diag(diag::err_drv_invalid_riscv_arch_name)
           << Arch << ErrMsg.getMessage();
     });
 
     return false;
   }
 
   (*ISAInfo)->toFeatures(
-      Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); });
+      Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
+      /*AddAllExtensions=*/true);
   return true;
 }
 
 // Get features except standard extension feature
 static bool getRISCFeaturesFromMcpu(const llvm::Triple &Triple, StringRef Mcpu,
                                     std::vector<StringRef> &Features) {
   bool Is64Bit = Triple.isRISCV64();
   llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);

clang/test/Driver/riscv-cpus.c

 // Check target CPUs are correctly passed.
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s
 // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32"
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
 // MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
-// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit"
 // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
 // MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
-// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "-64bit"
 // MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
 
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=native | FileCheck -check-prefix=MCPU-NATIVE %s
 // MCPU-NATIVE-NOT: "-target-cpu" "native"
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"

 // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
 // MCPU-SIFIVE-E34: "-target-feature" "+c"
 // MCPU-SIFIVE-E34: "-target-abi" "ilp32"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
 // MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
 // MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
-// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
 // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
-// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
 
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s
 // MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54"
 // MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S54: "-target-feature" "+c"
+// MCPU-SIFIVE-S54: "-target-feature" "+64bit"
 // MCPU-SIFIVE-S54: "-target-abi" "lp64d"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s
 // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
 // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S76: "-target-feature" "+c"
+// MCPU-SIFIVE-S76: "-target-feature" "+64bit"
 // MCPU-SIFIVE-S76: "-target-abi" "lp64d"
 
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
 // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
 // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-U54: "-target-feature" "+c"
+// MCPU-SIFIVE-U54: "-target-feature" "+64bit"
 // MCPU-SIFIVE-U54: "-target-abi" "lp64d"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s
 // MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-U54: "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
 
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s
 // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
 // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
 // MCPU-SIFIVE-E76: "-target-feature" "+c"
 // MCPU-SIFIVE-E76: "-target-abi" "ilp32"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
 // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
 // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
 
 // march overwrite mcpu's default march
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c"
 // MCPU-MARCH: "-target-abi" "ilp32"
 
 // Check interaction between mcpu and mtune, mtune won't affect arch related

clang/test/Driver/riscv-default-features.c

 // RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
 // RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
-// RV32: "target-features"="+32bit,+a,+c,+m,+relax,-save-restore"
-// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
+// RV32-SAME: -save-restore
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
+// RV64-SAME: -save-restore
 
 // Dummy function
 int foo(void){
   return  3;
 }

clang/test/Driver/riscv-march-mcpu-mtune.c

+// Check the priority between -mcpu, -mtune and -march
+
+// sifive-e76 is rv32imafc and sifive-e31 is rv32imac
+
+// -mcpu, -mtune and -march are not given, pipeline model and arch ext. use
+// default setting.
+// RUN: %clang --target=riscv32-elf -### -c %s 2>&1 \
+// RUN:     | FileCheck -check-prefix=CHECK-DEFAULT %s
+// CHECK-DEFAULT: "-target-cpu" "generic-rv32"
+// CHECK-DEFAULT: "-target-feature" "+m" "-target-feature" "+a"
+// CHECK-DEFAULT: "-target-feature" "+c"
+
+// -mtune is given, pipeline model take from -mtune, arch ext. use
+// default setting.
+// RUN: %clang --target=riscv32 -mtune=sifive-e76 -### -c %s 2>&1 \
+// RUN:     | FileCheck -check-prefix=MTUNE-E76 %s
+// MTUNE-E76: "-target-feature" "+m" "-target-feature" "+a"
+// MTUNE-E76: "-target-feature" "+c"
+// MTUNE-E76: "-target-feature" "-f"
+// MTUNE-E76: "-tune-cpu" "sifive-e76"
+
+// -march is given, arch ext. take from -march, pipeline model use
+// default setting.
+// RUN: %clang --target=riscv32 -### -c %s -march=rv32imafdc 2>&1 \
+// RUN:     | FileCheck -check-prefix=MARCH-RV32IMAFDC %s
+// MARCH-RV32IMAFDC: "-target-cpu" "generic-rv32"
+// MARCH-RV32IMAFDC: "-target-feature" "+m" "-target-feature" "+a"
+// MARCH-RV32IMAFDC: "-target-feature" "+f" "-target-feature" "+d"
+// MARCH-RV32IMAFDC: "-target-feature" "+c"
+
+// -mcpu is given, pipeline model and arch ext. from -mcpu.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 2>&1 \
+// RUN:     | FileCheck -check-prefix=MCPU-E76 %s
+// MCPU-E76: "-target-cpu" "sifive-e76"
+// MCPU-E76: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-E76: "-target-feature" "+f" "-target-feature" "+c"
+
+// -mcpu and -mtune are given, so pipeline model take from -mtune, and arch ext.
+// take from -mcpu since -march is not given.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 -mtune=sifive-e31 2>&1 \
+// RUN:     | FileCheck -check-prefix=MCPU-E76-MTUNE-E31 %s
+// MCPU-E76-MTUNE-E31: "-target-cpu" "sifive-e76"
+// MCPU-E76-MTUNE-E31: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-E76-MTUNE-E31: "-target-feature" "+f" "-target-feature" "+c"
+// MCPU-E76-MTUNE-E31: "-tune-cpu" "sifive-e31"
+
+// RUN: %clang --target=riscv32 -### -c %s -mtune=sifive-e76 -mcpu=sifive-e31 2>&1 \
+// RUN:     | FileCheck -check-prefix=MTUNE-E76-MCPU-E31 %s
+// MTUNE-E76-MCPU-E31: "-target-cpu" "sifive-e31"
+// MTUNE-E76-MCPU-E31: "-target-feature" "+m" "-target-feature" "+a"
+// MTUNE-E76-MCPU-E31: "-target-feature" "+c"
+// MTUNE-E76-MCPU-E31: "-target-feature" "-f"
+// MTUNE-E76-MCPU-E31: "-tune-cpu" "sifive-e76"
+
+// -mcpu and -march are given, so pipeline model take from -mcpu since -mtune is
+// not given, and arch ext. take from -march.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -march=rv32ic 2>&1 \
+// RUN:     | FileCheck -check-prefix=MCPU-E31-MARCH-RV32I %s
+// MCPU-E31-MARCH-RV32I: "-target-cpu" "sifive-e31"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "+c"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-m"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-a"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-f"
+
+// -mcpu, -march and -mtune are given, so pipeline model take from -mtune
+// and arch ext. take from -march, -mcpu is unused.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -mtune=sifive-e76 -march=rv32ic 2>&1 \
+// RUN:     | FileCheck -check-prefix=MCPU-E31-MTUNE-E76-MARCH-RV32I %s
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-cpu" "sifive-e31"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "+c"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-a"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-f"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-tune-cpu" "sifive-e76"

llvm/include/llvm/Support/RISCVISAInfo.h

parseArchString(StringRef Arch, bool EnableExperimentalExtension,
                   bool ExperimentalExtensionVersionCheck = true);
 
   /// Parse RISCV ISA info from feature vector.
   static llvm::Expected<std::unique_ptr<RISCVISAInfo>>
   parseFeatures(unsigned XLen, const std::vector<std::string> &Features);
 
   /// Convert RISCV ISA info to a feature vector.
   void toFeatures(std::vector<StringRef> &Features,
-                  std::function<StringRef(const Twine &)> StrAlloc) const;
+                  llvm::function_ref<StringRef(const Twine &)> StrAlloc,
+                  bool AddAllExtensions) const;
 
   const OrderedExtensionMap &getExtensions() const { return Exts; };
 
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
   unsigned getMinVLen() const { return MinVLen; }
   unsigned getMaxVLen() const { return 65536; }
   unsigned getMaxELen() const { return MaxELen; }

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISCV Arch String Parser -------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <array>
 #include <optional>
 #include <string>
 #include <vector>
 
if (LHSRank != RHSRank)
     return LHSRank < RHSRank;
 
   // If the rank is same, it must be sorted by lexicographic order.
   return LHS < RHS;
 }
 
 void RISCVISAInfo::toFeatures(
     std::vector<StringRef> &Features,
-    std::function<StringRef(const Twine &)> StrAlloc) const {
+    llvm::function_ref<StringRef(const Twine &)> StrAlloc,
+    bool AddAllExtensions) const {
   for (auto const &Ext : Exts) {
     StringRef ExtName = Ext.first;
 
     if (ExtName == "i")
       continue;
 
     if (isExperimentalExtension(ExtName)) {
       Features.push_back(StrAlloc("+experimental-" + ExtName));
     } else {
       Features.push_back(StrAlloc("+" + ExtName));
     }
   }
+  if (AddAllExtensions) {
+    for (const RISCVSupportedExtension &Ext : SupportedExtensions) {
+      if (Exts.count(Ext.Name))
+        continue;
+      Features.push_back(StrAlloc(Twine("-") + Ext.Name));
+    }
+
+    for (const RISCVSupportedExtension &Ext : SupportedExperimentalExtensions) {
+      if (Exts.count(Ext.Name))
+        continue;
+      Features.push_back(StrAlloc(Twine("-experimental-") + Ext.Name));
+    }
+  }
 }
 
 // Extensions may have a version number, and may be separated by
 // an underscore '_' e.g.: rv32i2_m2.
 // Version number is divided into major and minor version numbers,
 // separated by a 'p'. If the minor version is 0 then 'p0' can be
 // omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1.
 static Error getExtensionVersion(StringRef Ext, StringRef In, unsigned &Major,