[RISCV] Add integer scalar instructions to isAssociativeAndCommutative

[HsiangKai]

Summary

Inspired by D138107.

We can add ADD, AND, OR, XOR, MUL to isAssociativeAndCommutative to
increase instruction-level parallelism by the existing MachineCombiner
pass.

[HsiangKai]

Add default case for the switch statement.

[HsiangKai]

clang format

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

2627–2629

This seems out of scope of this patch?

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

2627–2629

In order to let hasReassociableSibling() return correct result for integer scalar cases, we have to handle non-fp cases here.

I think it makes sense to return true when instructions have no FRM operand in this function. There may be better way to handle it for hasReassociableSibling(). Any suggestions?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1380

I don't think MULH and MULHU are associative.

[HsiangKai]

Remove MULH, MULHU from the list.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1380

I added them by mistake. Thanks for pointing it out.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

2627–2629

Thanks for the explanation, the function name let me feel that's unrelated to integer operations, however I think this kind of change the behavior of this function, next if-condition is

if (MI1FrmOpIdx < 0 || MI2FrmOpIdx < 0)
  return false;

I didn't have idea how to improve that yet, but I feel it should be add check logic in hasReassociableSibling rather than here.

Anyway I don't have strong objection here.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1370

extract this switch to a new function isAssociativeAndCommutativeIntOpc and then use that in RISCVInstrInfo::hasReassociableSibling?

[HsiangKai]

• Move FRM operand checking to hasReassociableSibling.
• Add ADD, SUB, ADDW, SUBW to getInverseOpcode and add test cases for the inverse cases.

[HsiangKai]

clang format

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1370

I moved FRM checking to hasReassociableSibling.

[asi-sc]

Have you had a chance to make some performance measurements?

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1378

One thing that I'm a little worried is the described in the spec possibility for microarchitecture fusion(7.1):

If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.

As I know, we do nothing to support this fusion, however we quite often generate the recommended sequence (I checked some binaries I have on hand, it's not thorough research). Also some mul/mulh pairs we can easily fix by a simple DAG mutation at the scheduling stage:

%10:gpr = MULHU %9:gpr, %5:gpr
%11:gpr = MUL %9:gpr, %5:gpr
--->
%11:gpr = MUL %9:gpr, %5:gpr
%10:gpr = MULHU %9:gpr, %5:gpr

Machine combiner aggressively changes operands of multiplications, so I expect it'll worsen code from the fusion point of view.

Actually, I not sure that it's a real problem and just want to ensure that we are OK with it.

[HsiangKai]

In D140530#4015004, @asi-sc wrote:

Have you had a chance to make some performance measurements?

Quoted from D138107,

I run C/C++ benchmarks in SPECrate 2017 on Fujitsu A64FX processor, which has two pipelines for integer operations and SIMD/FP operations each. 511.povray_r had 4% improvement. Other benchmarks (int: 500, 502, 505, 520, 523, 525, 531, 541, 557; fp: 508, 510, 519, 538, 544) were within 1% up/down. For a synthetic benchmark, it doubled the performance.

I have no performance number for RISC-V multiple issue machines. I am not sure what the impact is of the patch. Is there anyone can help to measure it?

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1378

Thank you for pointing it out. It is a good point. I am not aware the possibilities of mulh/mul fusion in the microarchitecture design. It is hard to say which one is better unless we have more performance data. How about removing mul/mulw in this patch to be conservative?

[HsiangKai]

In D140530#4016511, @HsiangKai wrote:

In D140530#4015004, @asi-sc wrote:

Have you had a chance to make some performance measurements?

Quoted from D138107,

I run C/C++ benchmarks in SPECrate 2017 on Fujitsu A64FX processor, which has two pipelines for integer operations and SIMD/FP operations each. 511.povray_r had 4% improvement. Other benchmarks (int: 500, 502, 505, 520, 523, 525, 531, 541, 557; fp: 508, 510, 519, 538, 544) were within 1% up/down. For a synthetic benchmark, it doubled the performance.

I have no performance number for RISC-V multiple issue machines. I am not sure what the impact is of the patch. Is there anyone can help to measure it?

By the way, the number from D138107 are including SIMD/SVE instruction patterns. We only implement scalar part. (Vector instructions have more than 2 input operands. They are not applicable here.)

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1373

Do you plan to support Zbb MIN(U)/MAX(U)?

1378

I'm not sure we need to worry about fusion until the compiler supports the DAG mutation for such fusion.

[asi-sc]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1378

From my expectations, reassociation of mul instructions that can be fused with mulh should be a quite rare case. Whereas reassociation of mul instructions happens often (I did some experiments previously). So, I agree with Craig but I'd ask you to add a comment about the possible impact of MachineCombiner on the fusion.

[HsiangKai]

• Add comment for MUL.
• Add MIN(U)/MAX(U).

[asi-sc]

Thanks, no more comments from my side.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1354

swap the order of these conditions. There's no reason to call hasEqualFRM if we already know both indices are negative.

[HsiangKai]

Address comments.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

bool RISCVInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
   if (!TargetInstrInfo::hasReassociableSibling(Inst, Commuted))
     return false;
 
   const MachineRegisterInfo &MRI = Inst.getMF()->getRegInfo();
   unsigned OperandIdx = Commuted ? 2 : 1;
   const MachineInstr &Sibling =
       *MRI.getVRegDef(Inst.getOperand(OperandIdx).getReg());
 
-  return RISCV::hasEqualFRM(Inst, Sibling);
+  int16_t InstFrmOpIdx =
+      RISCV::getNamedOperandIdx(Inst.getOpcode(), RISCV::OpName::frm);
+  int16_t SiblingFrmOpIdx =
+      RISCV::getNamedOperandIdx(Sibling.getOpcode(), RISCV::OpName::frm);
+
+  return RISCV::hasEqualFRM(Inst, Sibling) || (InstFrmOpIdx < 0 && SiblingFrmOpIdx < 0);
 }
 
 bool RISCVInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
                                                  bool Invert) const {
   unsigned Opc = Inst.getOpcode();
   if (Invert) {
     auto InverseOpcode = getInverseOpcode(Opc);
     if (!InverseOpcode)
       return false;
     Opc = *InverseOpcode;
   }
 
   if (isFADD(Opc) || isFMUL(Opc))
     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
+
+  switch (Opc) {
+  default:
+    return false;
+  case RISCV::ADD:
+  case RISCV::ADDW:
+  case RISCV::AND:
+  case RISCV::OR:
+  case RISCV::XOR:
+  case RISCV::MUL:
+  case RISCV::MULW:
+    return true;
+  }
+
   return false;
 }
 
 std::optional<unsigned>
 RISCVInstrInfo::getInverseOpcode(unsigned Opcode) const {
   switch (Opcode) {
   default:
     return std::nullopt;
   case RISCV::FADD_H:
     return RISCV::FSUB_H;
   case RISCV::FADD_S:
     return RISCV::FSUB_S;
   case RISCV::FADD_D:
     return RISCV::FSUB_D;
   case RISCV::FSUB_H:
     return RISCV::FADD_H;
   case RISCV::FSUB_S:
     return RISCV::FADD_S;
   case RISCV::FSUB_D:
     return RISCV::FADD_D;
+  case RISCV::ADD:
+    return RISCV::SUB;
+  case RISCV::SUB:
+    return RISCV::ADD;
+  case RISCV::ADDW:
+    return RISCV::SUBW;
+  case RISCV::SUBW:
+    return RISCV::ADDW;
   }
 }
 
 static bool canCombineFPFusedMultiply(const MachineInstr &Root,
                                       const MachineOperand &MO,
                                       bool DoRegPressureReduce) {
   if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
     return false;
return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
          !MI.isInlineAsm();
 }
 
 bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
   int16_t MI1FrmOpIdx =
       RISCV::getNamedOperandIdx(MI1.getOpcode(), RISCV::OpName::frm);
   int16_t MI2FrmOpIdx =
       RISCV::getNamedOperandIdx(MI2.getOpcode(), RISCV::OpName::frm);
   if (MI1FrmOpIdx < 0 || MI2FrmOpIdx < 0)
     return false;
   MachineOperand FrmOp1 = MI1.getOperand(MI1FrmOpIdx);
   MachineOperand FrmOp2 = MI2.getOperand(MI2FrmOpIdx);
   return FrmOp1.getImm() == FrmOp2.getImm();
 }

llvm/test/CodeGen/RISCV/addc-adde-sube-subc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 
 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
 
 define i64 @addc_adde(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: addc_adde:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a3, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
   %1 = add i64 %a, %b
   ret i64 %1
 }
 
 define i64 @subc_sube(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: subc_sube:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a4, a0, a2
+; RV32I-NEXT:    add a3, a3, a4
 ; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a1, a1, a4
 ; RV32I-NEXT:    sub a0, a0, a2
 ; RV32I-NEXT:    ret
   %1 = sub i64 %a, %b
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/addcarry.ll

 ; RISCV32-NEXT:    mul a4, a0, a3
 ; RISCV32-NEXT:    mulhu a5, a0, a2
 ; RISCV32-NEXT:    add a6, a5, a4
 ; RISCV32-NEXT:    mul a4, a1, a2
 ; RISCV32-NEXT:    add a4, a6, a4
 ; RISCV32-NEXT:    sltu a7, a4, a6
 ; RISCV32-NEXT:    sltu a5, a6, a5
 ; RISCV32-NEXT:    mulhu a6, a0, a3
-; RISCV32-NEXT:    add a5, a6, a5
-; RISCV32-NEXT:    mulhu a6, a1, a2
-; RISCV32-NEXT:    add a5, a5, a6
+; RISCV32-NEXT:    mulhu t0, a1, a2
+; RISCV32-NEXT:    add a5, a5, t0
+; RISCV32-NEXT:    add a5, a5, a7
+; RISCV32-NEXT:    mul a7, a1, a3
 ; RISCV32-NEXT:    add a5, a5, a7
-; RISCV32-NEXT:    mul a6, a1, a3
-; RISCV32-NEXT:    add a5, a5, a6
+; RISCV32-NEXT:    add a5, a6, a5
 ; RISCV32-NEXT:    bgez a1, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1:
 ; RISCV32-NEXT:    sub a5, a5, a2
 ; RISCV32-NEXT:  .LBB0_2:
 ; RISCV32-NEXT:    bgez a3, .LBB0_4
 ; RISCV32-NEXT:  # %bb.3:
 ; RISCV32-NEXT:    sub a5, a5, a0
 ; RISCV32-NEXT:  .LBB0_4:

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

 }
 
 define i64 @add_mul_combine_accept_a3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_a3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    addi a0, a2, 1073
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_a3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addi a0, a0, 1073
 ; RV64IMB-NEXT:    ret

 }
 
 define i64 @add_mul_combine_accept_b3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_b3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 23
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 50
 ; RV32IMB-NEXT:    addi a0, a0, 1119
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_b3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    li a1, 23
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
 ; RV64IMB-NEXT:    addiw a1, a1, 1119

 }
 
 define i64 @add_mul_combine_reject_a3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_a3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -185
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    ret

 }
 
 define i64 @add_mul_combine_reject_c3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_c3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 73
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 18
 ; RV32IMB-NEXT:    addi a0, a0, -728
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    ret

 
 define i64 @add_mul_combine_reject_d3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_d3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 192
 ; RV32IMB-NEXT:    mulhu a2, a0, a2
 ; RV32IMB-NEXT:    sh1add a1, a1, a1
 ; RV32IMB-NEXT:    slli a1, a1, 6
-; RV32IMB-NEXT:    add a1, a2, a1
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
-; RV32IMB-NEXT:    slli a2, a0, 6
+; RV32IMB-NEXT:    slli a3, a0, 6
 ; RV32IMB-NEXT:    lui a0, 47
 ; RV32IMB-NEXT:    addi a0, a0, -512
-; RV32IMB-NEXT:    add a0, a2, a0
-; RV32IMB-NEXT:    sltu a2, a0, a2
-; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a0, a3, a0
+; RV32IMB-NEXT:    sltu a3, a0, a3
+; RV32IMB-NEXT:    add a1, a1, a3
+; RV32IMB-NEXT:    add a1, a2, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_d3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh1add a0, a0, a0
 ; RV64IMB-NEXT:    slli a0, a0, 6
 ; RV64IMB-NEXT:    ret

 }
 
 define i64 @add_mul_combine_reject_e3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_e3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -185
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    ret

 }
 
 define i64 @add_mul_combine_reject_f3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_f3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -145
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1972
 ; RV64IMB-NEXT:    li a1, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addi a0, a0, 11

 }
 
 define i64 @add_mul_combine_reject_g3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_g3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    li a2, 73
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, -882
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addi a0, a0, 10

 
 define i64 @mul3000_add8990_c(i64 %x) {
 ; RV32IMB-LABEL: mul3000_add8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1
 ; RV32IMB-NEXT:    addi a2, a2, -1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, 798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_add8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1

 
 define i64 @mul3000_sub8990_c(i64 %x) {
 ; RV32IMB-LABEL: mul3000_sub8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1
 ; RV32IMB-NEXT:    addi a2, a2, -1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 1048574
 ; RV32IMB-NEXT:    addi a0, a0, -798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    addi a1, a1, -1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096

 
 define i64 @mulneg3000_add8990_c(i64 %x) {
 ; RV32IMB-LABEL: mulneg3000_add8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1048575
 ; RV32IMB-NEXT:    addi a2, a2, 1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    sub a3, a3, a0
-; RV32IMB-NEXT:    add a1, a3, a1
+; RV32IMB-NEXT:    sub a1, a0, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, 798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
-; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    sub a1, a1, a2
+; RV32IMB-NEXT:    sub a1, a3, a1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, -3
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1

 
 define i64 @mulneg3000_sub8990_c(i64 %x) {
 ; RV32IMB-LABEL: mulneg3000_sub8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1048575
 ; RV32IMB-NEXT:    addi a2, a2, 1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
-; RV32IMB-NEXT:    sub a3, a3, a0
-; RV32IMB-NEXT:    add a1, a3, a1
+; RV32IMB-NEXT:    sub a1, a0, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 1048574
 ; RV32IMB-NEXT:    addi a0, a0, -798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
-; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    sub a1, a1, a2
+; RV32IMB-NEXT:    sub a1, a3, a1
 ; RV32IMB-NEXT:    addi a1, a1, -1
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 3
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096

llvm/test/CodeGen/RISCV/alu64.ll

 define i64 @add(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: add:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: add:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a3, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
   %1 = add i64 %a, %b
   ret i64 %1
 }
 
 define i64 @sub(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sub:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: sub:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a4, a0, a2
+; RV32I-NEXT:    add a3, a3, a4
 ; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a1, a1, a4
 ; RV32I-NEXT:    sub a0, a0, a2
 ; RV32I-NEXT:    ret
   %1 = sub i64 %a, %b
   ret i64 %1
 }
 
 define i64 @sll(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sll:

llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

 ; RV32I-NEXT:    lui a2, 16
 ; RV32I-NEXT:    addi a2, a2, -256
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a3, a0, 24
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    and a2, a0, a2
 ; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_bswap_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a0, 8
 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 8
 ; RV64I-NEXT:    slliw a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZB-LABEL: test_bswap_i32:
 ; RV32ZB:       # %bb.0:
 ; RV32ZB-NEXT:    rev8 a0, a0
 ; RV32ZB-NEXT:    ret
 ;

 ; RV32I-NEXT:    lui a3, 16
 ; RV32I-NEXT:    addi a3, a3, -256
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
 ; RV32I-NEXT:    and a4, a1, a3
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    or a2, a4, a2
 ; RV32I-NEXT:    or a2, a1, a2
 ; RV32I-NEXT:    srli a1, a0, 8
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    srli a4, a0, 24
 ; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:    and a3, a0, a3
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a3
+; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_bswap_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a0, 40
 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srli a3, a0, 56
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    srli a3, a0, 24
 ; RV64I-NEXT:    lui a4, 4080
 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    srli a5, a0, 8
 ; RV64I-NEXT:    srliw a5, a5, 24
 ; RV64I-NEXT:    slli a5, a5, 24
-; RV64I-NEXT:    or a3, a5, a3
 ; RV64I-NEXT:    or a1, a3, a1
+; RV64I-NEXT:    or a1, a5, a1
 ; RV64I-NEXT:    and a4, a0, a4
 ; RV64I-NEXT:    slli a4, a4, 24
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    slli a3, a3, 32
 ; RV64I-NEXT:    or a3, a4, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 40
 ; RV64I-NEXT:    slli a0, a0, 56
-; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a2, a2, a3
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZB-LABEL: test_bswap_i64:
 ; RV32ZB:       # %bb.0:
 ; RV32ZB-NEXT:    rev8 a2, a1
 ; RV32ZB-NEXT:    rev8 a1, a0
 ; RV32ZB-NEXT:    mv a0, a2

 ; RV32I-NEXT:    lui a2, 16
 ; RV32I-NEXT:    addi a2, a2, -256
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a3, a0, 24
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    and a2, a0, a2
 ; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    lui a2, 61681
 ; RV32I-NEXT:    addi a2, a2, -241
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    or a0, a1, a0

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 8
 ; RV64I-NEXT:    slliw a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    lui a2, 61681
 ; RV64I-NEXT:    addiw a2, a2, -241
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    slliw a0, a0, 4
 ; RV64I-NEXT:    or a0, a1, a0

 ; RV32I-NEXT:    lui a3, 16
 ; RV32I-NEXT:    addi a3, a3, -256
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
 ; RV32I-NEXT:    and a4, a1, a3
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    or a2, a4, a2
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    srli a2, a1, 4
 ; RV32I-NEXT:    lui a4, 61681
 ; RV32I-NEXT:    addi a4, a4, -241
 ; RV32I-NEXT:    and a2, a2, a4
 ; RV32I-NEXT:    and a1, a1, a4
 ; RV32I-NEXT:    slli a1, a1, 4
 ; RV32I-NEXT:    or a1, a2, a1

 ; RV32I-NEXT:    or a2, a2, a1
 ; RV32I-NEXT:    srli a1, a0, 8
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    srli a7, a0, 24
 ; RV32I-NEXT:    or a1, a1, a7
 ; RV32I-NEXT:    and a3, a0, a3
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a3
+; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    and a1, a1, a4
 ; RV32I-NEXT:    and a0, a0, a4
 ; RV32I-NEXT:    slli a0, a0, 4
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 2
 ; RV32I-NEXT:    and a1, a1, a5

 ; RV64I-NEXT:    srli a3, a0, 56
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    srli a3, a0, 24
 ; RV64I-NEXT:    lui a4, 4080
 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    srli a5, a0, 8
 ; RV64I-NEXT:    srliw a5, a5, 24
 ; RV64I-NEXT:    slli a5, a5, 24
-; RV64I-NEXT:    or a3, a5, a3
 ; RV64I-NEXT:    or a1, a3, a1
+; RV64I-NEXT:    or a1, a5, a1
 ; RV64I-NEXT:    and a4, a0, a4
 ; RV64I-NEXT:    slli a4, a4, 24
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    slli a3, a3, 32
 ; RV64I-NEXT:    or a3, a4, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 40
 ; RV64I-NEXT:    slli a0, a0, 56
-; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    lui a2, %hi(.LCPI6_0)
-; RV64I-NEXT:    ld a2, %lo(.LCPI6_0)(a2)
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a2, a2, a3
+; RV64I-NEXT:    lui a3, %hi(.LCPI6_0)
+; RV64I-NEXT:    ld a3, %lo(.LCPI6_0)(a3)
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    and a1, a1, a3
+; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    lui a2, %hi(.LCPI6_1)
 ; RV64I-NEXT:    ld a2, %lo(.LCPI6_1)(a2)
 ; RV64I-NEXT:    slli a0, a0, 4
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 2
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    lui a2, %hi(.LCPI6_2)

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

 ; Check 2x*xlen values are aligned appropriately when passed on the stack
 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
 define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind {
 ; The double should be 8-byte aligned on the stack, but the two-element array
 ; should only be 4-byte aligned
 ; RV32I-FPELIM-LABEL: callee_aligned_stack:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lw a0, 0(a2)
-; RV32I-FPELIM-NEXT:    lw a1, 20(sp)
-; RV32I-FPELIM-NEXT:    lw a2, 0(sp)
-; RV32I-FPELIM-NEXT:    lw a3, 8(sp)
-; RV32I-FPELIM-NEXT:    lw a4, 16(sp)
-; RV32I-FPELIM-NEXT:    add a0, a0, a7
-; RV32I-FPELIM-NEXT:    add a0, a0, a2
-; RV32I-FPELIM-NEXT:    add a0, a0, a3
-; RV32I-FPELIM-NEXT:    add a0, a0, a4
+; RV32I-FPELIM-NEXT:    lw a1, 0(sp)
+; RV32I-FPELIM-NEXT:    lw a2, 8(sp)
+; RV32I-FPELIM-NEXT:    lw a3, 16(sp)
+; RV32I-FPELIM-NEXT:    lw a4, 20(sp)
+; RV32I-FPELIM-NEXT:    add a1, a7, a1
+; RV32I-FPELIM-NEXT:    add a1, a1, a2
+; RV32I-FPELIM-NEXT:    add a1, a1, a3
+; RV32I-FPELIM-NEXT:    add a1, a1, a4
 ; RV32I-FPELIM-NEXT:    add a0, a0, a1
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_aligned_stack:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw a0, 0(a2)
-; RV32I-WITHFP-NEXT:    lw a1, 20(s0)
-; RV32I-WITHFP-NEXT:    lw a2, 0(s0)
-; RV32I-WITHFP-NEXT:    lw a3, 8(s0)
-; RV32I-WITHFP-NEXT:    lw a4, 16(s0)
-; RV32I-WITHFP-NEXT:    add a0, a0, a7
-; RV32I-WITHFP-NEXT:    add a0, a0, a2
-; RV32I-WITHFP-NEXT:    add a0, a0, a3
-; RV32I-WITHFP-NEXT:    add a0, a0, a4
+; RV32I-WITHFP-NEXT:    lw a1, 0(s0)
+; RV32I-WITHFP-NEXT:    lw a2, 8(s0)
+; RV32I-WITHFP-NEXT:    lw a3, 16(s0)
+; RV32I-WITHFP-NEXT:    lw a4, 20(s0)
+; RV32I-WITHFP-NEXT:    add a1, a7, a1
+; RV32I-WITHFP-NEXT:    add a1, a1, a2
+; RV32I-WITHFP-NEXT:    add a1, a1, a3
+; RV32I-WITHFP-NEXT:    add a1, a1, a4
 ; RV32I-WITHFP-NEXT:    add a0, a0, a1
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = bitcast fp128 %c to i128
   %2 = trunc i128 %1 to i32
   %3 = add i32 %2, %g

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

 define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
 ; RV32I-FPELIM-LABEL: callee_many_scalars:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lw t0, 4(sp)
 ; RV32I-FPELIM-NEXT:    lw t1, 0(sp)
 ; RV32I-FPELIM-NEXT:    andi a0, a0, 255
 ; RV32I-FPELIM-NEXT:    slli a1, a1, 16
 ; RV32I-FPELIM-NEXT:    srli a1, a1, 16
-; RV32I-FPELIM-NEXT:    add a0, a0, a1
-; RV32I-FPELIM-NEXT:    add a0, a0, a2
-; RV32I-FPELIM-NEXT:    xor a1, a4, t1
-; RV32I-FPELIM-NEXT:    xor a2, a3, a7
-; RV32I-FPELIM-NEXT:    or a1, a2, a1
-; RV32I-FPELIM-NEXT:    seqz a1, a1
-; RV32I-FPELIM-NEXT:    add a0, a1, a0
+; RV32I-FPELIM-NEXT:    add a1, a1, a2
+; RV32I-FPELIM-NEXT:    xor a2, a4, t1
+; RV32I-FPELIM-NEXT:    xor a3, a3, a7
+; RV32I-FPELIM-NEXT:    or a2, a3, a2
+; RV32I-FPELIM-NEXT:    seqz a2, a2
+; RV32I-FPELIM-NEXT:    add a1, a2, a1
 ; RV32I-FPELIM-NEXT:    add a0, a0, a5
 ; RV32I-FPELIM-NEXT:    add a0, a0, a6
 ; RV32I-FPELIM-NEXT:    add a0, a0, t0
+; RV32I-FPELIM-NEXT:    add a0, a1, a0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_many_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw t0, 4(s0)
 ; RV32I-WITHFP-NEXT:    lw t1, 0(s0)
 ; RV32I-WITHFP-NEXT:    andi a0, a0, 255
 ; RV32I-WITHFP-NEXT:    slli a1, a1, 16
 ; RV32I-WITHFP-NEXT:    srli a1, a1, 16
-; RV32I-WITHFP-NEXT:    add a0, a0, a1
-; RV32I-WITHFP-NEXT:    add a0, a0, a2
-; RV32I-WITHFP-NEXT:    xor a1, a4, t1
-; RV32I-WITHFP-NEXT:    xor a2, a3, a7
-; RV32I-WITHFP-NEXT:    or a1, a2, a1
-; RV32I-WITHFP-NEXT:    seqz a1, a1
-; RV32I-WITHFP-NEXT:    add a0, a1, a0
+; RV32I-WITHFP-NEXT:    add a1, a1, a2
+; RV32I-WITHFP-NEXT:    xor a2, a4, t1
+; RV32I-WITHFP-NEXT:    xor a3, a3, a7
+; RV32I-WITHFP-NEXT:    or a2, a3, a2
+; RV32I-WITHFP-NEXT:    seqz a2, a2
+; RV32I-WITHFP-NEXT:    add a1, a2, a1
 ; RV32I-WITHFP-NEXT:    add a0, a0, a5
 ; RV32I-WITHFP-NEXT:    add a0, a0, a6
 ; RV32I-WITHFP-NEXT:    add a0, a0, t0
+; RV32I-WITHFP-NEXT:    add a0, a1, a0
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %a_ext = zext i8 %a to i32
   %b_ext = zext i16 %b to i32
   %1 = add i32 %a_ext, %b_ext
   %2 = add i32 %1, %c

 ; RV32I-FPELIM-NEXT:    lw a7, 4(a0)
 ; RV32I-FPELIM-NEXT:    lw a1, 8(a1)
 ; RV32I-FPELIM-NEXT:    lw a0, 8(a0)
 ; RV32I-FPELIM-NEXT:    xor a5, a6, a5
 ; RV32I-FPELIM-NEXT:    xor a4, a7, a4
 ; RV32I-FPELIM-NEXT:    or a4, a4, a5
 ; RV32I-FPELIM-NEXT:    xor a0, a0, a1
 ; RV32I-FPELIM-NEXT:    xor a2, a3, a2
-; RV32I-FPELIM-NEXT:    or a0, a2, a0
 ; RV32I-FPELIM-NEXT:    or a0, a0, a4
+; RV32I-FPELIM-NEXT:    or a0, a2, a0
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_large_scalars:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw a2, 0(a1)
 ; RV32I-WITHFP-NEXT:    lw a3, 0(a0)
 ; RV32I-WITHFP-NEXT:    lw a4, 4(a1)
 ; RV32I-WITHFP-NEXT:    lw a5, 12(a1)
 ; RV32I-WITHFP-NEXT:    lw a6, 12(a0)
 ; RV32I-WITHFP-NEXT:    lw a7, 4(a0)
 ; RV32I-WITHFP-NEXT:    lw a1, 8(a1)
 ; RV32I-WITHFP-NEXT:    lw a0, 8(a0)
 ; RV32I-WITHFP-NEXT:    xor a5, a6, a5
 ; RV32I-WITHFP-NEXT:    xor a4, a7, a4
 ; RV32I-WITHFP-NEXT:    or a4, a4, a5
 ; RV32I-WITHFP-NEXT:    xor a0, a0, a1
 ; RV32I-WITHFP-NEXT:    xor a2, a3, a2
-; RV32I-WITHFP-NEXT:    or a0, a2, a0
 ; RV32I-WITHFP-NEXT:    or a0, a0, a4
+; RV32I-WITHFP-NEXT:    or a0, a2, a0
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %b_bitcast = bitcast fp128 %b to i128
   %1 = icmp eq i128 %a, %b_bitcast
   %2 = zext i1 %1 to i32

 ; RV32I-FPELIM-NEXT:    lw a6, 4(a7)
 ; RV32I-FPELIM-NEXT:    lw a0, 8(a0)
 ; RV32I-FPELIM-NEXT:    lw a7, 8(a7)
 ; RV32I-FPELIM-NEXT:    xor a4, a5, a4
 ; RV32I-FPELIM-NEXT:    xor a3, a6, a3
 ; RV32I-FPELIM-NEXT:    or a3, a3, a4
 ; RV32I-FPELIM-NEXT:    xor a0, a7, a0
 ; RV32I-FPELIM-NEXT:    xor a1, a2, a1
-; RV32I-FPELIM-NEXT:    or a0, a1, a0
 ; RV32I-FPELIM-NEXT:    or a0, a0, a3
+; RV32I-FPELIM-NEXT:    or a0, a1, a0
 ; RV32I-FPELIM-NEXT:    seqz a0, a0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw a0, 4(s0)
 ; RV32I-WITHFP-NEXT:    lw a1, 0(a0)
 ; RV32I-WITHFP-NEXT:    lw a2, 0(a7)
 ; RV32I-WITHFP-NEXT:    lw a3, 4(a0)
 ; RV32I-WITHFP-NEXT:    lw a4, 12(a0)
 ; RV32I-WITHFP-NEXT:    lw a5, 12(a7)
 ; RV32I-WITHFP-NEXT:    lw a6, 4(a7)
 ; RV32I-WITHFP-NEXT:    lw a0, 8(a0)
 ; RV32I-WITHFP-NEXT:    lw a7, 8(a7)
 ; RV32I-WITHFP-NEXT:    xor a4, a5, a4
 ; RV32I-WITHFP-NEXT:    xor a3, a6, a3
 ; RV32I-WITHFP-NEXT:    or a3, a3, a4
 ; RV32I-WITHFP-NEXT:    xor a0, a7, a0
 ; RV32I-WITHFP-NEXT:    xor a1, a2, a1
-; RV32I-WITHFP-NEXT:    or a0, a1, a0
 ; RV32I-WITHFP-NEXT:    or a0, a0, a3
+; RV32I-WITHFP-NEXT:    or a0, a1, a0
 ; RV32I-WITHFP-NEXT:    seqz a0, a0
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %j_bitcast = bitcast fp128 %j to i128
   %1 = icmp eq i128 %h, %j_bitcast
   %2 = zext i1 %1 to i32

 ; Check 2x*xlen values are aligned appropriately when passed on the stack
 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
 define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, i64 %i, i32 %j, [2 x i32] %k) nounwind {
 ; The i64 should be 8-byte aligned on the stack, but the two-element array
 ; should only be 4-byte aligned
 ; RV32I-FPELIM-LABEL: callee_aligned_stack:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lw a0, 0(a2)
-; RV32I-FPELIM-NEXT:    lw a1, 20(sp)
-; RV32I-FPELIM-NEXT:    lw a2, 0(sp)
-; RV32I-FPELIM-NEXT:    lw a3, 8(sp)
-; RV32I-FPELIM-NEXT:    lw a4, 16(sp)
-; RV32I-FPELIM-NEXT:    add a0, a0, a7
-; RV32I-FPELIM-NEXT:    add a0, a0, a2
-; RV32I-FPELIM-NEXT:    add a0, a0, a3
-; RV32I-FPELIM-NEXT:    add a0, a0, a4
+; RV32I-FPELIM-NEXT:    lw a1, 0(sp)
+; RV32I-FPELIM-NEXT:    lw a2, 8(sp)
+; RV32I-FPELIM-NEXT:    lw a3, 16(sp)
+; RV32I-FPELIM-NEXT:    lw a4, 20(sp)
+; RV32I-FPELIM-NEXT:    add a1, a7, a1
+; RV32I-FPELIM-NEXT:    add a1, a1, a2
+; RV32I-FPELIM-NEXT:    add a1, a1, a3
+; RV32I-FPELIM-NEXT:    add a1, a1, a4
 ; RV32I-FPELIM-NEXT:    add a0, a0, a1
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: callee_aligned_stack:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lw a0, 0(a2)
-; RV32I-WITHFP-NEXT:    lw a1, 20(s0)
-; RV32I-WITHFP-NEXT:    lw a2, 0(s0)
-; RV32I-WITHFP-NEXT:    lw a3, 8(s0)
-; RV32I-WITHFP-NEXT:    lw a4, 16(s0)
-; RV32I-WITHFP-NEXT:    add a0, a0, a7
-; RV32I-WITHFP-NEXT:    add a0, a0, a2
-; RV32I-WITHFP-NEXT:    add a0, a0, a3
-; RV32I-WITHFP-NEXT:    add a0, a0, a4
+; RV32I-WITHFP-NEXT:    lw a1, 0(s0)
+; RV32I-WITHFP-NEXT:    lw a2, 8(s0)
+; RV32I-WITHFP-NEXT:    lw a3, 16(s0)
+; RV32I-WITHFP-NEXT:    lw a4, 20(s0)
+; RV32I-WITHFP-NEXT:    add a1, a7, a1
+; RV32I-WITHFP-NEXT:    add a1, a1, a2
+; RV32I-WITHFP-NEXT:    add a1, a1, a3
+; RV32I-WITHFP-NEXT:    add a1, a1, a4
 ; RV32I-WITHFP-NEXT:    add a0, a0, a1
 ; RV32I-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 16
 ; RV32I-WITHFP-NEXT:    ret
   %1 = bitcast fp128 %c to i128
   %2 = trunc i128 %1 to i32
   %3 = add i32 %2, %g

llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

 define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f, i128 %g, i32 %h) nounwind {
 ; RV64I-LABEL: callee_many_scalars:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lw t0, 8(sp)
 ; RV64I-NEXT:    ld t1, 0(sp)
 ; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    srli a1, a1, 48
-; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    addw a0, a0, a2
-; RV64I-NEXT:    xor a1, a4, t1
-; RV64I-NEXT:    xor a2, a3, a7
-; RV64I-NEXT:    or a1, a2, a1
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    addw a0, a1, a0
+; RV64I-NEXT:    addw a1, a1, a2
+; RV64I-NEXT:    xor a2, a4, t1
+; RV64I-NEXT:    xor a3, a3, a7
+; RV64I-NEXT:    or a2, a3, a2
+; RV64I-NEXT:    seqz a2, a2
+; RV64I-NEXT:    addw a1, a2, a1
 ; RV64I-NEXT:    addw a0, a0, a5
 ; RV64I-NEXT:    addw a0, a0, a6
 ; RV64I-NEXT:    addw a0, a0, t0
+; RV64I-NEXT:    addw a0, a1, a0
 ; RV64I-NEXT:    ret
   %a_ext = zext i8 %a to i32
   %b_ext = zext i16 %b to i32
   %1 = add i32 %a_ext, %b_ext
   %2 = add i32 %1, %c
   %3 = icmp eq i128 %d, %g
   %4 = zext i1 %3 to i32
   %5 = add i32 %4, %2

 ; RV64I-NEXT:    ld a7, 8(a0)
 ; RV64I-NEXT:    ld a1, 16(a1)
 ; RV64I-NEXT:    ld a0, 16(a0)
 ; RV64I-NEXT:    xor a5, a6, a5
 ; RV64I-NEXT:    xor a4, a7, a4
 ; RV64I-NEXT:    or a4, a4, a5
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    xor a2, a3, a2
-; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a4
+; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
   %1 = icmp eq i256 %a, %b
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @caller_large_scalars() nounwind {

 ; RV64I-NEXT:    ld a6, 8(a7)
 ; RV64I-NEXT:    ld a0, 16(a0)
 ; RV64I-NEXT:    ld a7, 16(a7)
 ; RV64I-NEXT:    xor a4, a5, a4
 ; RV64I-NEXT:    xor a3, a6, a3
 ; RV64I-NEXT:    or a3, a3, a4
 ; RV64I-NEXT:    xor a0, a7, a0
 ; RV64I-NEXT:    xor a1, a2, a1
-; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    ret
   %1 = icmp eq i256 %h, %j
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
 
 define i64 @caller_large_scalars_exhausted_regs() nounwind {

 
 ; Check 2x*xlen values are aligned appropriately when passed on the stack
 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
 define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f, i64 %g, i64 %h, i128 %i, i64 %j, [2 x i64] %k) nounwind {
 ; The i128 should be 16-byte aligned on the stack, but the two-element array
 ; should only be 8-byte aligned
 ; RV64I-LABEL: callee_aligned_stack:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    ld a0, 40(sp)
-; RV64I-NEXT:    ld a1, 0(sp)
-; RV64I-NEXT:    ld a2, 16(sp)
-; RV64I-NEXT:    ld a3, 32(sp)
-; RV64I-NEXT:    add a5, a5, a7
-; RV64I-NEXT:    add a1, a5, a1
-; RV64I-NEXT:    add a1, a1, a2
-; RV64I-NEXT:    add a1, a1, a3
-; RV64I-NEXT:    add a0, a1, a0
+; RV64I-NEXT:    ld a0, 0(sp)
+; RV64I-NEXT:    ld a1, 16(sp)
+; RV64I-NEXT:    ld a2, 32(sp)
+; RV64I-NEXT:    ld a3, 40(sp)
+; RV64I-NEXT:    add a0, a7, a0
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    add a0, a0, a2
+; RV64I-NEXT:    add a0, a0, a3
+; RV64I-NEXT:    add a0, a5, a0
 ; RV64I-NEXT:    ret
   %f_trunc = trunc i128 %f to i64
   %1 = add i64 %f_trunc, %g
   %2 = add i64 %1, %h
   %3 = trunc i128 %i to i64
   %4 = add i64 %2, %3
   %5 = add i64 %4, %j
   %6 = extractvalue [2 x i64] %k, 0

llvm/test/CodeGen/RISCV/compress.ll

 ; different test file.
 
 define i32 @simple_arith(i32 %a, i32 %b) #0 {
 ; RV32IC-LABEL: <simple_arith>:
 ; RV32IC:         addi a2, a0, 1
 ; RV32IC-NEXT:    c.andi a2, 11
 ; RV32IC-NEXT:    c.slli a2, 7
 ; RV32IC-NEXT:    c.srai a1, 9
-; RV32IC-NEXT:    c.add a1, a2
 ; RV32IC-NEXT:    sub a0, a1, a0
+; RV32IC-NEXT:    c.add a0, a2
 ; RV32IC-NEXT:    c.jr ra
   %1 = add i32 %a, 1
   %2 = and i32 %1, 11
   %3 = shl i32 %2, 7
   %4 = ashr i32 %b, 9
   %5 = add i32 %3, %4
   %6 = sub i32 %5, %a
   ret i32 %6

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a0, fa0
 ; RV32IF-NEXT:    fmv.x.w a1, fa1
 ; RV32IF-NEXT:    lui a2, 524288
 ; RV32IF-NEXT:    and a1, a1, a2
 ; RV32IF-NEXT:    srli a1, a1, 16
 ; RV32IF-NEXT:    slli a0, a0, 17
 ; RV32IF-NEXT:    srli a0, a0, 17
-; RV32IF-NEXT:    or a0, a0, a1
-; RV32IF-NEXT:    lui a1, 1048560
+; RV32IF-NEXT:    lui a2, 1048560
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    fmv.w.x fa0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_demote_h_s:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    fmv.x.w a0, fa0
 ; RV32IFD-NEXT:    fmv.x.w a1, fa1
 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    srli a1, a1, 16
 ; RV32IFD-NEXT:    slli a0, a0, 17
 ; RV32IFD-NEXT:    srli a0, a0, 17
-; RV32IFD-NEXT:    or a0, a0, a1
-; RV32IFD-NEXT:    lui a1, 1048560
+; RV32IFD-NEXT:    lui a2, 1048560
+; RV32IFD-NEXT:    or a1, a1, a2
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    fmv.w.x fa0, a0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_demote_h_s:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.x.w a0, fa0
 ; RV64IFD-NEXT:    fmv.x.w a1, fa1
 ; RV64IFD-NEXT:    lui a2, 524288
 ; RV64IFD-NEXT:    and a1, a1, a2
 ; RV64IFD-NEXT:    srli a1, a1, 16
 ; RV64IFD-NEXT:    slli a0, a0, 49
 ; RV64IFD-NEXT:    srli a0, a0, 49
-; RV64IFD-NEXT:    or a0, a0, a1
-; RV64IFD-NEXT:    lui a1, 1048560
+; RV64IFD-NEXT:    lui a2, 1048560
+; RV64IFD-NEXT:    or a1, a1, a2
 ; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    fmv.w.x fa0, a0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IFZFH-LABEL: fold_demote_h_s:
 ; RV32IFZFH:       # %bb.0:
 ; RV32IFZFH-NEXT:    fcvt.h.s ft0, fa1
 ; RV32IFZFH-NEXT:    fsgnj.h fa0, fa0, ft0

 ; RV32IF-LABEL: fold_demote_h_d:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.x.w a0, fa0
 ; RV32IF-NEXT:    lui a2, 524288
 ; RV32IF-NEXT:    and a1, a1, a2
 ; RV32IF-NEXT:    srli a1, a1, 16
 ; RV32IF-NEXT:    slli a0, a0, 17
 ; RV32IF-NEXT:    srli a0, a0, 17
-; RV32IF-NEXT:    or a0, a0, a1
-; RV32IF-NEXT:    lui a1, 1048560
+; RV32IF-NEXT:    lui a2, 1048560
+; RV32IF-NEXT:    or a1, a1, a2
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    fmv.w.x fa0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV32IFD-LABEL: fold_demote_h_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    fsd fa1, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 12(sp)
 ; RV32IFD-NEXT:    fmv.x.w a1, fa0
 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    and a0, a0, a2
 ; RV32IFD-NEXT:    srli a0, a0, 16
 ; RV32IFD-NEXT:    slli a1, a1, 17
 ; RV32IFD-NEXT:    srli a1, a1, 17
+; RV32IFD-NEXT:    lui a2, 1048560
+; RV32IFD-NEXT:    or a0, a0, a2
 ; RV32IFD-NEXT:    or a0, a1, a0
-; RV32IFD-NEXT:    lui a1, 1048560
-; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    fmv.w.x fa0, a0
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fold_demote_h_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.x.d a0, fa1
 ; RV64IFD-NEXT:    fmv.x.w a1, fa0
 ; RV64IFD-NEXT:    slli a1, a1, 49
 ; RV64IFD-NEXT:    srli a1, a1, 49
 ; RV64IFD-NEXT:    srli a0, a0, 63
 ; RV64IFD-NEXT:    slli a0, a0, 63
 ; RV64IFD-NEXT:    srli a0, a0, 48
+; RV64IFD-NEXT:    lui a2, 1048560
+; RV64IFD-NEXT:    or a0, a0, a2
 ; RV64IFD-NEXT:    or a0, a1, a0
-; RV64IFD-NEXT:    lui a1, 1048560
-; RV64IFD-NEXT:    or a0, a0, a1
 ; RV64IFD-NEXT:    fmv.w.x fa0, a0
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IFZFH-LABEL: fold_demote_h_d:
 ; RV32IFZFH:       # %bb.0:
 ; RV32IFZFH-NEXT:    srli a1, a1, 16
 ; RV32IFZFH-NEXT:    fmv.h.x ft0, a1
 ; RV32IFZFH-NEXT:    fsgnj.h fa0, fa0, ft0

llvm/test/CodeGen/RISCV/div-by-constant.ll

 ; RV32-NEXT:    srli a6, a5, 2
 ; RV32-NEXT:    andi a5, a5, -4
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, -820
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: udiv64_constant_no_add:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a1, %hi(.LCPI2_0)
 ; RV64-NEXT:    ld a1, %lo(.LCPI2_0)(a1)
 ; RV64-NEXT:    mulhu a0, a0, a1

llvm/test/CodeGen/RISCV/div-pow2.ll

 ; RV32I-NEXT:    srli a3, a2, 1
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    slli a0, a1, 31
 ; RV32I-NEXT:    or a3, a3, a0
 ; RV32I-NEXT:    neg a0, a3
 ; RV32I-NEXT:    snez a2, a3
 ; RV32I-NEXT:    srai a1, a1, 1
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_negative_2:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srli a1, a0, 63
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 1
 ; RV64I-NEXT:    neg a0, a0

 ; RV32I-NEXT:    srli a3, a2, 11
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    slli a0, a1, 21
 ; RV32I-NEXT:    or a3, a3, a0
 ; RV32I-NEXT:    neg a0, a3
 ; RV32I-NEXT:    snez a2, a3
 ; RV32I-NEXT:    srai a1, a1, 11
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_negative_2048:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    srli a1, a1, 53
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 11

 ; RV32I-NEXT:    srli a3, a2, 12
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    slli a0, a1, 20
 ; RV32I-NEXT:    or a3, a3, a0
 ; RV32I-NEXT:    neg a0, a3
 ; RV32I-NEXT:    snez a2, a3
 ; RV32I-NEXT:    srai a1, a1, 12
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_negative_4096:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    srli a1, a1, 52
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 12

 ; RV32I-NEXT:    srli a3, a2, 16
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    slli a0, a1, 16
 ; RV32I-NEXT:    or a3, a3, a0
 ; RV32I-NEXT:    neg a0, a3
 ; RV32I-NEXT:    snez a2, a3
 ; RV32I-NEXT:    srai a1, a1, 16
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_negative_65536:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    srli a1, a1, 48
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 16
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    ret
 entry:
   %div = sdiv i64 %a, -65536
   ret i64 %div
 }
 
 define i64 @sdiv64_pow2_8589934592(i64 %a) {
 ; RV32I-LABEL: sdiv64_pow2_8589934592:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    srli a2, a1, 31
-; RV32I-NEXT:    add a2, a1, a2
-; RV32I-NEXT:    srai a1, a1, 31
-; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    add a1, a2, a0
+; RV32I-NEXT:    srai a3, a1, 31
+; RV32I-NEXT:    add a3, a0, a3
+; RV32I-NEXT:    sltu a0, a3, a0
+; RV32I-NEXT:    add a0, a2, a0
+; RV32I-NEXT:    add a1, a1, a0
 ; RV32I-NEXT:    srai a0, a1, 1
 ; RV32I-NEXT:    srai a1, a1, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_8589934592:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    srli a1, a1, 31
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 33
 ; RV64I-NEXT:    ret
 entry:
   %div = sdiv i64 %a, 8589934592 ; 2^33
   ret i64 %div
 }
 
 define i64 @sdiv64_pow2_negative_8589934592(i64 %a) {
 ; RV32I-LABEL: sdiv64_pow2_negative_8589934592:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    srli a2, a1, 31
-; RV32I-NEXT:    add a2, a1, a2
-; RV32I-NEXT:    srai a1, a1, 31
-; RV32I-NEXT:    add a1, a0, a1
-; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    srai a3, a1, 31
+; RV32I-NEXT:    add a3, a0, a3
+; RV32I-NEXT:    sltu a0, a3, a0
 ; RV32I-NEXT:    add a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    srai a0, a0, 1
 ; RV32I-NEXT:    snez a2, a0
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    neg a0, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sdiv64_pow2_negative_8589934592:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    srli a1, a1, 31
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 33
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    ret
 entry:
   %div = sdiv i64 %a, -8589934592 ; -2^33
   ret i64 %div
 }

llvm/test/CodeGen/RISCV/div.ll

 ; RV32IM-NEXT:    srli a6, a5, 2
 ; RV32IM-NEXT:    andi a5, a5, -4
 ; RV32IM-NEXT:    add a5, a5, a6
 ; RV32IM-NEXT:    sub a2, a2, a5
 ; RV32IM-NEXT:    sub a5, a0, a2
 ; RV32IM-NEXT:    addi a3, a3, -820
 ; RV32IM-NEXT:    mul a3, a5, a3
 ; RV32IM-NEXT:    mulhu a6, a5, a4
-; RV32IM-NEXT:    add a3, a6, a3
 ; RV32IM-NEXT:    sltu a0, a0, a2
 ; RV32IM-NEXT:    sub a1, a1, a0
-; RV32IM-NEXT:    mul a1, a1, a4
-; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    mul a0, a1, a4
+; RV32IM-NEXT:    add a0, a3, a0
+; RV32IM-NEXT:    add a1, a6, a0
 ; RV32IM-NEXT:    mul a0, a5, a4
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: udiv64_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, 5
 ; RV64I-NEXT:    tail __udivdi3@plt
 ;

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    call __fixunsdfti@plt
 ; RV32IF-NEXT:    lw a0, 16(sp)
 ; RV32IF-NEXT:    lw a1, 20(sp)
 ; RV32IF-NEXT:    lw a2, 12(sp)
 ; RV32IF-NEXT:    lw a3, 8(sp)
 ; RV32IF-NEXT:    or a4, a1, a0
 ; RV32IF-NEXT:    snez a4, a4
 ; RV32IF-NEXT:    addi a4, a4, -1
-; RV32IF-NEXT:    and a3, a4, a3
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    addi a1, a0, -1
 ; RV32IF-NEXT:    and a0, a1, a3
-; RV32IF-NEXT:    and a2, a4, a2
+; RV32IF-NEXT:    and a0, a0, a4
 ; RV32IF-NEXT:    and a1, a1, a2
+; RV32IF-NEXT:    and a1, a1, a4
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f64i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixunsdfti@plt
 ; RV64-NEXT:    snez a2, a1
 ; RV64-NEXT:    addi a2, a2, -1
-; RV64-NEXT:    and a0, a2, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
+; RV64-NEXT:    and a0, a0, a2
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 ;
 ; RV32IFD-LABEL: utest_f64i64_mm:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -32
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 32
 ; RV32IFD-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixunsdfti@plt
 ; RV32IFD-NEXT:    lw a0, 16(sp)
 ; RV32IFD-NEXT:    lw a1, 20(sp)
 ; RV32IFD-NEXT:    lw a2, 12(sp)
 ; RV32IFD-NEXT:    lw a3, 8(sp)
 ; RV32IFD-NEXT:    or a4, a1, a0
 ; RV32IFD-NEXT:    snez a4, a4
 ; RV32IFD-NEXT:    addi a4, a4, -1
-; RV32IFD-NEXT:    and a3, a4, a3
 ; RV32IFD-NEXT:    xori a0, a0, 1
 ; RV32IFD-NEXT:    or a0, a0, a1
 ; RV32IFD-NEXT:    seqz a0, a0
 ; RV32IFD-NEXT:    addi a1, a0, -1
 ; RV32IFD-NEXT:    and a0, a1, a3
-; RV32IFD-NEXT:    and a2, a4, a2
+; RV32IFD-NEXT:    and a0, a0, a4
 ; RV32IFD-NEXT:    and a1, a1, a2
+; RV32IFD-NEXT:    and a1, a1, a4
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
 entry:
   %conv = fptoui double %x to i128
   %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)
   %conv6 = trunc i128 %spec.store.select to i64
   ret i64 %conv6

 ; RV32-NEXT:    call __fixunssfti@plt
 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
 ; RV32-NEXT:    or a4, a1, a0
 ; RV32-NEXT:    snez a4, a4
 ; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a3, a4, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
-; RV32-NEXT:    and a2, a4, a2
+; RV32-NEXT:    and a0, a0, a4
 ; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    and a1, a1, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utest_f32i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call __fixunssfti@plt
 ; RV64-NEXT:    snez a2, a1
 ; RV64-NEXT:    addi a2, a2, -1
-; RV64-NEXT:    and a0, a2, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
+; RV64-NEXT:    and a0, a0, a2
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 entry:
   %conv = fptoui float %x to i128
   %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)
   %conv6 = trunc i128 %spec.store.select to i64
   ret i64 %conv6

 ; RV32-NEXT:    call __fixunssfti@plt
 ; RV32-NEXT:    lw a0, 16(sp)
 ; RV32-NEXT:    lw a1, 20(sp)
 ; RV32-NEXT:    lw a2, 12(sp)
 ; RV32-NEXT:    lw a3, 8(sp)
 ; RV32-NEXT:    or a4, a1, a0
 ; RV32-NEXT:    snez a4, a4
 ; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    and a3, a4, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    addi a1, a0, -1
 ; RV32-NEXT:    and a0, a1, a3
-; RV32-NEXT:    and a2, a4, a2
+; RV32-NEXT:    and a0, a0, a4
 ; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:    and a1, a1, a4
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: utesth_f16i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    fmv.x.w a0, fa0
 ; RV64-NEXT:    call __extendhfsf2@plt
 ; RV64-NEXT:    call __fixunssfti@plt
 ; RV64-NEXT:    snez a2, a1
 ; RV64-NEXT:    addi a2, a2, -1
-; RV64-NEXT:    and a0, a2, a0
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
+; RV64-NEXT:    and a0, a0, a2
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
 entry:
   %conv = fptoui half %x to i128
   %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)
   %conv6 = trunc i128 %spec.store.select to i64
   ret i64 %conv6

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

 ; CHECK-NOV-NEXT:    fmv.d fa0, fa1
 ; CHECK-NOV-NEXT:    call __fixunsdfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.d fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixunsdfti@plt
 ; CHECK-NOV-NEXT:    snez a2, a1
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a0, a2, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    and a0, a1, a0
+; CHECK-NOV-NEXT:    and a0, a0, a2
 ; CHECK-NOV-NEXT:    snez a1, s1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
 ; CHECK-NOV-NEXT:    addi s1, s1, -1
 ; CHECK-NOV-NEXT:    seqz a2, s1
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s0
 ; CHECK-NOV-NEXT:    and a1, a2, a1
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;

 ; CHECK-V-NEXT:    mv s1, a1
 ; CHECK-V-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
 ; CHECK-V-NEXT:    addi a0, sp, 48
 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixunsdfti@plt
 ; CHECK-V-NEXT:    snez a2, s1
 ; CHECK-V-NEXT:    addi a2, a2, -1
-; CHECK-V-NEXT:    and a2, a2, s0
 ; CHECK-V-NEXT:    addi s1, s1, -1
 ; CHECK-V-NEXT:    seqz a3, s1
 ; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    and a3, a3, s0
 ; CHECK-V-NEXT:    and a2, a3, a2
 ; CHECK-V-NEXT:    snez a3, a1
 ; CHECK-V-NEXT:    addi a3, a3, -1
-; CHECK-V-NEXT:    and a0, a3, a0
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
+; CHECK-V-NEXT:    and a0, a0, a3
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma

 ; CHECK-NOV-NEXT:    fmv.s fa0, fa1
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    mv s0, a0
 ; CHECK-NOV-NEXT:    mv s1, a1
 ; CHECK-NOV-NEXT:    fmv.s fa0, fs0
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    snez a2, a1
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a0, a2, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    and a0, a1, a0
+; CHECK-NOV-NEXT:    and a0, a0, a2
 ; CHECK-NOV-NEXT:    snez a1, s1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s0
 ; CHECK-NOV-NEXT:    addi s1, s1, -1
 ; CHECK-NOV-NEXT:    seqz a2, s1
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s0
 ; CHECK-NOV-NEXT:    and a1, a2, a1
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;

 ; CHECK-V-NEXT:    mv s1, a1
 ; CHECK-V-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
 ; CHECK-V-NEXT:    addi a0, sp, 48
 ; CHECK-V-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
 ; CHECK-V-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    snez a2, s1
 ; CHECK-V-NEXT:    addi a2, a2, -1
-; CHECK-V-NEXT:    and a2, a2, s0
 ; CHECK-V-NEXT:    addi s1, s1, -1
 ; CHECK-V-NEXT:    seqz a3, s1
 ; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    and a3, a3, s0
 ; CHECK-V-NEXT:    and a2, a3, a2
 ; CHECK-V-NEXT:    snez a3, a1
 ; CHECK-V-NEXT:    addi a3, a3, -1
-; CHECK-V-NEXT:    and a0, a3, a0
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
+; CHECK-V-NEXT:    and a0, a0, a3
 ; CHECK-V-NEXT:    sd a0, 24(sp)
 ; CHECK-V-NEXT:    sd a2, 32(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 24
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v8, (a0)
 ; CHECK-V-NEXT:    addi a0, sp, 32
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, tu, ma

 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    mv s1, a0
 ; CHECK-NOV-NEXT:    mv s2, a1
 ; CHECK-NOV-NEXT:    mv a0, s0
 ; CHECK-NOV-NEXT:    call __extendhfsf2@plt
 ; CHECK-NOV-NEXT:    call __fixunssfti@plt
 ; CHECK-NOV-NEXT:    snez a2, a1
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
-; CHECK-NOV-NEXT:    and a0, a2, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    and a0, a1, a0
+; CHECK-NOV-NEXT:    and a0, a0, a2
 ; CHECK-NOV-NEXT:    snez a1, s2
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
-; CHECK-NOV-NEXT:    and a1, a1, s1
 ; CHECK-NOV-NEXT:    addi s2, s2, -1
 ; CHECK-NOV-NEXT:    seqz a2, s2
 ; CHECK-NOV-NEXT:    addi a2, a2, -1
+; CHECK-NOV-NEXT:    and a2, a2, s1
 ; CHECK-NOV-NEXT:    and a1, a2, a1
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    addi sp, sp, 32
 ; CHECK-NOV-NEXT:    ret
 ;

 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    mv s1, a0
 ; CHECK-V-NEXT:    mv s2, a1
 ; CHECK-V-NEXT:    mv a0, s0
 ; CHECK-V-NEXT:    call __extendhfsf2@plt
 ; CHECK-V-NEXT:    call __fixunssfti@plt
 ; CHECK-V-NEXT:    snez a2, a1
 ; CHECK-V-NEXT:    addi a2, a2, -1
-; CHECK-V-NEXT:    and a0, a2, a0
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    and a0, a1, a0
+; CHECK-V-NEXT:    and a0, a0, a2
 ; CHECK-V-NEXT:    snez a1, s2
 ; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    and a1, a1, s1
 ; CHECK-V-NEXT:    addi s2, s2, -1
 ; CHECK-V-NEXT:    seqz a2, s2
 ; CHECK-V-NEXT:    addi a2, a2, -1
+; CHECK-V-NEXT:    and a2, a2, s1
 ; CHECK-V-NEXT:    and a1, a2, a1
 ; CHECK-V-NEXT:    sd a1, 8(sp)
 ; CHECK-V-NEXT:    sd a0, 0(sp)
 ; CHECK-V-NEXT:    addi a0, sp, 8
 ; CHECK-V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-V-NEXT:    vle64.v v9, (a0)
 ; CHECK-V-NEXT:    mv a0, sp
 ; CHECK-V-NEXT:    vle64.v v8, (a0)

llvm/test/CodeGen/RISCV/iabs.ll

 ; RV32I-NEXT:  .LBB8_2:
 ; RV32I-NEXT:    lw a1, 8(a1)
 ; RV32I-NEXT:    bgez a4, .LBB8_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    neg a7, a1
 ; RV32I-NEXT:    sltu t0, a7, a6
 ; RV32I-NEXT:    snez a1, a1
 ; RV32I-NEXT:    add a1, a4, a1
-; RV32I-NEXT:    add a1, a1, t0
-; RV32I-NEXT:    neg a4, a1
+; RV32I-NEXT:    neg a4, t0
+; RV32I-NEXT:    sub a4, a4, a1
 ; RV32I-NEXT:    sub a1, a7, a6
 ; RV32I-NEXT:    add a2, a2, a5
 ; RV32I-NEXT:    neg a2, a2
 ; RV32I-NEXT:    neg a3, a3
 ; RV32I-NEXT:  .LBB8_4:
 ; RV32I-NEXT:    sw a3, 0(a0)
 ; RV32I-NEXT:    sw a1, 8(a0)
 ; RV32I-NEXT:    sw a2, 4(a0)

 ; RV32ZBB-NEXT:  .LBB8_2:
 ; RV32ZBB-NEXT:    lw a1, 8(a1)
 ; RV32ZBB-NEXT:    bgez a4, .LBB8_4
 ; RV32ZBB-NEXT:  # %bb.3:
 ; RV32ZBB-NEXT:    neg a7, a1
 ; RV32ZBB-NEXT:    sltu t0, a7, a6
 ; RV32ZBB-NEXT:    snez a1, a1
 ; RV32ZBB-NEXT:    add a1, a4, a1
-; RV32ZBB-NEXT:    add a1, a1, t0
-; RV32ZBB-NEXT:    neg a4, a1
+; RV32ZBB-NEXT:    neg a4, t0
+; RV32ZBB-NEXT:    sub a4, a4, a1
 ; RV32ZBB-NEXT:    sub a1, a7, a6
 ; RV32ZBB-NEXT:    add a2, a2, a5
 ; RV32ZBB-NEXT:    neg a2, a2
 ; RV32ZBB-NEXT:    neg a3, a3
 ; RV32ZBB-NEXT:  .LBB8_4:
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
 ; RV32ZBB-NEXT:    sw a1, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 4(a0)

 ; RV32I-NEXT:  .LBB9_2:
 ; RV32I-NEXT:    lw a1, 8(a1)
 ; RV32I-NEXT:    bgez a4, .LBB9_4
 ; RV32I-NEXT:  # %bb.3:
 ; RV32I-NEXT:    neg a7, a1
 ; RV32I-NEXT:    sltu t0, a7, a6
 ; RV32I-NEXT:    snez a1, a1
 ; RV32I-NEXT:    add a1, a4, a1
-; RV32I-NEXT:    add a1, a1, t0
-; RV32I-NEXT:    neg a4, a1
+; RV32I-NEXT:    neg a4, t0
+; RV32I-NEXT:    sub a4, a4, a1
 ; RV32I-NEXT:    sub a1, a7, a6
 ; RV32I-NEXT:    add a2, a2, a5
 ; RV32I-NEXT:    neg a2, a2
 ; RV32I-NEXT:    neg a3, a3
 ; RV32I-NEXT:  .LBB9_4:
 ; RV32I-NEXT:    sw a3, 0(a0)
 ; RV32I-NEXT:    sw a1, 8(a0)
 ; RV32I-NEXT:    sw a2, 4(a0)

 ; RV32ZBB-NEXT:  .LBB9_2:
 ; RV32ZBB-NEXT:    lw a1, 8(a1)
 ; RV32ZBB-NEXT:    bgez a4, .LBB9_4
 ; RV32ZBB-NEXT:  # %bb.3:
 ; RV32ZBB-NEXT:    neg a7, a1
 ; RV32ZBB-NEXT:    sltu t0, a7, a6
 ; RV32ZBB-NEXT:    snez a1, a1
 ; RV32ZBB-NEXT:    add a1, a4, a1
-; RV32ZBB-NEXT:    add a1, a1, t0
-; RV32ZBB-NEXT:    neg a4, a1
+; RV32ZBB-NEXT:    neg a4, t0
+; RV32ZBB-NEXT:    sub a4, a4, a1
 ; RV32ZBB-NEXT:    sub a1, a7, a6
 ; RV32ZBB-NEXT:    add a2, a2, a5
 ; RV32ZBB-NEXT:    neg a2, a2
 ; RV32ZBB-NEXT:    neg a3, a3
 ; RV32ZBB-NEXT:  .LBB9_4:
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
 ; RV32ZBB-NEXT:    sw a1, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 4(a0)

llvm/test/CodeGen/RISCV/machine-combiner.ll

 ; CHECK-NEXT:    fsub.d ft1, fa3, fa2
 ; CHECK-NEXT:    fadd.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fadd nsz reassoc double %a0, %a1
   %t1 = fsub nsz reassoc double %a2, %t0
   %t2 = fsub nsz reassoc double %a3, %t1
   ret double %t2
 }
+
+define i8 @test_reassoc_add_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
+; CHECK-LABEL: test_reassoc_add_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a2, a3
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i8 %a0, %a1
+  %t1 = add i8 %t0, %a2
+  %t2 = add i8 %t1, %a3
+  ret i8 %t2
+}
+
+define i16 @test_reassoc_add_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
+; CHECK-LABEL: test_reassoc_add_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a2, a3
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i16 %a0, %a1
+  %t1 = add i16 %t0, %a2
+  %t2 = add i16 %t1, %a3
+  ret i16 %t2
+}
+
+define i32 @test_reassoc_add_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_add_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addw a0, a0, a1
+; CHECK-NEXT:    addw a2, a2, a3
+; CHECK-NEXT:    addw a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i32 %a0, %a1
+  %t1 = add i32 %t0, %a2
+  %t2 = add i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_add_i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_add_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a2, a3
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i64 %a0, %a1
+  %t1 = add i64 %t0, %a2
+  %t2 = add i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i32 @test_reassoc_add_sub_i32_1(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addw a0, a0, a1
+; CHECK-NEXT:    subw a2, a2, a3
+; CHECK-NEXT:    subw a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i32 %a0, %a1
+  %t1 = sub i32 %t0, %a2
+  %t2 = add i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i32 @test_reassoc_add_sub_i32_2(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addw a0, a0, a1
+; CHECK-NEXT:    subw a2, a2, a3
+; CHECK-NEXT:    addw a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i32 %a0, %a1
+  %t1 = add i32 %t0, %a2
+  %t2 = sub i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i32 @test_reassoc_add_sub_i32_3(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addw a0, a0, a1
+; CHECK-NEXT:    addw a2, a2, a3
+; CHECK-NEXT:    subw a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i32 %a0, %a1
+  %t1 = sub i32 %t0, %a2
+  %t2 = sub i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_add_sub_i64_1(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    sub a2, a2, a3
+; CHECK-NEXT:    sub a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i64 %a0, %a1
+  %t1 = sub i64 %t0, %a2
+  %t2 = add i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i64 @test_reassoc_add_sub_i64_2(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    sub a2, a2, a3
+; CHECK-NEXT:    add a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i64 %a0, %a1
+  %t1 = add i64 %t0, %a2
+  %t2 = sub i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i64 @test_reassoc_add_sub_i64_3(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_add_sub_i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a0, a1
+; CHECK-NEXT:    add a2, a2, a3
+; CHECK-NEXT:    sub a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = add i64 %a0, %a1
+  %t1 = sub i64 %t0, %a2
+  %t2 = sub i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i8 @test_reassoc_and_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
+; CHECK-LABEL: test_reassoc_and_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    and a2, a2, a3
+; CHECK-NEXT:    and a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = and i8 %a0, %a1
+  %t1 = and i8 %t0, %a2
+  %t2 = and i8 %t1, %a3
+  ret i8 %t2
+}
+
+define i16 @test_reassoc_and_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
+; CHECK-LABEL: test_reassoc_and_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    and a2, a2, a3
+; CHECK-NEXT:    and a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = and i16 %a0, %a1
+  %t1 = and i16 %t0, %a2
+  %t2 = and i16 %t1, %a3
+  ret i16 %t2
+}
+
+define i32 @test_reassoc_and_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_and_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    and a2, a2, a3
+; CHECK-NEXT:    and a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = and i32 %a0, %a1
+  %t1 = and i32 %t0, %a2
+  %t2 = and i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_and_i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_and_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    and a2, a2, a3
+; CHECK-NEXT:    and a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = and i64 %a0, %a1
+  %t1 = and i64 %t0, %a2
+  %t2 = and i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i8 @test_reassoc_or_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
+; CHECK-LABEL: test_reassoc_or_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a2, a2, a3
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = or i8 %a0, %a1
+  %t1 = or i8 %t0, %a2
+  %t2 = or i8 %t1, %a3
+  ret i8 %t2
+}
+
+define i16 @test_reassoc_or_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
+; CHECK-LABEL: test_reassoc_or_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a2, a2, a3
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = or i16 %a0, %a1
+  %t1 = or i16 %t0, %a2
+  %t2 = or i16 %t1, %a3
+  ret i16 %t2
+}
+
+define i32 @test_reassoc_or_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_or_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a2, a2, a3
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = or i32 %a0, %a1
+  %t1 = or i32 %t0, %a2
+  %t2 = or i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_or_i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_or_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    or a2, a2, a3
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = or i64 %a0, %a1
+  %t1 = or i64 %t0, %a2
+  %t2 = or i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i8 @test_reassoc_xor_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
+; CHECK-LABEL: test_reassoc_xor_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    xor a2, a2, a3
+; CHECK-NEXT:    xor a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = xor i8 %a0, %a1
+  %t1 = xor i8 %t0, %a2
+  %t2 = xor i8 %t1, %a3
+  ret i8 %t2
+}
+
+define i16 @test_reassoc_xor_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
+; CHECK-LABEL: test_reassoc_xor_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    xor a2, a2, a3
+; CHECK-NEXT:    xor a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = xor i16 %a0, %a1
+  %t1 = xor i16 %t0, %a2
+  %t2 = xor i16 %t1, %a3
+  ret i16 %t2
+}
+
+define i32 @test_reassoc_xor_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_xor_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    xor a2, a2, a3
+; CHECK-NEXT:    xor a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = xor i32 %a0, %a1
+  %t1 = xor i32 %t0, %a2
+  %t2 = xor i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_xor_i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_xor_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xor a0, a0, a1
+; CHECK-NEXT:    xor a2, a2, a3
+; CHECK-NEXT:    xor a0, a0, a2
+; CHECK-NEXT:    ret
+  %t0 = xor i64 %a0, %a1
+  %t1 = xor i64 %t0, %a2
+  %t2 = xor i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i8 @test_reassoc_mul_i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3) {
+; CHECK-LABEL: test_reassoc_mul_i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    mul a1, a2, a3
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
+  %t0 = mul i8 %a0, %a1
+  %t1 = mul i8 %t0, %a2
+  %t2 = mul i8 %t1, %a3
+  ret i8 %t2
+}
+
+define i16 @test_reassoc_mul_i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3) {
+; CHECK-LABEL: test_reassoc_mul_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    mul a1, a2, a3
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
+  %t0 = mul i16 %a0, %a1
+  %t1 = mul i16 %t0, %a2
+  %t2 = mul i16 %t1, %a3
+  ret i16 %t2
+}
+
+define i32 @test_reassoc_mul_i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
+; CHECK-LABEL: test_reassoc_mul_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mulw a0, a0, a1
+; CHECK-NEXT:    mulw a1, a2, a3
+; CHECK-NEXT:    mulw a0, a0, a1
+; CHECK-NEXT:    ret
+  %t0 = mul i32 %a0, %a1
+  %t1 = mul i32 %t0, %a2
+  %t2 = mul i32 %t1, %a3
+  ret i32 %t2
+}
+
+define i64 @test_reassoc_mul_i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+; CHECK-LABEL: test_reassoc_mul_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    mul a1, a2, a3
+; CHECK-NEXT:    mul a0, a0, a1
+; CHECK-NEXT:    ret
+  %t0 = mul i64 %a0, %a1
+  %t1 = mul i64 %t0, %a2
+  %t2 = mul i64 %t1, %a3
+  ret i64 %t2
+}

llvm/test/CodeGen/RISCV/mul.ll

 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul64:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    mul a3, a0, a3
 ; RV32IM-NEXT:    mulhu a4, a0, a2
-; RV32IM-NEXT:    add a3, a4, a3
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    add a1, a4, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: mul64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    tail __muldi3@plt
 ;
 ; RV64IM-LABEL: mul64:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, %b
   ret i64 %1
 }
 
 define i64 @mul64_constant(i64 %a) nounwind {
 ; RV32I-LABEL: mul64_constant:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a3, a0, 2
 ; RV32I-NEXT:    add a2, a3, a0
 ; RV32I-NEXT:    sltu a3, a2, a3
 ; RV32I-NEXT:    srli a0, a0, 30
 ; RV32I-NEXT:    slli a4, a1, 2
 ; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    add a1, a0, a3
+; RV32I-NEXT:    add a1, a1, a3
+; RV32I-NEXT:    add a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mul64_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, 5
 ; RV32IM-NEXT:    mulhu a2, a0, a2
 ; RV32IM-NEXT:    slli a3, a1, 2
-; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    add a1, a2, a1
+; RV32IM-NEXT:    add a1, a1, a3
 ; RV32IM-NEXT:    slli a2, a0, 2
 ; RV32IM-NEXT:    add a0, a2, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: mul64_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 2
 ; RV64I-NEXT:    add a0, a1, a0

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    slli a2, a0, 2
 ; RV32I-NEXT:    add a3, a2, a0
 ; RV32I-NEXT:    sltu a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 30
 ; RV32I-NEXT:    slli a3, a1, 2
 ; RV32I-NEXT:    or a0, a3, a0
+; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mulhs_positive_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a1, 5
 ; RV32IM-NEXT:    mulh a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    slli a2, a0, 2
 ; RV32I-NEXT:    add a3, a2, a0
 ; RV32I-NEXT:    sltu a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 30
 ; RV32I-NEXT:    slli a4, a1, 2
 ; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    snez a1, a3
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    snez a2, a3
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sub a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: mulhs_negative_constant:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a1, -5
 ; RV32IM-NEXT:    mulh a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: mulhs_negative_constant:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    slli a1, a0, 2
-; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: mulhs_negative_constant:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    sext.w a0, a0
 ; RV64IM-NEXT:    slli a1, a0, 2
-; RV64IM-NEXT:    add a0, a1, a0
 ; RV64IM-NEXT:    neg a0, a0
+; RV64IM-NEXT:    sub a0, a0, a1
 ; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sext i32 %a to i64
   %2 = mul i64 %1, -5
   %3 = lshr i64 %2, 32
   %4 = trunc i64 %3 to i32
   ret i32 %4
 }

 ; RV32I-LABEL: muli64_p65:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a3, a0, 6
 ; RV32I-NEXT:    add a2, a3, a0
 ; RV32I-NEXT:    sltu a3, a2, a3
 ; RV32I-NEXT:    srli a0, a0, 26
 ; RV32I-NEXT:    slli a4, a1, 6
 ; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    add a1, a0, a3
+; RV32I-NEXT:    add a1, a1, a3
+; RV32I-NEXT:    add a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p65:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, 65
 ; RV32IM-NEXT:    mulhu a2, a0, a2
 ; RV32IM-NEXT:    slli a3, a1, 6
-; RV32IM-NEXT:    add a1, a3, a1
 ; RV32IM-NEXT:    add a1, a2, a1
+; RV32IM-NEXT:    add a1, a1, a3
 ; RV32IM-NEXT:    slli a2, a0, 6
 ; RV32IM-NEXT:    add a0, a2, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_p65:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 6
 ; RV64I-NEXT:    add a0, a1, a0

 define i64 @muli64_p63(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_p63:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a2, a0, 6
 ; RV32I-NEXT:    sltu a3, a2, a0
 ; RV32I-NEXT:    srli a4, a0, 26
 ; RV32I-NEXT:    slli a5, a1, 6
 ; RV32I-NEXT:    or a4, a5, a4
+; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    sub a1, a4, a1
-; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p63:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, 63
 ; RV32IM-NEXT:    mulhu a2, a0, a2
 ; RV32IM-NEXT:    slli a3, a1, 6
-; RV32IM-NEXT:    sub a1, a3, a1
-; RV32IM-NEXT:    add a1, a2, a1
+; RV32IM-NEXT:    sub a1, a2, a1
+; RV32IM-NEXT:    add a1, a1, a3
 ; RV32IM-NEXT:    slli a2, a0, 6
 ; RV32IM-NEXT:    sub a0, a2, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_p63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 6
 ; RV64I-NEXT:    sub a0, a1, a0
; RV64IM-NEXT:    ret
   %1 = mul i32 %a, -63
   ret i32 %1
 }
 
 define i32 @muli32_m65(i32 %a) nounwind {
 ; RV32I-LABEL: muli32_m65:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a1, a0, 6
-; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli32_m65:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a1, a0, 6
-; RV32IM-NEXT:    add a0, a1, a0
 ; RV32IM-NEXT:    neg a0, a0
+; RV32IM-NEXT:    sub a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli32_m65:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slliw a1, a0, 6
-; RV64I-NEXT:    addw a0, a1, a0
 ; RV64I-NEXT:    negw a0, a0
+; RV64I-NEXT:    subw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli32_m65:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slliw a1, a0, 6
-; RV64IM-NEXT:    addw a0, a1, a0
 ; RV64IM-NEXT:    negw a0, a0
+; RV64IM-NEXT:    subw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, -65
   ret i32 %1
 }
 
 define i64 @muli64_m63(i64 %a) nounwind {
 ; RV32I-LABEL: muli64_m63:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a2, a0, 6
 ; RV32I-NEXT:    sltu a3, a0, a2
 ; RV32I-NEXT:    srli a4, a0, 26
 ; RV32I-NEXT:    slli a5, a1, 6
 ; RV32I-NEXT:    or a4, a5, a4
-; RV32I-NEXT:    sub a1, a1, a4
+; RV32I-NEXT:    add a3, a4, a3
 ; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m63:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a2, a1, 6
 ; RV32IM-NEXT:    sub a1, a1, a2
 ; RV32IM-NEXT:    li a2, -63
 ; RV32IM-NEXT:    mulhu a2, a0, a2
-; RV32IM-NEXT:    sub a2, a2, a0
-; RV32IM-NEXT:    add a1, a2, a1
+; RV32IM-NEXT:    sub a1, a0, a1
+; RV32IM-NEXT:    sub a1, a2, a1
 ; RV32IM-NEXT:    slli a2, a0, 6
 ; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 6
 ; RV64I-NEXT:    sub a0, a0, a1

 ; RV32I-LABEL: muli64_m65:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a2, a0, 6
 ; RV32I-NEXT:    add a3, a2, a0
 ; RV32I-NEXT:    sltu a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 26
 ; RV32I-NEXT:    slli a4, a1, 6
 ; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    add a0, a0, a2
-; RV32I-NEXT:    snez a1, a3
-; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    neg a1, a0
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    snez a2, a3
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sub a1, a1, a0
 ; RV32I-NEXT:    neg a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m65:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    slli a2, a1, 6
 ; RV32IM-NEXT:    add a1, a2, a1
 ; RV32IM-NEXT:    li a2, -65
 ; RV32IM-NEXT:    mulhu a2, a0, a2
-; RV32IM-NEXT:    sub a2, a2, a0
+; RV32IM-NEXT:    add a1, a0, a1
 ; RV32IM-NEXT:    sub a1, a2, a1
 ; RV32IM-NEXT:    slli a2, a0, 6
-; RV32IM-NEXT:    add a0, a2, a0
 ; RV32IM-NEXT:    neg a0, a0
+; RV32IM-NEXT:    sub a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m65:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 6
-; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    sub a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli64_m65:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a1, a0, 6
-; RV64IM-NEXT:    add a0, a1, a0
 ; RV64IM-NEXT:    neg a0, a0
+; RV64IM-NEXT:    sub a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = mul i64 %a, -65
   ret i64 %1
 }
 
 define i32 @muli32_p384(i32 %a) nounwind {
 ; RV32I-LABEL: muli32_p384:
 ; RV32I:       # %bb.0:

 ; RV32I-LABEL: muli64_p4352:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a0, 24
 ; RV32I-NEXT:    slli a3, a1, 8
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a3, a0, 20
 ; RV32I-NEXT:    slli a1, a1, 12
 ; RV32I-NEXT:    or a1, a1, a3
-; RV32I-NEXT:    add a1, a1, a2
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    slli a3, a0, 12
-; RV32I-NEXT:    add a0, a3, a2
-; RV32I-NEXT:    sltu a2, a0, a3
+; RV32I-NEXT:    slli a3, a0, 8
+; RV32I-NEXT:    slli a4, a0, 12
+; RV32I-NEXT:    add a0, a4, a3
+; RV32I-NEXT:    sltu a3, a0, a4
+; RV32I-NEXT:    add a2, a2, a3
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p4352:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, 17
 ; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2

 ; RV32I-LABEL: muli64_p3840:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a0, 24
 ; RV32I-NEXT:    slli a3, a1, 8
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a3, a0, 20
 ; RV32I-NEXT:    slli a1, a1, 12
 ; RV32I-NEXT:    or a1, a1, a3
-; RV32I-NEXT:    sub a1, a1, a2
-; RV32I-NEXT:    slli a2, a0, 8
+; RV32I-NEXT:    slli a3, a0, 8
 ; RV32I-NEXT:    slli a0, a0, 12
-; RV32I-NEXT:    sltu a3, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a0, a0, a2
+; RV32I-NEXT:    sltu a4, a0, a3
+; RV32I-NEXT:    add a2, a2, a4
+; RV32I-NEXT:    sub a1, a1, a2
+; RV32I-NEXT:    sub a0, a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_p3840:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, 15
 ; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2

 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m4352:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, -17
 ; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
-; RV32IM-NEXT:    sub a3, a3, a0
-; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    sub a1, a0, a1
+; RV32IM-NEXT:    sub a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m4352:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a1, -17
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    tail __muldi3@plt

 ; RV32I-LABEL: muli64_m3840:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a0, 20
 ; RV32I-NEXT:    slli a3, a1, 12
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a3, a0, 24
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a3
-; RV32I-NEXT:    sub a1, a1, a2
-; RV32I-NEXT:    slli a2, a0, 12
+; RV32I-NEXT:    slli a3, a0, 12
 ; RV32I-NEXT:    slli a0, a0, 8
-; RV32I-NEXT:    sltu a3, a0, a2
-; RV32I-NEXT:    sub a1, a1, a3
-; RV32I-NEXT:    sub a0, a0, a2
+; RV32I-NEXT:    sltu a4, a0, a3
+; RV32I-NEXT:    add a2, a2, a4
+; RV32I-NEXT:    sub a1, a1, a2
+; RV32I-NEXT:    sub a0, a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV32IM-LABEL: muli64_m3840:
 ; RV32IM:       # %bb.0:
 ; RV32IM-NEXT:    li a2, -15
 ; RV32IM-NEXT:    slli a2, a2, 8
 ; RV32IM-NEXT:    mul a1, a1, a2
 ; RV32IM-NEXT:    mulhu a3, a0, a2
-; RV32IM-NEXT:    sub a3, a3, a0
-; RV32IM-NEXT:    add a1, a3, a1
+; RV32IM-NEXT:    sub a1, a0, a1
+; RV32IM-NEXT:    sub a1, a3, a1
 ; RV32IM-NEXT:    mul a0, a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli64_m3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 12
 ; RV64I-NEXT:    slli a0, a0, 8
 ; RV64I-NEXT:    sub a0, a0, a1

 ; RV32I-NEXT:    lw a6, 0(a1)
 ; RV32I-NEXT:    lw a5, 12(a1)
 ; RV32I-NEXT:    srli a1, a4, 20
 ; RV32I-NEXT:    slli a2, a3, 12
 ; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    srli a2, a4, 24
 ; RV32I-NEXT:    slli a7, a3, 8
 ; RV32I-NEXT:    or a2, a7, a2
-; RV32I-NEXT:    sltu t0, a2, a1
-; RV32I-NEXT:    srli a7, a3, 20
+; RV32I-NEXT:    sltu a7, a2, a1
+; RV32I-NEXT:    srli t0, a3, 20
 ; RV32I-NEXT:    slli t1, a5, 12
-; RV32I-NEXT:    or a7, t1, a7
+; RV32I-NEXT:    or t0, t1, t0
 ; RV32I-NEXT:    srli a3, a3, 24
 ; RV32I-NEXT:    slli a5, a5, 8
-; RV32I-NEXT:    or a3, a5, a3
-; RV32I-NEXT:    sub t1, a3, a7
+; RV32I-NEXT:    or t1, a5, a3
+; RV32I-NEXT:    add t0, t0, a7
 ; RV32I-NEXT:    srli a3, a6, 20
 ; RV32I-NEXT:    slli a5, a4, 12
 ; RV32I-NEXT:    or a3, a5, a3
 ; RV32I-NEXT:    srli a5, a6, 24
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    or a5, a4, a5
 ; RV32I-NEXT:    slli a4, a6, 12
 ; RV32I-NEXT:    slli a6, a6, 8

 ; RV32IM-NEXT:    mul t5, a3, a5
 ; RV32IM-NEXT:    sub t5, t5, a4
 ; RV32IM-NEXT:    add t6, t4, t5
 ; RV32IM-NEXT:    sltu s0, t6, t4
 ; RV32IM-NEXT:    neg s1, a1
 ; RV32IM-NEXT:    sltu t4, t4, s1
 ; RV32IM-NEXT:    sltu a7, t1, a7
 ; RV32IM-NEXT:    mulhu t1, a1, t2
-; RV32IM-NEXT:    add a7, t1, a7
 ; RV32IM-NEXT:    add a7, a7, t4
 ; RV32IM-NEXT:    sltu t0, t5, t0
 ; RV32IM-NEXT:    mul a2, a2, a5
-; RV32IM-NEXT:    mulhu t1, a3, a5
-; RV32IM-NEXT:    sub a3, t1, a3
-; RV32IM-NEXT:    add a2, a3, a2
-; RV32IM-NEXT:    sub a3, t3, a4
-; RV32IM-NEXT:    sub a3, a3, a1
-; RV32IM-NEXT:    add a2, a3, a2
-; RV32IM-NEXT:    add a2, a2, t0
-; RV32IM-NEXT:    add a2, a7, a2
-; RV32IM-NEXT:    add a2, a2, s0
-; RV32IM-NEXT:    mul a1, a4, a5
-; RV32IM-NEXT:    sw a1, 0(a0)
+; RV32IM-NEXT:    mulhu t2, a3, a5
+; RV32IM-NEXT:    sub a3, a3, a2
+; RV32IM-NEXT:    sub a2, t2, a3
+; RV32IM-NEXT:    add a1, a4, a1
+; RV32IM-NEXT:    sub a1, a1, a2
+; RV32IM-NEXT:    sub a1, a1, t0
+; RV32IM-NEXT:    sub a1, t3, a1
+; RV32IM-NEXT:    add a1, a7, a1
+; RV32IM-NEXT:    add a1, a1, s0
+; RV32IM-NEXT:    add a1, t1, a1
+; RV32IM-NEXT:    mul a2, a4, a5
+; RV32IM-NEXT:    sw a2, 0(a0)
 ; RV32IM-NEXT:    sw a6, 4(a0)
 ; RV32IM-NEXT:    sw t6, 8(a0)
-; RV32IM-NEXT:    sw a2, 12(a0)
+; RV32IM-NEXT:    sw a1, 12(a0)
 ; RV32IM-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32IM-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli128_m3840:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a2, a0, 52
 ; RV64I-NEXT:    slli a3, a1, 12
 ; RV64I-NEXT:    or a2, a3, a2
 ; RV64I-NEXT:    srli a3, a0, 56
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a1, a1, a3
-; RV64I-NEXT:    sub a1, a1, a2
-; RV64I-NEXT:    slli a2, a0, 12
+; RV64I-NEXT:    slli a3, a0, 12
 ; RV64I-NEXT:    slli a0, a0, 8
-; RV64I-NEXT:    sltu a3, a0, a2
-; RV64I-NEXT:    sub a1, a1, a3
-; RV64I-NEXT:    sub a0, a0, a2
+; RV64I-NEXT:    sltu a4, a0, a3
+; RV64I-NEXT:    add a2, a2, a4
+; RV64I-NEXT:    sub a1, a1, a2
+; RV64I-NEXT:    sub a0, a0, a3
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli128_m3840:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    li a2, -15
 ; RV64IM-NEXT:    slli a2, a2, 8
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    mulhu a3, a0, a2
-; RV64IM-NEXT:    sub a3, a3, a0
-; RV64IM-NEXT:    add a1, a3, a1
+; RV64IM-NEXT:    sub a1, a0, a1
+; RV64IM-NEXT:    sub a1, a3, a1
 ; RV64IM-NEXT:    mul a0, a0, a2
 ; RV64IM-NEXT:    ret
   %1 = mul i128 %a, -3840
   ret i128 %1
 }
 
 define i128 @muli128_m63(i128 %a) nounwind {
 ; RV32I-LABEL: muli128_m63:

 ; RV32I-NEXT:    or t1, t2, t1
 ; RV32I-NEXT:    sub t2, a7, t1
 ; RV32I-NEXT:    sltu t3, t2, t0
 ; RV32I-NEXT:    sltu t1, a7, t1
 ; RV32I-NEXT:    srli a7, a7, 26
 ; RV32I-NEXT:    slli t4, a5, 6
 ; RV32I-NEXT:    or a7, t4, a7
 ; RV32I-NEXT:    sub a5, a5, a7
+; RV32I-NEXT:    add t1, t1, t3
 ; RV32I-NEXT:    sub a5, a5, t1
-; RV32I-NEXT:    sub a5, a5, t3
 ; RV32I-NEXT:    sub a7, t2, t0
 ; RV32I-NEXT:    sub a3, a3, a6
 ; RV32I-NEXT:    sub a3, a3, a4
 ; RV32I-NEXT:    sub a2, a2, a1
 ; RV32I-NEXT:    sw a2, 0(a0)
 ; RV32I-NEXT:    sw a3, 4(a0)
 ; RV32I-NEXT:    sw a7, 8(a0)
 ; RV32I-NEXT:    sw a5, 12(a0)

 ; RV32IM-NEXT:    neg t0, a3
 ; RV32IM-NEXT:    sltu t1, a6, t0
 ; RV32IM-NEXT:    li t2, -1
 ; RV32IM-NEXT:    mulhu t3, a3, t2
 ; RV32IM-NEXT:    add t1, t3, t1
 ; RV32IM-NEXT:    add t1, a7, t1
 ; RV32IM-NEXT:    sub t4, t1, a4
 ; RV32IM-NEXT:    slli t5, a1, 6
-; RV32IM-NEXT:    sub t5, t5, a1
-; RV32IM-NEXT:    add t5, t5, a3
+; RV32IM-NEXT:    sub t6, a1, a3
+; RV32IM-NEXT:    sub t5, t5, t6
 ; RV32IM-NEXT:    sub t6, t4, t5
 ; RV32IM-NEXT:    sltu s0, t6, t4
 ; RV32IM-NEXT:    neg s1, a4
 ; RV32IM-NEXT:    sltu t4, t4, s1
 ; RV32IM-NEXT:    sltu a7, t1, a7
 ; RV32IM-NEXT:    mulhu t1, a4, t2
-; RV32IM-NEXT:    add a7, t1, a7
 ; RV32IM-NEXT:    add a7, a7, t4
-; RV32IM-NEXT:    slli t1, a2, 6
-; RV32IM-NEXT:    sub a2, a2, t1
+; RV32IM-NEXT:    slli t2, a2, 6
+; RV32IM-NEXT:    sub a2, a2, t2
 ; RV32IM-NEXT:    mulhu a5, a1, a5
+; RV32IM-NEXT:    sub a1, a1, a2
 ; RV32IM-NEXT:    sub a5, a5, a1
-; RV32IM-NEXT:    add a2, a5, a2
-; RV32IM-NEXT:    sub a1, t3, a3
-; RV32IM-NEXT:    sub a1, a1, a4
-; RV32IM-NEXT:    add a1, a1, a2
-; RV32IM-NEXT:    neg a2, t5
-; RV32IM-NEXT:    sltu a2, a2, t0
-; RV32IM-NEXT:    add a1, a1, a2
+; RV32IM-NEXT:    add a4, a3, a4
+; RV32IM-NEXT:    sub a4, a4, a5
+; RV32IM-NEXT:    neg a1, t5
+; RV32IM-NEXT:    sltu a1, a1, t0
+; RV32IM-NEXT:    sub a4, a4, a1
+; RV32IM-NEXT:    sub a1, t3, a4
 ; RV32IM-NEXT:    add a1, a7, a1
 ; RV32IM-NEXT:    add a1, a1, s0
+; RV32IM-NEXT:    add a1, t1, a1
 ; RV32IM-NEXT:    slli a2, a3, 6
 ; RV32IM-NEXT:    sub a3, a3, a2
 ; RV32IM-NEXT:    sw a3, 0(a0)
 ; RV32IM-NEXT:    sw a6, 4(a0)
 ; RV32IM-NEXT:    sw t6, 8(a0)
 ; RV32IM-NEXT:    sw a1, 12(a0)
 ; RV32IM-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32IM-NEXT:    lw s1, 8(sp) # 4-byte Folded Reload
 ; RV32IM-NEXT:    addi sp, sp, 16
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: muli128_m63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a2, a0, 6
 ; RV64I-NEXT:    sltu a3, a0, a2
 ; RV64I-NEXT:    srli a4, a0, 58
 ; RV64I-NEXT:    slli a5, a1, 6
 ; RV64I-NEXT:    or a4, a5, a4
-; RV64I-NEXT:    sub a1, a1, a4
+; RV64I-NEXT:    add a3, a4, a3
 ; RV64I-NEXT:    sub a1, a1, a3
 ; RV64I-NEXT:    sub a0, a0, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: muli128_m63:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a2, a1, 6
 ; RV64IM-NEXT:    sub a1, a1, a2
 ; RV64IM-NEXT:    li a2, -63
 ; RV64IM-NEXT:    mulhu a2, a0, a2
-; RV64IM-NEXT:    sub a2, a2, a0
-; RV64IM-NEXT:    add a1, a2, a1
+; RV64IM-NEXT:    sub a1, a0, a1
+; RV64IM-NEXT:    sub a1, a2, a1
 ; RV64IM-NEXT:    slli a2, a0, 6
 ; RV64IM-NEXT:    sub a0, a0, a2
 ; RV64IM-NEXT:    ret
   %1 = mul i128 %a, -63
   ret i128 %1
 }
 
 define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {

 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __muldi3@plt
 ; RV32I-NEXT:    add s2, a0, s2
 ; RV32I-NEXT:    add a2, s9, s2
 ; RV32I-NEXT:    sltu a3, a2, s9
 ; RV32I-NEXT:    sltu a4, s9, s5
 ; RV32I-NEXT:    sltu a5, s8, s7
-; RV32I-NEXT:    add a5, s6, a5
 ; RV32I-NEXT:    add a4, a5, a4
-; RV32I-NEXT:    add a1, a1, s3
 ; RV32I-NEXT:    sltu a0, s2, a0
+; RV32I-NEXT:    add a0, s3, a0
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    add a0, a4, a0
-; RV32I-NEXT:    add a1, a0, a3
+; RV32I-NEXT:    add a0, a0, a3
+; RV32I-NEXT:    add a1, s6, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 36(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 32(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s5, 20(sp) # 4-byte Folded Reload

 ; RV32IM-NEXT:    mul a7, a1, a3
 ; RV32IM-NEXT:    add t0, a7, a5
 ; RV32IM-NEXT:    mul t1, a4, a0
 ; RV32IM-NEXT:    add a2, t0, t1
 ; RV32IM-NEXT:    sltu t2, a2, t0
 ; RV32IM-NEXT:    sltu a7, t0, a7
 ; RV32IM-NEXT:    sltu a5, a5, a6
 ; RV32IM-NEXT:    mulhu a3, a1, a3
-; RV32IM-NEXT:    add a3, a3, a5
-; RV32IM-NEXT:    add a3, a3, a7
+; RV32IM-NEXT:    add a5, a5, a7
 ; RV32IM-NEXT:    mul a1, a4, a1
 ; RV32IM-NEXT:    mulhu a0, a4, a0
+; RV32IM-NEXT:    add a1, a1, t1
 ; RV32IM-NEXT:    add a0, a0, a1
-; RV32IM-NEXT:    add a0, a0, t1
-; RV32IM-NEXT:    add a0, a3, a0
-; RV32IM-NEXT:    add a1, a0, t2
+; RV32IM-NEXT:    add a0, a5, a0
+; RV32IM-NEXT:    add a0, a0, t2
+; RV32IM-NEXT:    add a1, a3, a0
 ; RV32IM-NEXT:    mv a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: mulhsu_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv a2, a1

llvm/test/CodeGen/RISCV/neg-abs.ll

 
 define i64 @neg_abs64(i64 %x) {
 ; RV32I-LABEL: neg_abs64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a2, a1, 31
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a3, a2, a0
 ; RV32I-NEXT:    xor a1, a1, a2
+; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    sub a1, a2, a1
-; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: neg_abs64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    srai a2, a1, 31
 ; RV32ZBB-NEXT:    xor a0, a0, a2
 ; RV32ZBB-NEXT:    sltu a3, a2, a0
 ; RV32ZBB-NEXT:    xor a1, a1, a2
+; RV32ZBB-NEXT:    add a1, a1, a3
 ; RV32ZBB-NEXT:    sub a1, a2, a1
-; RV32ZBB-NEXT:    sub a1, a1, a3
 ; RV32ZBB-NEXT:    sub a0, a2, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64I-LABEL: neg_abs64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    sub a0, a1, a0

 
 define i64 @select_neg_abs64(i64 %x) {
 ; RV32I-LABEL: select_neg_abs64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a2, a1, 31
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a3, a2, a0
 ; RV32I-NEXT:    xor a1, a1, a2
+; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    sub a1, a2, a1
-; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: select_neg_abs64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    srai a2, a1, 31
 ; RV32ZBB-NEXT:    xor a0, a0, a2
 ; RV32ZBB-NEXT:    sltu a3, a2, a0
 ; RV32ZBB-NEXT:    xor a1, a1, a2
+; RV32ZBB-NEXT:    add a1, a1, a3
 ; RV32ZBB-NEXT:    sub a1, a2, a1
-; RV32ZBB-NEXT:    sub a1, a1, a3
 ; RV32ZBB-NEXT:    sub a0, a2, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64I-LABEL: select_neg_abs64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    sub a0, a1, a0

llvm/test/CodeGen/RISCV/rv32zbb.ll

 ; RV32I-NEXT:    lui a2, 16
 ; RV32I-NEXT:    addi a2, a2, -256
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a3, a0, 24
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    and a2, a0, a2
 ; RV32I-NEXT:    slli a2, a2, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a2
+; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: bswap_i32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rev8 a0, a0
 ; RV32ZBB-NEXT:    ret
   %1 = tail call i32 @llvm.bswap.i32(i32 %a)

 ; RV32I-NEXT:    lui a3, 16
 ; RV32I-NEXT:    addi a3, a3, -256
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
 ; RV32I-NEXT:    and a4, a1, a3
 ; RV32I-NEXT:    slli a4, a4, 8
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    or a2, a4, a2
 ; RV32I-NEXT:    or a2, a1, a2
 ; RV32I-NEXT:    srli a1, a0, 8
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    srli a4, a0, 24
 ; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:    and a3, a0, a3
 ; RV32I-NEXT:    slli a3, a3, 8
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a3
+; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: bswap_i64:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rev8 a2, a1
 ; RV32ZBB-NEXT:    rev8 a1, a0
 ; RV32ZBB-NEXT:    mv a0, a2
 ; RV32ZBB-NEXT:    ret
   %1 = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rv64zbb.ll

 ; RV64I-NEXT:    lui a2, 16
 ; RV64I-NEXT:    addiw a2, a2, -256
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 8
 ; RV64I-NEXT:    slliw a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a2
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: bswap_i32:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rev8 a0, a0
 ; RV64ZBB-NEXT:    srai a0, a0, 32
 ; RV64ZBB-NEXT:    ret

 ; RV64I-NEXT:    lui a3, 16
 ; RV64I-NEXT:    addiw a3, a3, -256
 ; RV64I-NEXT:    and a2, a2, a3
 ; RV64I-NEXT:    srliw a4, a0, 24
 ; RV64I-NEXT:    or a2, a2, a4
 ; RV64I-NEXT:    and a3, a0, a3
 ; RV64I-NEXT:    slliw a3, a3, 8
 ; RV64I-NEXT:    slliw a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a2, a3, a2
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    sw a0, 0(a1)
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: bswap_i32_nosext:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rev8 a0, a0
 ; RV64ZBB-NEXT:    srli a0, a0, 32

 ; RV64I-NEXT:    srli a3, a0, 56
 ; RV64I-NEXT:    or a1, a1, a3
 ; RV64I-NEXT:    srli a3, a0, 24
 ; RV64I-NEXT:    lui a4, 4080
 ; RV64I-NEXT:    and a3, a3, a4
 ; RV64I-NEXT:    srli a5, a0, 8
 ; RV64I-NEXT:    srliw a5, a5, 24
 ; RV64I-NEXT:    slli a5, a5, 24
-; RV64I-NEXT:    or a3, a5, a3
 ; RV64I-NEXT:    or a1, a3, a1
+; RV64I-NEXT:    or a1, a5, a1
 ; RV64I-NEXT:    and a4, a0, a4
 ; RV64I-NEXT:    slli a4, a4, 24
 ; RV64I-NEXT:    srliw a3, a0, 24
 ; RV64I-NEXT:    slli a3, a3, 32
 ; RV64I-NEXT:    or a3, a4, a3
 ; RV64I-NEXT:    and a2, a0, a2
 ; RV64I-NEXT:    slli a2, a2, 40
 ; RV64I-NEXT:    slli a0, a0, 56
-; RV64I-NEXT:    or a0, a0, a2
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a2, a2, a3
+; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: bswap_i64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rev8 a0, a0
 ; RV64ZBB-NEXT:    ret
   %1 = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

 ; i64 vectors should be scalarized
 define void @add_v2i64(ptr %x, ptr %y) {
 ; RV32-LABEL: add_v2i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lw a2, 8(a0)
 ; RV32-NEXT:    lw a3, 12(a0)
 ; RV32-NEXT:    lw a4, 0(a0)
 ; RV32-NEXT:    lw a5, 4(a0)
-; RV32-NEXT:    lw a6, 4(a1)
-; RV32-NEXT:    lw a7, 0(a1)
-; RV32-NEXT:    lw t0, 8(a1)
+; RV32-NEXT:    lw a6, 0(a1)
+; RV32-NEXT:    lw a7, 8(a1)
+; RV32-NEXT:    lw t0, 4(a1)
 ; RV32-NEXT:    lw a1, 12(a1)
-; RV32-NEXT:    add a5, a5, a6
-; RV32-NEXT:    add a7, a4, a7
-; RV32-NEXT:    sltu a4, a7, a4
+; RV32-NEXT:    add a6, a4, a6
+; RV32-NEXT:    sltu a4, a6, a4
+; RV32-NEXT:    add a4, t0, a4
 ; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    add a1, a3, a1
-; RV32-NEXT:    add t0, a2, t0
-; RV32-NEXT:    sltu a2, t0, a2
+; RV32-NEXT:    add a7, a2, a7
+; RV32-NEXT:    sltu a2, a7, a2
 ; RV32-NEXT:    add a1, a1, a2
-; RV32-NEXT:    sw t0, 8(a0)
-; RV32-NEXT:    sw a7, 0(a0)
+; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    sw a7, 8(a0)
+; RV32-NEXT:    sw a6, 0(a0)
 ; RV32-NEXT:    sw a1, 12(a0)
 ; RV32-NEXT:    sw a4, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: add_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    ld a2, 8(a0)
 ; RV64-NEXT:    ld a3, 0(a0)
; CHECK-NEXT:    ret
   ret void
 }
 
 ; i64 vectors should be scalarized
 define void @add_v1i64(ptr %x, ptr %y) {
 ; RV32-LABEL: add_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lw a2, 0(a0)
-; RV32-NEXT:    lw a3, 4(a0)
-; RV32-NEXT:    lw a4, 4(a1)
-; RV32-NEXT:    lw a1, 0(a1)
-; RV32-NEXT:    add a3, a3, a4
-; RV32-NEXT:    add a1, a2, a1
-; RV32-NEXT:    sltu a2, a1, a2
-; RV32-NEXT:    add a2, a3, a2
-; RV32-NEXT:    sw a1, 0(a0)
-; RV32-NEXT:    sw a2, 4(a0)
+; RV32-NEXT:    lw a3, 0(a1)
+; RV32-NEXT:    lw a1, 4(a1)
+; RV32-NEXT:    lw a4, 4(a0)
+; RV32-NEXT:    add a3, a2, a3
+; RV32-NEXT:    sltu a2, a3, a2
+; RV32-NEXT:    add a1, a1, a2
+; RV32-NEXT:    add a1, a4, a1
+; RV32-NEXT:    sw a3, 0(a0)
+; RV32-NEXT:    sw a1, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: add_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    ld a2, 0(a0)
 ; RV64-NEXT:    ld a1, 0(a1)
 ; RV64-NEXT:    add a1, a2, a1
 ; RV64-NEXT:    sd a1, 0(a0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

 ; RV32-NEXT:    lbu a3, 1(a0)
 ; RV32-NEXT:    lbu a4, 0(a0)
 ; RV32-NEXT:    lbu a5, 2(a0)
 ; RV32-NEXT:    lbu a6, 3(a0)
 ; RV32-NEXT:    slli a3, a3, 8
 ; RV32-NEXT:    or a3, a3, a4
 ; RV32-NEXT:    slli a5, a5, 16
 ; RV32-NEXT:    slli a6, a6, 24
-; RV32-NEXT:    or a4, a6, a5
-; RV32-NEXT:    or a3, a4, a3
+; RV32-NEXT:    or a3, a5, a3
+; RV32-NEXT:    or a3, a6, a3
 ; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV32-NEXT:    vmv.v.x v8, a3
 ; RV32-NEXT:    andi a2, a2, 2
 ; RV32-NEXT:    bnez a2, .LBB8_3
 ; RV32-NEXT:    j .LBB8_4
 ; RV32-NEXT:  .LBB8_2:
 ; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    andi a2, a2, 2
 ; RV32-NEXT:    beqz a2, .LBB8_4
 ; RV32-NEXT:  .LBB8_3: # %cond.load1
 ; RV32-NEXT:    lbu a2, 5(a0)
 ; RV32-NEXT:    lbu a3, 4(a0)
 ; RV32-NEXT:    lbu a4, 6(a0)
 ; RV32-NEXT:    lbu a0, 7(a0)
 ; RV32-NEXT:    slli a2, a2, 8
 ; RV32-NEXT:    or a2, a2, a3
 ; RV32-NEXT:    slli a4, a4, 16
 ; RV32-NEXT:    slli a0, a0, 24
-; RV32-NEXT:    or a0, a0, a4
+; RV32-NEXT:    or a2, a4, a2
 ; RV32-NEXT:    or a0, a0, a2
 ; RV32-NEXT:    vmv.s.x v9, a0
 ; RV32-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
 ; RV32-NEXT:    vslideup.vi v8, v9, 1
 ; RV32-NEXT:  .LBB8_4: # %else2
 ; RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV32-NEXT:    vse32.v v8, (a1)
 ; RV32-NEXT:    ret

 ; RV64-NEXT:    lbu a3, 1(a0)
 ; RV64-NEXT:    lbu a4, 0(a0)
 ; RV64-NEXT:    lbu a5, 2(a0)
 ; RV64-NEXT:    lb a6, 3(a0)
 ; RV64-NEXT:    slli a3, a3, 8
 ; RV64-NEXT:    or a3, a3, a4
 ; RV64-NEXT:    slli a5, a5, 16
 ; RV64-NEXT:    slli a6, a6, 24
-; RV64-NEXT:    or a4, a6, a5
-; RV64-NEXT:    or a3, a4, a3
+; RV64-NEXT:    or a3, a5, a3
+; RV64-NEXT:    or a3, a6, a3
 ; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV64-NEXT:    vmv.v.x v8, a3
 ; RV64-NEXT:    andi a2, a2, 2
 ; RV64-NEXT:    bnez a2, .LBB8_3
 ; RV64-NEXT:    j .LBB8_4
 ; RV64-NEXT:  .LBB8_2:
 ; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 0
 ; RV64-NEXT:    andi a2, a2, 2
 ; RV64-NEXT:    beqz a2, .LBB8_4
 ; RV64-NEXT:  .LBB8_3: # %cond.load1
 ; RV64-NEXT:    lbu a2, 5(a0)
 ; RV64-NEXT:    lbu a3, 4(a0)
 ; RV64-NEXT:    lbu a4, 6(a0)
 ; RV64-NEXT:    lb a0, 7(a0)
 ; RV64-NEXT:    slli a2, a2, 8
 ; RV64-NEXT:    or a2, a2, a3
 ; RV64-NEXT:    slli a4, a4, 16
 ; RV64-NEXT:    slli a0, a0, 24
-; RV64-NEXT:    or a0, a0, a4
+; RV64-NEXT:    or a2, a4, a2
 ; RV64-NEXT:    or a0, a0, a2
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
 ; RV64-NEXT:    vslideup.vi v8, v9, 1
 ; RV64-NEXT:  .LBB8_4: # %else2
 ; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
 ; RV64-NEXT:    vse32.v v8, (a1)
 ; RV64-NEXT:    ret

llvm/test/CodeGen/RISCV/sadd_sat.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a4, a1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    add a5, a4, a3
 ; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    add a1, a5, a1
+; RV32I-NEXT:    add a1, a3, a1
+; RV32I-NEXT:    add a1, a4, a1
 ; RV32I-NEXT:    xor a2, a4, a1
 ; RV32I-NEXT:    xor a3, a4, a3
 ; RV32I-NEXT:    not a3, a3
 ; RV32I-NEXT:    and a2, a3, a2
 ; RV32I-NEXT:    bgez a2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64-NEXT:    xor a0, a0, a1
 ; RV64-NEXT:  .LBB1_2:
 ; RV64-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a4, a1
 ; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a5, a4, a3
 ; RV32IZbb-NEXT:    add a0, a0, a2
 ; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a1, a5, a1
+; RV32IZbb-NEXT:    add a1, a3, a1
+; RV32IZbb-NEXT:    add a1, a4, a1
 ; RV32IZbb-NEXT:    xor a2, a4, a1
 ; RV32IZbb-NEXT:    xor a3, a4, a3
 ; RV32IZbb-NEXT:    andn a2, a2, a3
 ; RV32IZbb-NEXT:    bgez a2, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    srai a0, a1, 31
 ; RV32IZbb-NEXT:    lui a1, 524288
 ; RV32IZbb-NEXT:    xor a1, a0, a1

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    mv a2, a1
 ; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    add a3, a2, a5
 ; RV32I-NEXT:    add a0, a0, a4
 ; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    add a1, a3, a1
+; RV32I-NEXT:    add a1, a5, a1
+; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    xor a3, a2, a1
 ; RV32I-NEXT:    xor a2, a2, a5
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    bgez a2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srai a0, a1, 31
 ; RV32I-NEXT:    lui a1, 524288

 ; RV64-NEXT:    xor a0, a0, a1
 ; RV64-NEXT:  .LBB1_2:
 ; RV64-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    mv a2, a1
 ; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a3, a2, a5
 ; RV32IZbb-NEXT:    add a0, a0, a4
 ; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a1, a3, a1
+; RV32IZbb-NEXT:    add a1, a5, a1
+; RV32IZbb-NEXT:    add a1, a2, a1
 ; RV32IZbb-NEXT:    xor a3, a2, a1
 ; RV32IZbb-NEXT:    xor a2, a2, a5
 ; RV32IZbb-NEXT:    andn a2, a3, a2
 ; RV32IZbb-NEXT:    bgez a2, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    srai a0, a1, 31
 ; RV32IZbb-NEXT:    lui a1, 524288
 ; RV32IZbb-NEXT:    xor a1, a0, a1

llvm/test/CodeGen/RISCV/select-binop-identity.ll

 define i64 @add_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: add_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    neg a0, a0
 ; RV32I-NEXT:    and a2, a0, a2
 ; RV32I-NEXT:    and a1, a0, a1
 ; RV32I-NEXT:    add a0, a1, a3
 ; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    add a2, a2, a4
+; RV32I-NEXT:    add a1, a4, a1
 ; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    add a0, a0, a2

 
 define i64 @sub_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
 ; RV32I-LABEL: sub_select_all_zeros_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    neg a0, a0
 ; RV32I-NEXT:    and a2, a0, a2
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    sltu a1, a3, a0
-; RV32I-NEXT:    sub a4, a4, a2
+; RV32I-NEXT:    add a1, a2, a1
 ; RV32I-NEXT:    sub a1, a4, a1
 ; RV32I-NEXT:    sub a0, a3, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sub_select_all_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    and a0, a0, a1

llvm/test/CodeGen/RISCV/shadowcallstack.ll

 ; RV32-NEXT:    .cfi_offset s3, -16
 ; RV32-NEXT:    call bar@plt
 ; RV32-NEXT:    mv s0, a0
 ; RV32-NEXT:    call bar@plt
 ; RV32-NEXT:    mv s1, a0
 ; RV32-NEXT:    call bar@plt
 ; RV32-NEXT:    mv s3, a0
 ; RV32-NEXT:    call bar@plt
-; RV32-NEXT:    add s0, s0, s1
 ; RV32-NEXT:    add a0, s3, a0
+; RV32-NEXT:    add a0, s1, a0
 ; RV32-NEXT:    add a0, s0, a0
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s3, 0(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    lw ra, -4(s2)
 ; RV32-NEXT:    addi s2, s2, -4

 ; RV64-NEXT:    .cfi_offset s3, -32
 ; RV64-NEXT:    call bar@plt
 ; RV64-NEXT:    mv s0, a0
 ; RV64-NEXT:    call bar@plt
 ; RV64-NEXT:    mv s1, a0
 ; RV64-NEXT:    call bar@plt
 ; RV64-NEXT:    mv s3, a0
 ; RV64-NEXT:    call bar@plt
-; RV64-NEXT:    addw s0, s0, s1
 ; RV64-NEXT:    addw a0, s3, a0
+; RV64-NEXT:    addw a0, s1, a0
 ; RV64-NEXT:    addw a0, s0, a0
 ; RV64-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s3, 0(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 32
 ; RV64-NEXT:    ld ra, -8(s2)
 ; RV64-NEXT:    addi s2, s2, -8

llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll

 ; RV32-NEXT:    srli a6, a5, 1
 ; RV32-NEXT:    andi a5, a5, -2
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, -1366
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_3:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI0_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI0_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a4, a3, a2
 ; RV64-NEXT:    srli a5, a4, 1
 ; RV64-NEXT:    andi a4, a4, -2
 ; RV64-NEXT:    lui a6, %hi(.LCPI0_1)
 ; RV64-NEXT:    ld a6, %lo(.LCPI0_1)(a6)
 ; RV64-NEXT:    add a4, a4, a5
 ; RV64-NEXT:    sub a3, a3, a4
 ; RV64-NEXT:    sub a4, a0, a3
 ; RV64-NEXT:    mul a5, a4, a6
 ; RV64-NEXT:    mulhu a6, a4, a2
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a3
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a2
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a2
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a4, a2
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 3
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_5(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_5:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    sltu a3, a2, a0
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    lui a3, 838861
 ; RV32-NEXT:    addi a4, a3, -819
 ; RV32-NEXT:    mulhu a5, a2, a4
 ; RV32-NEXT:    srli a6, a5, 2
 ; RV32-NEXT:    andi a5, a5, -4
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, -820
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_5:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI1_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI1_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a4, a3, a2
 ; RV64-NEXT:    srli a5, a4, 2
 ; RV64-NEXT:    andi a4, a4, -4
 ; RV64-NEXT:    lui a6, %hi(.LCPI1_1)
 ; RV64-NEXT:    ld a6, %lo(.LCPI1_1)(a6)
 ; RV64-NEXT:    add a4, a4, a5
 ; RV64-NEXT:    sub a3, a3, a4
 ; RV64-NEXT:    sub a4, a0, a3
 ; RV64-NEXT:    mul a5, a4, a6
 ; RV64-NEXT:    mulhu a6, a4, a2
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a3
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a2
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a2
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a4, a2
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 5
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_7(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_7:

 ; RV32-NEXT:    sub a3, a3, a4
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    sub a3, a0, a2
 ; RV32-NEXT:    lui a4, 978671
 ; RV32-NEXT:    addi a5, a4, -274
 ; RV32-NEXT:    mul a5, a3, a5
 ; RV32-NEXT:    addi a4, a4, -273
 ; RV32-NEXT:    mulhu a6, a3, a4
-; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a5, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a5, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a3, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_15:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI4_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI4_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a2, a3, a2
 ; RV64-NEXT:    srli a2, a2, 3
 ; RV64-NEXT:    slli a4, a2, 4
 ; RV64-NEXT:    sub a2, a2, a4
 ; RV64-NEXT:    lui a4, %hi(.LCPI4_1)
 ; RV64-NEXT:    ld a4, %lo(.LCPI4_1)(a4)
 ; RV64-NEXT:    lui a5, %hi(.LCPI4_2)
 ; RV64-NEXT:    ld a5, %lo(.LCPI4_2)(a5)
 ; RV64-NEXT:    add a2, a3, a2
 ; RV64-NEXT:    sub a3, a0, a2
 ; RV64-NEXT:    mul a4, a3, a4
 ; RV64-NEXT:    mulhu a6, a3, a5
-; RV64-NEXT:    add a4, a6, a4
 ; RV64-NEXT:    sltu a0, a0, a2
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a5
-; RV64-NEXT:    add a1, a4, a1
+; RV64-NEXT:    mul a0, a1, a5
+; RV64-NEXT:    add a0, a4, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a3, a5
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 15
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_17(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_17:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    sltu a3, a2, a0
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    lui a3, 986895
 ; RV32-NEXT:    addi a4, a3, 241
 ; RV32-NEXT:    mulhu a5, a2, a4
 ; RV32-NEXT:    srli a6, a5, 4
 ; RV32-NEXT:    andi a5, a5, -16
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, 240
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_17:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI5_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI5_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a4, a3, a2
 ; RV64-NEXT:    srli a5, a4, 4
 ; RV64-NEXT:    andi a4, a4, -16
 ; RV64-NEXT:    lui a6, %hi(.LCPI5_1)
 ; RV64-NEXT:    ld a6, %lo(.LCPI5_1)(a6)
 ; RV64-NEXT:    add a4, a4, a5
 ; RV64-NEXT:    sub a3, a3, a4
 ; RV64-NEXT:    sub a4, a0, a3
 ; RV64-NEXT:    mul a5, a4, a6
 ; RV64-NEXT:    mulhu a6, a4, a2
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a3
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a2
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a2
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a4, a2
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 17
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_255(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_255:

 ; RV32-NEXT:    sub a3, a3, a4
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    sub a3, a0, a2
 ; RV32-NEXT:    lui a4, 1044464
 ; RV32-NEXT:    addi a5, a4, -258
 ; RV32-NEXT:    mul a5, a3, a5
 ; RV32-NEXT:    addi a4, a4, -257
 ; RV32-NEXT:    mulhu a6, a3, a4
-; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a5, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a5, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a3, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_255:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI6_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI6_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a2, a3, a2
 ; RV64-NEXT:    srli a2, a2, 7
 ; RV64-NEXT:    slli a4, a2, 8
 ; RV64-NEXT:    sub a2, a2, a4
 ; RV64-NEXT:    lui a4, %hi(.LCPI6_1)
 ; RV64-NEXT:    ld a4, %lo(.LCPI6_1)(a4)
 ; RV64-NEXT:    lui a5, %hi(.LCPI6_2)
 ; RV64-NEXT:    ld a5, %lo(.LCPI6_2)(a5)
 ; RV64-NEXT:    add a2, a3, a2
 ; RV64-NEXT:    sub a3, a0, a2
 ; RV64-NEXT:    mul a4, a3, a4
 ; RV64-NEXT:    mulhu a6, a3, a5
-; RV64-NEXT:    add a4, a6, a4
 ; RV64-NEXT:    sltu a0, a0, a2
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a5
-; RV64-NEXT:    add a1, a4, a1
+; RV64-NEXT:    mul a0, a1, a5
+; RV64-NEXT:    add a0, a4, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a3, a5
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 255
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_257(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_257:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    sltu a3, a2, a0
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    lui a3, 1044496
 ; RV32-NEXT:    addi a4, a3, -255
 ; RV32-NEXT:    mulhu a5, a2, a4
 ; RV32-NEXT:    srli a6, a5, 8
 ; RV32-NEXT:    andi a5, a5, -256
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, -256
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_257:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI7_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI7_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a4, a3, a2
 ; RV64-NEXT:    srli a5, a4, 8
 ; RV64-NEXT:    andi a4, a4, -256
 ; RV64-NEXT:    lui a6, %hi(.LCPI7_1)
 ; RV64-NEXT:    ld a6, %lo(.LCPI7_1)(a6)
 ; RV64-NEXT:    add a4, a4, a5
 ; RV64-NEXT:    sub a3, a3, a4
 ; RV64-NEXT:    sub a4, a0, a3
 ; RV64-NEXT:    mul a5, a4, a6
 ; RV64-NEXT:    mulhu a6, a4, a2
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a3
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a2
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a2
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a4, a2
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 257
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_65535(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_65535:

 ; RV32-NEXT:    sub a3, a3, a4
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    sub a3, a0, a2
 ; RV32-NEXT:    lui a4, 1048560
 ; RV32-NEXT:    addi a5, a4, -2
 ; RV32-NEXT:    mul a5, a3, a5
 ; RV32-NEXT:    addi a4, a4, -1
 ; RV32-NEXT:    mulhu a4, a3, a4
-; RV32-NEXT:    add a4, a4, a5
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
 ; RV32-NEXT:    slli a0, a1, 16
 ; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    sub a1, a4, a0
+; RV32-NEXT:    sub a1, a5, a0
+; RV32-NEXT:    add a1, a4, a1
 ; RV32-NEXT:    slli a0, a3, 16
-; RV32-NEXT:    add a0, a0, a3
-; RV32-NEXT:    neg a0, a0
+; RV32-NEXT:    neg a2, a3
+; RV32-NEXT:    sub a0, a2, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_65535:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a2, %hi(.LCPI8_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI8_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a2, a3, a2
 ; RV64-NEXT:    srli a2, a2, 15
 ; RV64-NEXT:    slli a4, a2, 16
 ; RV64-NEXT:    sub a2, a2, a4
 ; RV64-NEXT:    add a2, a3, a2
 ; RV64-NEXT:    sub a3, a0, a2
 ; RV64-NEXT:    lui a4, 983039
 ; RV64-NEXT:    slli a4, a4, 4
 ; RV64-NEXT:    addi a4, a4, -1
 ; RV64-NEXT:    slli a4, a4, 16
 ; RV64-NEXT:    addi a5, a4, -2
 ; RV64-NEXT:    mul a5, a3, a5
 ; RV64-NEXT:    addi a4, a4, -1
 ; RV64-NEXT:    mulhu a6, a3, a4
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a2
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a4
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a4
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a3, a4
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 65535
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_65537(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_65537:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    add a2, a0, a1
 ; RV32-NEXT:    sltu a3, a2, a0
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    lui a3, 1048560
 ; RV32-NEXT:    addi a4, a3, 1
 ; RV32-NEXT:    mulhu a5, a2, a4
 ; RV32-NEXT:    and a3, a5, a3
 ; RV32-NEXT:    srli a5, a5, 16
 ; RV32-NEXT:    or a3, a3, a5
 ; RV32-NEXT:    sub a2, a2, a3
 ; RV32-NEXT:    sub a3, a0, a2
 ; RV32-NEXT:    mulhu a4, a3, a4
 ; RV32-NEXT:    slli a5, a3, 16
-; RV32-NEXT:    sub a4, a4, a5
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
 ; RV32-NEXT:    slli a0, a1, 16
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    add a1, a4, a1
+; RV32-NEXT:    sub a0, a5, a1
+; RV32-NEXT:    sub a1, a4, a0
 ; RV32-NEXT:    sub a0, a3, a5
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_65537:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    sltu a3, a2, a0
 ; RV64-NEXT:    add a2, a2, a3
 ; RV64-NEXT:    lui a3, 983041
 ; RV64-NEXT:    slli a3, a3, 4
 ; RV64-NEXT:    addi a3, a3, -1
 ; RV64-NEXT:    slli a3, a3, 16
 ; RV64-NEXT:    addi a4, a3, 1
 ; RV64-NEXT:    mulhu a5, a2, a4
 ; RV64-NEXT:    lui a6, 1048560
 ; RV64-NEXT:    and a6, a5, a6
 ; RV64-NEXT:    srli a5, a5, 16
 ; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sub a2, a2, a5
 ; RV64-NEXT:    sub a5, a0, a2
 ; RV64-NEXT:    mul a3, a5, a3
 ; RV64-NEXT:    mulhu a6, a5, a4
-; RV64-NEXT:    add a3, a6, a3
 ; RV64-NEXT:    sltu a0, a0, a2
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a4
-; RV64-NEXT:    add a1, a3, a1
+; RV64-NEXT:    mul a0, a1, a4
+; RV64-NEXT:    add a0, a3, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a5, a4
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 65537
   ret iXLen2 %a
 }
 
 define iXLen2 @test_udiv_12(iXLen2 %x) nounwind {
 ; RV32-LABEL: test_udiv_12:

 ; RV32-NEXT:    srli a6, a5, 1
 ; RV32-NEXT:    andi a5, a5, -2
 ; RV32-NEXT:    add a5, a5, a6
 ; RV32-NEXT:    sub a2, a2, a5
 ; RV32-NEXT:    sub a5, a0, a2
 ; RV32-NEXT:    addi a3, a3, -1366
 ; RV32-NEXT:    mul a3, a5, a3
 ; RV32-NEXT:    mulhu a6, a5, a4
-; RV32-NEXT:    add a3, a6, a3
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:    sub a1, a1, a0
-; RV32-NEXT:    mul a1, a1, a4
-; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    mul a0, a1, a4
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a1, a6, a0
 ; RV32-NEXT:    mul a0, a5, a4
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_udiv_12:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slli a2, a1, 62
 ; RV64-NEXT:    srli a0, a0, 2
 ; RV64-NEXT:    or a0, a0, a2
 ; RV64-NEXT:    srli a1, a1, 2
 ; RV64-NEXT:    lui a2, %hi(.LCPI10_0)
 ; RV64-NEXT:    ld a2, %lo(.LCPI10_0)(a2)
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    sltu a4, a3, a0
 ; RV64-NEXT:    add a3, a3, a4
 ; RV64-NEXT:    mulhu a4, a3, a2
 ; RV64-NEXT:    srli a5, a4, 1
 ; RV64-NEXT:    andi a4, a4, -2
 ; RV64-NEXT:    lui a6, %hi(.LCPI10_1)
 ; RV64-NEXT:    ld a6, %lo(.LCPI10_1)(a6)
 ; RV64-NEXT:    add a4, a4, a5
 ; RV64-NEXT:    sub a3, a3, a4
 ; RV64-NEXT:    sub a4, a0, a3
 ; RV64-NEXT:    mul a5, a4, a6
 ; RV64-NEXT:    mulhu a6, a4, a2
-; RV64-NEXT:    add a5, a6, a5
 ; RV64-NEXT:    sltu a0, a0, a3
 ; RV64-NEXT:    sub a1, a1, a0
-; RV64-NEXT:    mul a1, a1, a2
-; RV64-NEXT:    add a1, a5, a1
+; RV64-NEXT:    mul a0, a1, a2
+; RV64-NEXT:    add a0, a5, a0
+; RV64-NEXT:    add a1, a6, a0
 ; RV64-NEXT:    mul a0, a4, a2
 ; RV64-NEXT:    ret
   %a = udiv iXLen2 %x, 12
   ret iXLen2 %a
 }

llvm/test/CodeGen/RISCV/srem-lkk.ll

 ; RV32IM-NEXT:    addi a1, a1, 389
 ; RV32IM-NEXT:    mulh a1, a0, a1
 ; RV32IM-NEXT:    add a1, a1, a0
 ; RV32IM-NEXT:    srli a2, a1, 31
 ; RV32IM-NEXT:    srai a1, a1, 6
 ; RV32IM-NEXT:    add a1, a1, a2
 ; RV32IM-NEXT:    li a2, 95
 ; RV32IM-NEXT:    mul a2, a1, a2
+; RV32IM-NEXT:    sub a2, a2, a1
 ; RV32IM-NEXT:    sub a0, a0, a2
-; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill

 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    srli a1, a1, 32
 ; RV64IM-NEXT:    addw a1, a1, a0
 ; RV64IM-NEXT:    srliw a2, a1, 31
 ; RV64IM-NEXT:    sraiw a1, a1, 6
 ; RV64IM-NEXT:    addw a1, a1, a2
 ; RV64IM-NEXT:    li a2, 95
 ; RV64IM-NEXT:    mulw a2, a1, a2
+; RV64IM-NEXT:    subw a2, a2, a1
 ; RV64IM-NEXT:    subw a0, a0, a2
-; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %x, 95
   %2 = sdiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 
 ; Don't fold for divisors that are a power of two.

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

 ; RV32-NEXT:    andi a3, a0, 7
 ; RV32-NEXT:    sb a3, 12(s0)
 ; RV32-NEXT:    slli a3, a1, 1
 ; RV32-NEXT:    or a2, a3, a2
 ; RV32-NEXT:    sw a2, 4(s0)
 ; RV32-NEXT:    srli a2, a1, 31
 ; RV32-NEXT:    andi a1, a1, 1
 ; RV32-NEXT:    slli a1, a1, 1
-; RV32-NEXT:    or a1, a2, a1
 ; RV32-NEXT:    slli a0, a0, 2
 ; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    or a0, a2, a0
 ; RV32-NEXT:    sw a0, 8(s0)
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload

 ; RV32M-NEXT:    andi a3, a0, 7
 ; RV32M-NEXT:    sb a3, 12(s0)
 ; RV32M-NEXT:    slli a3, a1, 1
 ; RV32M-NEXT:    or a2, a3, a2
 ; RV32M-NEXT:    sw a2, 4(s0)
 ; RV32M-NEXT:    srli a2, a1, 31
 ; RV32M-NEXT:    andi a1, a1, 1
 ; RV32M-NEXT:    slli a1, a1, 1
-; RV32M-NEXT:    or a1, a2, a1
 ; RV32M-NEXT:    slli a0, a0, 2
 ; RV32M-NEXT:    or a0, a1, a0
+; RV32M-NEXT:    or a0, a2, a0
 ; RV32M-NEXT:    sw a0, 8(s0)
 ; RV32M-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s5, 4(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    lw s6, 0(sp) # 4-byte Folded Reload
 ; RV32M-NEXT:    addi sp, sp, 32
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_srem_vec:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    ld a1, 0(a0)
 ; RV64M-NEXT:    lwu a2, 8(a0)
 ; RV64M-NEXT:    srli a3, a1, 2
 ; RV64M-NEXT:    lb a4, 12(a0)
 ; RV64M-NEXT:    slli a5, a2, 62
 ; RV64M-NEXT:    or a3, a5, a3
 ; RV64M-NEXT:    srai a3, a3, 31
 ; RV64M-NEXT:    slli a4, a4, 32
-; RV64M-NEXT:    lui a5, %hi(.LCPI3_0)
-; RV64M-NEXT:    ld a5, %lo(.LCPI3_0)(a5)
 ; RV64M-NEXT:    or a2, a2, a4
 ; RV64M-NEXT:    slli a2, a2, 29
+; RV64M-NEXT:    lui a4, %hi(.LCPI3_0)
+; RV64M-NEXT:    ld a4, %lo(.LCPI3_0)(a4)
 ; RV64M-NEXT:    srai a2, a2, 31
-; RV64M-NEXT:    mulh a4, a2, a5
+; RV64M-NEXT:    slli a1, a1, 31
+; RV64M-NEXT:    srai a1, a1, 31
+; RV64M-NEXT:    mulh a4, a2, a4
 ; RV64M-NEXT:    srli a5, a4, 63
 ; RV64M-NEXT:    srai a4, a4, 1
 ; RV64M-NEXT:    add a4, a4, a5
-; RV64M-NEXT:    slli a5, a4, 2
-; RV64M-NEXT:    add a4, a5, a4
 ; RV64M-NEXT:    lui a5, %hi(.LCPI3_1)
 ; RV64M-NEXT:    ld a5, %lo(.LCPI3_1)(a5)
-; RV64M-NEXT:    slli a1, a1, 31
-; RV64M-NEXT:    srai a1, a1, 31
+; RV64M-NEXT:    add a2, a2, a4
+; RV64M-NEXT:    slli a4, a4, 2
 ; RV64M-NEXT:    add a2, a2, a4
 ; RV64M-NEXT:    mulh a4, a3, a5
 ; RV64M-NEXT:    srli a5, a4, 63
 ; RV64M-NEXT:    srai a4, a4, 1
 ; RV64M-NEXT:    add a4, a4, a5
 ; RV64M-NEXT:    slli a5, a4, 3
-; RV64M-NEXT:    sub a4, a4, a5
+; RV64M-NEXT:    sub a3, a3, a5
 ; RV64M-NEXT:    add a3, a3, a4
 ; RV64M-NEXT:    addi a3, a3, -1
 ; RV64M-NEXT:    seqz a3, a3
 ; RV64M-NEXT:    lui a4, %hi(.LCPI3_2)
 ; RV64M-NEXT:    ld a4, %lo(.LCPI3_2)(a4)
 ; RV64M-NEXT:    lui a5, %hi(.LCPI3_3)
 ; RV64M-NEXT:    ld a5, %lo(.LCPI3_3)(a5)
 ; RV64M-NEXT:    addi a2, a2, -2

 ; RV32MV-NEXT:    or a2, a3, a2
 ; RV32MV-NEXT:    andi a2, a2, 7
 ; RV32MV-NEXT:    sb a2, 12(s2)
 ; RV32MV-NEXT:    srli a1, a1, 31
 ; RV32MV-NEXT:    vslidedown.vi v8, v8, 3
 ; RV32MV-NEXT:    vmv.x.s a2, v8
 ; RV32MV-NEXT:    andi a2, a2, 1
 ; RV32MV-NEXT:    slli a2, a2, 1
-; RV32MV-NEXT:    or a1, a1, a2
 ; RV32MV-NEXT:    slli a0, a0, 2
+; RV32MV-NEXT:    or a0, a2, a0
 ; RV32MV-NEXT:    or a0, a1, a0
 ; RV32MV-NEXT:    sw a0, 8(s2)
 ; RV32MV-NEXT:    addi sp, s0, -64
 ; RV32MV-NEXT:    lw ra, 60(sp) # 4-byte Folded Reload
 ; RV32MV-NEXT:    lw s0, 56(sp) # 4-byte Folded Reload
 ; RV32MV-NEXT:    lw s2, 52(sp) # 4-byte Folded Reload
 ; RV32MV-NEXT:    lw s3, 48(sp) # 4-byte Folded Reload
 ; RV32MV-NEXT:    lw s4, 44(sp) # 4-byte Folded Reload

 ; RV64MV-NEXT:    sd a3, 0(sp)
 ; RV64MV-NEXT:    mulh a3, a2, a5
 ; RV64MV-NEXT:    srli a4, a3, 63
 ; RV64MV-NEXT:    srai a3, a3, 1
 ; RV64MV-NEXT:    add a3, a3, a4
 ; RV64MV-NEXT:    slli a4, a3, 3
 ; RV64MV-NEXT:    lui a5, %hi(.LCPI3_2)
 ; RV64MV-NEXT:    ld a5, %lo(.LCPI3_2)(a5)
-; RV64MV-NEXT:    sub a3, a3, a4
+; RV64MV-NEXT:    sub a2, a2, a4
 ; RV64MV-NEXT:    add a2, a2, a3
 ; RV64MV-NEXT:    sd a2, 8(sp)
 ; RV64MV-NEXT:    mulh a2, a1, a5
 ; RV64MV-NEXT:    srli a3, a2, 63
 ; RV64MV-NEXT:    srai a2, a2, 1
 ; RV64MV-NEXT:    add a2, a2, a3
 ; RV64MV-NEXT:    slli a3, a2, 2
-; RV64MV-NEXT:    add a2, a3, a2
 ; RV64MV-NEXT:    add a1, a1, a2
+; RV64MV-NEXT:    add a1, a1, a3
 ; RV64MV-NEXT:    sd a1, 16(sp)
 ; RV64MV-NEXT:    mv a1, sp
 ; RV64MV-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64MV-NEXT:    vle64.v v8, (a1)
 ; RV64MV-NEXT:    lui a1, %hi(.LCPI3_3)
 ; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI3_3)
 ; RV64MV-NEXT:    vle64.v v10, (a1)
 ; RV64MV-NEXT:    li a1, -1

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

 ; RV32IM-NEXT:    addi a5, a5, 389
 ; RV32IM-NEXT:    mulh a6, a4, a5
 ; RV32IM-NEXT:    add a6, a6, a4
 ; RV32IM-NEXT:    srli a7, a6, 31
 ; RV32IM-NEXT:    srai a6, a6, 6
 ; RV32IM-NEXT:    add a6, a6, a7
 ; RV32IM-NEXT:    li a7, 95
 ; RV32IM-NEXT:    mul t0, a6, a7
-; RV32IM-NEXT:    sub a4, a4, t0
-; RV32IM-NEXT:    mulh t0, a1, a5
-; RV32IM-NEXT:    add t0, t0, a1
-; RV32IM-NEXT:    srli t1, t0, 31
-; RV32IM-NEXT:    srai t0, t0, 6
-; RV32IM-NEXT:    add t0, t0, t1
-; RV32IM-NEXT:    mul t1, t0, a7
-; RV32IM-NEXT:    sub a1, a1, t1
-; RV32IM-NEXT:    mulh t1, a3, a5
-; RV32IM-NEXT:    add t1, t1, a3
+; RV32IM-NEXT:    mulh t1, a1, a5
+; RV32IM-NEXT:    add t1, t1, a1
 ; RV32IM-NEXT:    srli t2, t1, 31
 ; RV32IM-NEXT:    srai t1, t1, 6
 ; RV32IM-NEXT:    add t1, t1, t2
 ; RV32IM-NEXT:    mul t2, t1, a7
-; RV32IM-NEXT:    sub a3, a3, t2
+; RV32IM-NEXT:    mulh t3, a3, a5
+; RV32IM-NEXT:    add t3, t3, a3
+; RV32IM-NEXT:    srli t4, t3, 31
+; RV32IM-NEXT:    srai t3, t3, 6
+; RV32IM-NEXT:    add t3, t3, t4
+; RV32IM-NEXT:    mul t4, t3, a7
 ; RV32IM-NEXT:    mulh a5, a2, a5
 ; RV32IM-NEXT:    add a5, a5, a2
-; RV32IM-NEXT:    srli t2, a5, 31
+; RV32IM-NEXT:    srli t5, a5, 31
 ; RV32IM-NEXT:    srai a5, a5, 6
-; RV32IM-NEXT:    add a5, a5, t2
+; RV32IM-NEXT:    add a5, a5, t5
 ; RV32IM-NEXT:    mul a7, a5, a7
-; RV32IM-NEXT:    sub a2, a2, a7
-; RV32IM-NEXT:    add a2, a2, a5
-; RV32IM-NEXT:    add a3, a3, t1
-; RV32IM-NEXT:    add a1, a1, t0
-; RV32IM-NEXT:    add a4, a4, a6
+; RV32IM-NEXT:    sub a5, a7, a5
+; RV32IM-NEXT:    sub a2, a2, a5
+; RV32IM-NEXT:    sub a5, t4, t3
+; RV32IM-NEXT:    sub a3, a3, a5
+; RV32IM-NEXT:    sub a5, t2, t1
+; RV32IM-NEXT:    sub a1, a1, a5
+; RV32IM-NEXT:    sub a5, t0, a6
+; RV32IM-NEXT:    sub a4, a4, a5
 ; RV32IM-NEXT:    sh a4, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a3, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_srem_sdiv:
 ; RV64I:       # %bb.0:

 ; RV64IM-NEXT:    lh a1, 16(a1)
 ; RV64IM-NEXT:    mulh a6, a2, a3
 ; RV64IM-NEXT:    add a6, a6, a2
 ; RV64IM-NEXT:    srli a7, a6, 63
 ; RV64IM-NEXT:    srai a6, a6, 6
 ; RV64IM-NEXT:    addw a6, a6, a7
 ; RV64IM-NEXT:    li a7, 95
 ; RV64IM-NEXT:    mulw t0, a6, a7
-; RV64IM-NEXT:    subw a2, a2, t0
-; RV64IM-NEXT:    mulh t0, a1, a3
-; RV64IM-NEXT:    add t0, t0, a1
-; RV64IM-NEXT:    srli t1, t0, 63
-; RV64IM-NEXT:    srai t0, t0, 6
-; RV64IM-NEXT:    addw t0, t0, t1
-; RV64IM-NEXT:    mulw t1, t0, a7
-; RV64IM-NEXT:    subw a1, a1, t1
-; RV64IM-NEXT:    mulh t1, a5, a3
-; RV64IM-NEXT:    add t1, t1, a5
+; RV64IM-NEXT:    mulh t1, a1, a3
+; RV64IM-NEXT:    add t1, t1, a1
 ; RV64IM-NEXT:    srli t2, t1, 63
 ; RV64IM-NEXT:    srai t1, t1, 6
 ; RV64IM-NEXT:    addw t1, t1, t2
 ; RV64IM-NEXT:    mulw t2, t1, a7
-; RV64IM-NEXT:    subw a5, a5, t2
+; RV64IM-NEXT:    mulh t3, a5, a3
+; RV64IM-NEXT:    add t3, t3, a5
+; RV64IM-NEXT:    srli t4, t3, 63
+; RV64IM-NEXT:    srai t3, t3, 6
+; RV64IM-NEXT:    addw t3, t3, t4
+; RV64IM-NEXT:    mulw t4, t3, a7
 ; RV64IM-NEXT:    mulh a3, a4, a3
 ; RV64IM-NEXT:    add a3, a3, a4
-; RV64IM-NEXT:    srli t2, a3, 63
+; RV64IM-NEXT:    srli t5, a3, 63
 ; RV64IM-NEXT:    srai a3, a3, 6
-; RV64IM-NEXT:    addw a3, a3, t2
+; RV64IM-NEXT:    addw a3, a3, t5
 ; RV64IM-NEXT:    mulw a7, a3, a7
-; RV64IM-NEXT:    subw a4, a4, a7
-; RV64IM-NEXT:    addw a3, a4, a3
-; RV64IM-NEXT:    addw a4, a5, t1
-; RV64IM-NEXT:    addw a1, a1, t0
-; RV64IM-NEXT:    addw a2, a2, a6
+; RV64IM-NEXT:    subw a3, a7, a3
+; RV64IM-NEXT:    subw a4, a4, a3
+; RV64IM-NEXT:    subw a3, t4, t3
+; RV64IM-NEXT:    subw a5, a5, a3
+; RV64IM-NEXT:    subw a3, t2, t1
+; RV64IM-NEXT:    subw a1, a1, a3
+; RV64IM-NEXT:    subw a3, t0, a6
+; RV64IM-NEXT:    subw a2, a2, a3
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    sh a4, 2(a0)
-; RV64IM-NEXT:    sh a3, 0(a0)
+; RV64IM-NEXT:    sh a5, 2(a0)
+; RV64IM-NEXT:    sh a4, 0(a0)
 ; RV64IM-NEXT:    ret
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %3 = add <4 x i16> %1, %2
   ret <4 x i16> %3
 }
 
 ; Don't fold for divisors that are a power of two.

llvm/test/CodeGen/RISCV/ssub_sat.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32-LABEL: func2:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    mv a4, a1
 ; RV32-NEXT:    sltu a1, a0, a2
-; RV32-NEXT:    sub a5, a4, a3
-; RV32-NEXT:    sub a1, a5, a1
+; RV32-NEXT:    add a1, a3, a1
+; RV32-NEXT:    sub a1, a4, a1
 ; RV32-NEXT:    xor a5, a4, a1
 ; RV32-NEXT:    xor a3, a4, a3
 ; RV32-NEXT:    and a3, a3, a5
 ; RV32-NEXT:    bltz a3, .LBB1_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a0, a0, a2
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB1_2:

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

; RV64IZbb-NEXT:    ret
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32-LABEL: func64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    mv a2, a1
 ; RV32-NEXT:    sltu a1, a0, a4
-; RV32-NEXT:    sub a3, a2, a5
-; RV32-NEXT:    sub a1, a3, a1
+; RV32-NEXT:    add a1, a5, a1
+; RV32-NEXT:    sub a1, a2, a1
 ; RV32-NEXT:    xor a3, a2, a1
 ; RV32-NEXT:    xor a2, a2, a5
 ; RV32-NEXT:    and a2, a2, a3
 ; RV32-NEXT:    bltz a2, .LBB1_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a0, a0, a4
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB1_2:

llvm/test/CodeGen/RISCV/uadd_sat.ll

 ; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a3, a1, a3
 ; RV32I-NEXT:    add a2, a0, a2
 ; RV32I-NEXT:    sltu a0, a2, a0
 ; RV32I-NEXT:    add a3, a3, a0
+; RV32I-NEXT:    add a3, a1, a3
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a3, a1
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    neg a1, a0
 ; RV32I-NEXT:    or a0, a1, a2
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a1, a0, a1
 ; RV64I-NEXT:    sltu a0, a1, a0
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    add a3, a1, a3
 ; RV32IZbb-NEXT:    add a2, a0, a2
 ; RV32IZbb-NEXT:    sltu a0, a2, a0
 ; RV32IZbb-NEXT:    add a3, a3, a0
+; RV32IZbb-NEXT:    add a3, a1, a3
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a3, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    neg a1, a0
 ; RV32IZbb-NEXT:    or a0, a1, a2
 ; RV32IZbb-NEXT:    or a1, a1, a3
 ; RV32IZbb-NEXT:    ret

llvm/test/CodeGen/RISCV/uadd_sat_plus.ll

; RV64IZbb-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    add a2, a1, a5
 ; RV32I-NEXT:    add a4, a0, a4
 ; RV32I-NEXT:    sltu a0, a4, a0
-; RV32I-NEXT:    add a2, a2, a0
+; RV32I-NEXT:    add a2, a5, a0
+; RV32I-NEXT:    add a2, a1, a2
 ; RV32I-NEXT:    beq a2, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a2, a1
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    neg a1, a0
 ; RV32I-NEXT:    or a0, a1, a4
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    add a2, a0, a2
 ; RV64I-NEXT:    sltu a0, a2, a0
 ; RV64I-NEXT:    neg a0, a0
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    add a2, a1, a5
 ; RV32IZbb-NEXT:    add a4, a0, a4
 ; RV32IZbb-NEXT:    sltu a0, a4, a0
-; RV32IZbb-NEXT:    add a2, a2, a0
+; RV32IZbb-NEXT:    add a2, a5, a0
+; RV32IZbb-NEXT:    add a2, a1, a2
 ; RV32IZbb-NEXT:    beq a2, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a2, a1
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    neg a1, a0
 ; RV32IZbb-NEXT:    or a0, a1, a4
 ; RV32IZbb-NEXT:    or a1, a1, a2
 ; RV32IZbb-NEXT:    ret

llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
 ; RISCV32-LABEL: muloti_test:
 ; RISCV32:       # %bb.0: # %start
 ; RISCV32-NEXT:    addi sp, sp, -32
 ; RISCV32-NEXT:    sw s0, 28(sp) # 4-byte Folded Spill
 ; RISCV32-NEXT:    sw s1, 24(sp) # 4-byte Folded Spill
 ; RISCV32-NEXT:    sw s2, 20(sp) # 4-byte Folded Spill
 ; RISCV32-NEXT:    sw s3, 16(sp) # 4-byte Folded Spill
 ; RISCV32-NEXT:    sw s4, 12(sp) # 4-byte Folded Spill
-; RISCV32-NEXT:    lw a3, 12(a1)
+; RISCV32-NEXT:    lw a4, 12(a1)
 ; RISCV32-NEXT:    lw a7, 12(a2)
 ; RISCV32-NEXT:    lw a6, 8(a1)
-; RISCV32-NEXT:    lw a4, 0(a2)
+; RISCV32-NEXT:    lw a3, 0(a2)
 ; RISCV32-NEXT:    lw a5, 0(a1)
 ; RISCV32-NEXT:    lw t3, 4(a1)
 ; RISCV32-NEXT:    lw t0, 8(a2)
 ; RISCV32-NEXT:    lw a2, 4(a2)
-; RISCV32-NEXT:    mulhu a1, a5, a4
-; RISCV32-NEXT:    mul t1, t3, a4
+; RISCV32-NEXT:    mulhu a1, a5, a3
+; RISCV32-NEXT:    mul t1, t3, a3
 ; RISCV32-NEXT:    add a1, t1, a1
 ; RISCV32-NEXT:    sltu t1, a1, t1
-; RISCV32-NEXT:    mulhu t2, t3, a4
+; RISCV32-NEXT:    mulhu t2, t3, a3
 ; RISCV32-NEXT:    add t4, t2, t1
 ; RISCV32-NEXT:    mul t1, a5, a2
 ; RISCV32-NEXT:    add a1, t1, a1
 ; RISCV32-NEXT:    sltu t1, a1, t1
 ; RISCV32-NEXT:    mulhu t2, a5, a2
 ; RISCV32-NEXT:    add t1, t2, t1
 ; RISCV32-NEXT:    add t5, t4, t1
 ; RISCV32-NEXT:    mul t6, t3, a2
 ; RISCV32-NEXT:    add s0, t6, t5
 ; RISCV32-NEXT:    mul t1, t0, a5
-; RISCV32-NEXT:    mul s3, a6, a4
+; RISCV32-NEXT:    mul s3, a6, a3
 ; RISCV32-NEXT:    add s4, s3, t1
 ; RISCV32-NEXT:    add t1, s0, s4
 ; RISCV32-NEXT:    sltu t2, t1, s0
-; RISCV32-NEXT:    sltu s0, s0, t6
+; RISCV32-NEXT:    sltu t6, s0, t6
 ; RISCV32-NEXT:    sltu t4, t5, t4
-; RISCV32-NEXT:    mulhu t5, t3, a2
-; RISCV32-NEXT:    add t4, t5, t4
-; RISCV32-NEXT:    add s0, t4, s0
+; RISCV32-NEXT:    mulhu s1, t3, a2
+; RISCV32-NEXT:    add t4, t4, t6
+; RISCV32-NEXT:    add s1, s1, t4
 ; RISCV32-NEXT:    mul t4, t3, t0
-; RISCV32-NEXT:    mul t5, a7, a5
-; RISCV32-NEXT:    add t4, t5, t4
-; RISCV32-NEXT:    mulhu s1, t0, a5
-; RISCV32-NEXT:    add s2, s1, t4
+; RISCV32-NEXT:    mul s2, a7, a5
+; RISCV32-NEXT:    mulhu s0, t0, a5
+; RISCV32-NEXT:    add t4, s0, t4
+; RISCV32-NEXT:    add s2, t4, s2
 ; RISCV32-NEXT:    mul t4, a2, a6
-; RISCV32-NEXT:    mul t5, a3, a4
+; RISCV32-NEXT:    mul t6, a4, a3
+; RISCV32-NEXT:    mulhu t5, a6, a3
 ; RISCV32-NEXT:    add t4, t5, t4
-; RISCV32-NEXT:    mulhu t5, a6, a4
-; RISCV32-NEXT:    add t6, t5, t4
-; RISCV32-NEXT:    add t4, t6, s2
-; RISCV32-NEXT:    sltu s3, s4, s3
-; RISCV32-NEXT:    add t4, t4, s3
-; RISCV32-NEXT:    add t4, s0, t4
+; RISCV32-NEXT:    add t6, t4, t6
+; RISCV32-NEXT:    sltu t4, s4, s3
+; RISCV32-NEXT:    add t4, s2, t4
+; RISCV32-NEXT:    add t4, t6, t4
 ; RISCV32-NEXT:    add t4, t4, t2
-; RISCV32-NEXT:    beq t4, s0, .LBB0_2
+; RISCV32-NEXT:    add t4, s1, t4
+; RISCV32-NEXT:    beq t4, s1, .LBB0_2
 ; RISCV32-NEXT:  # %bb.1: # %start
-; RISCV32-NEXT:    sltu t2, t4, s0
+; RISCV32-NEXT:    sltu t2, t4, s1
 ; RISCV32-NEXT:  .LBB0_2: # %start
-; RISCV32-NEXT:    sltu s0, s2, s1
+; RISCV32-NEXT:    sltu s0, s2, s0
 ; RISCV32-NEXT:    snez s1, t3
 ; RISCV32-NEXT:    snez s2, a7
 ; RISCV32-NEXT:    and s1, s2, s1
 ; RISCV32-NEXT:    mulhu s2, a7, a5
 ; RISCV32-NEXT:    snez s2, s2
-; RISCV32-NEXT:    or s1, s1, s2
 ; RISCV32-NEXT:    mulhu t3, t3, t0
 ; RISCV32-NEXT:    snez t3, t3
-; RISCV32-NEXT:    or t3, s1, t3
+; RISCV32-NEXT:    or t3, s2, t3
 ; RISCV32-NEXT:    or t3, t3, s0
+; RISCV32-NEXT:    or t3, s1, t3
 ; RISCV32-NEXT:    sltu t5, t6, t5
 ; RISCV32-NEXT:    snez t6, a2
-; RISCV32-NEXT:    snez s0, a3
+; RISCV32-NEXT:    snez s0, a4
 ; RISCV32-NEXT:    and t6, s0, t6
-; RISCV32-NEXT:    mulhu s0, a3, a4
+; RISCV32-NEXT:    mulhu s0, a4, a3
 ; RISCV32-NEXT:    snez s0, s0
-; RISCV32-NEXT:    or t6, t6, s0
 ; RISCV32-NEXT:    mulhu a2, a2, a6
 ; RISCV32-NEXT:    snez a2, a2
-; RISCV32-NEXT:    or a2, t6, a2
+; RISCV32-NEXT:    or a2, s0, a2
 ; RISCV32-NEXT:    or a2, a2, t5
 ; RISCV32-NEXT:    or a7, t0, a7
 ; RISCV32-NEXT:    snez a7, a7
-; RISCV32-NEXT:    or a3, a6, a3
-; RISCV32-NEXT:    snez a3, a3
-; RISCV32-NEXT:    and a3, a3, a7
-; RISCV32-NEXT:    or a2, a3, a2
-; RISCV32-NEXT:    or a2, a2, t3
-; RISCV32-NEXT:    or a2, a2, t2
-; RISCV32-NEXT:    mul a3, a5, a4
+; RISCV32-NEXT:    or a4, a6, a4
+; RISCV32-NEXT:    snez a4, a4
+; RISCV32-NEXT:    and a4, a4, a7
+; RISCV32-NEXT:    or a2, a4, a2
+; RISCV32-NEXT:    or a4, t6, t3
+; RISCV32-NEXT:    or a4, a4, t2
+; RISCV32-NEXT:    or a2, a2, a4
+; RISCV32-NEXT:    mul a3, a5, a3
 ; RISCV32-NEXT:    andi a2, a2, 1
 ; RISCV32-NEXT:    sw a3, 0(a0)
 ; RISCV32-NEXT:    sw a1, 4(a0)
 ; RISCV32-NEXT:    sw t1, 8(a0)
 ; RISCV32-NEXT:    sw t4, 12(a0)
 ; RISCV32-NEXT:    sb a2, 16(a0)
 ; RISCV32-NEXT:    lw s0, 28(sp) # 4-byte Folded Reload
 ; RISCV32-NEXT:    lw s1, 24(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/unaligned-load-store.ll

; MISALIGN-NEXT:    ret
   %res = load i16, ptr %p, align 1
   ret i16 %res
 }
 
 define i24 @load_i24(ptr %p) {
 ; NOMISALIGN-LABEL: load_i24:
 ; NOMISALIGN:       # %bb.0:
 ; NOMISALIGN-NEXT:    lbu a1, 1(a0)
-; NOMISALIGN-NEXT:    lbu a2, 0(a0)
-; NOMISALIGN-NEXT:    lb a0, 2(a0)
+; NOMISALIGN-NEXT:    lb a2, 2(a0)
+; NOMISALIGN-NEXT:    lbu a0, 0(a0)
 ; NOMISALIGN-NEXT:    slli a1, a1, 8
-; NOMISALIGN-NEXT:    or a1, a1, a2
-; NOMISALIGN-NEXT:    slli a0, a0, 16
+; NOMISALIGN-NEXT:    slli a2, a2, 16
+; NOMISALIGN-NEXT:    or a0, a0, a2
 ; NOMISALIGN-NEXT:    or a0, a1, a0
 ; NOMISALIGN-NEXT:    ret
 ;
 ; MISALIGN-LABEL: load_i24:
 ; MISALIGN:       # %bb.0:
 ; MISALIGN-NEXT:    lb a1, 2(a0)
 ; MISALIGN-NEXT:    lhu a0, 0(a0)
 ; MISALIGN-NEXT:    slli a1, a1, 16

 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 0(a0)
 ; RV32I-NEXT:    lbu a3, 2(a0)
 ; RV32I-NEXT:    lbu a0, 3(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    slli a3, a3, 16
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a3
+; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 0(a0)
 ; RV64I-NEXT:    lbu a3, 2(a0)
 ; RV64I-NEXT:    lb a0, 3(a0)
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a3, a3, 16
 ; RV64I-NEXT:    slli a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a1, a3, a1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; MISALIGN-LABEL: load_i32:
 ; MISALIGN:       # %bb.0:
 ; MISALIGN-NEXT:    lw a0, 0(a0)
 ; MISALIGN-NEXT:    ret
   %res = load i32, ptr %p, align 1
   ret i32 %res
 }
 
 define i64 @load_i64(ptr %p) {
 ; RV32I-LABEL: load_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lbu a1, 1(a0)
 ; RV32I-NEXT:    lbu a2, 0(a0)
 ; RV32I-NEXT:    lbu a3, 2(a0)
 ; RV32I-NEXT:    lbu a4, 3(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    slli a3, a3, 16
 ; RV32I-NEXT:    slli a4, a4, 24
-; RV32I-NEXT:    or a2, a4, a3
-; RV32I-NEXT:    or a2, a2, a1
+; RV32I-NEXT:    or a1, a3, a1
+; RV32I-NEXT:    or a2, a4, a1
 ; RV32I-NEXT:    lbu a1, 5(a0)
 ; RV32I-NEXT:    lbu a3, 4(a0)
 ; RV32I-NEXT:    lbu a4, 6(a0)
 ; RV32I-NEXT:    lbu a0, 7(a0)
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    slli a4, a4, 16
 ; RV32I-NEXT:    slli a0, a0, 24
-; RV32I-NEXT:    or a0, a0, a4
+; RV32I-NEXT:    or a1, a4, a1
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: load_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lbu a1, 1(a0)
 ; RV64I-NEXT:    lbu a2, 0(a0)
 ; RV64I-NEXT:    lbu a3, 2(a0)
-; RV64I-NEXT:    lbu a4, 3(a0)
 ; RV64I-NEXT:    slli a1, a1, 8
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    slli a3, a3, 16
-; RV64I-NEXT:    slli a4, a4, 24
-; RV64I-NEXT:    or a3, a4, a3
-; RV64I-NEXT:    or a1, a3, a1
 ; RV64I-NEXT:    lbu a2, 5(a0)
+; RV64I-NEXT:    lbu a4, 3(a0)
+; RV64I-NEXT:    or a1, a3, a1
 ; RV64I-NEXT:    lbu a3, 4(a0)
-; RV64I-NEXT:    lbu a4, 6(a0)
-; RV64I-NEXT:    lbu a0, 7(a0)
 ; RV64I-NEXT:    slliw a2, a2, 8
+; RV64I-NEXT:    lbu a5, 6(a0)
+; RV64I-NEXT:    lbu a0, 7(a0)
 ; RV64I-NEXT:    or a2, a2, a3
-; RV64I-NEXT:    slliw a3, a4, 16
+; RV64I-NEXT:    slli a4, a4, 24
+; RV64I-NEXT:    slliw a3, a5, 16
 ; RV64I-NEXT:    slliw a0, a0, 24
-; RV64I-NEXT:    or a0, a0, a3
+; RV64I-NEXT:    or a2, a3, a2
 ; RV64I-NEXT:    or a0, a0, a2
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    or a0, a0, a4
 ; RV64I-NEXT:    ret
 ;
 ; MISALIGN-RV32I-LABEL: load_i64:
 ; MISALIGN-RV32I:       # %bb.0:
 ; MISALIGN-RV32I-NEXT:    lw a2, 0(a0)
 ; MISALIGN-RV32I-NEXT:    lw a1, 4(a0)
 ; MISALIGN-RV32I-NEXT:    mv a0, a2
 ; MISALIGN-RV32I-NEXT:    ret

llvm/test/CodeGen/RISCV/urem-lkk.ll

 ; RV32IM-NEXT:    addi a1, a1, 777
 ; RV32IM-NEXT:    mulhu a1, a0, a1
 ; RV32IM-NEXT:    sub a2, a0, a1
 ; RV32IM-NEXT:    srli a2, a2, 1
 ; RV32IM-NEXT:    add a1, a2, a1
 ; RV32IM-NEXT:    srli a1, a1, 6
 ; RV32IM-NEXT:    li a2, 95
 ; RV32IM-NEXT:    mul a2, a1, a2
+; RV32IM-NEXT:    sub a2, a2, a1
 ; RV32IM-NEXT:    sub a0, a0, a2
-; RV32IM-NEXT:    add a0, a0, a1
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill

 ; RV64IM-NEXT:    mulhu a1, a1, a2
 ; RV64IM-NEXT:    srli a1, a1, 32
 ; RV64IM-NEXT:    subw a2, a0, a1
 ; RV64IM-NEXT:    srliw a2, a2, 1
 ; RV64IM-NEXT:    add a1, a2, a1
 ; RV64IM-NEXT:    srli a1, a1, 6
 ; RV64IM-NEXT:    li a2, 95
 ; RV64IM-NEXT:    mulw a2, a1, a2
+; RV64IM-NEXT:    subw a2, a2, a1
 ; RV64IM-NEXT:    subw a0, a0, a2
-; RV64IM-NEXT:    addw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 95
   %2 = udiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 
 ; Don't fold for divisors that are a power of two.

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

; RV64MV-NEXT:    ret
   %cmp = icmp eq i27 %urem, 0
   ret i1 %cmp
 }
 
 define i1 @test_urem_odd_setne(i4 %X) nounwind {
 ; RV32-LABEL: test_urem_odd_setne:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    slli a1, a0, 1
-; RV32-NEXT:    add a0, a1, a0
 ; RV32-NEXT:    neg a0, a0
+; RV32-NEXT:    sub a0, a0, a1
 ; RV32-NEXT:    andi a0, a0, 15
 ; RV32-NEXT:    sltiu a0, a0, 4
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_odd_setne:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    slliw a1, a0, 1
-; RV64-NEXT:    addw a0, a1, a0
 ; RV64-NEXT:    negw a0, a0
+; RV64-NEXT:    subw a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 15
 ; RV64-NEXT:    sltiu a0, a0, 4
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32M-LABEL: test_urem_odd_setne:
 ; RV32M:       # %bb.0:
 ; RV32M-NEXT:    slli a1, a0, 1
-; RV32M-NEXT:    add a0, a1, a0
 ; RV32M-NEXT:    neg a0, a0
+; RV32M-NEXT:    sub a0, a0, a1
 ; RV32M-NEXT:    andi a0, a0, 15
 ; RV32M-NEXT:    sltiu a0, a0, 4
 ; RV32M-NEXT:    xori a0, a0, 1
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_urem_odd_setne:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    slliw a1, a0, 1
-; RV64M-NEXT:    addw a0, a1, a0
 ; RV64M-NEXT:    negw a0, a0
+; RV64M-NEXT:    subw a0, a0, a1
 ; RV64M-NEXT:    andi a0, a0, 15
 ; RV64M-NEXT:    sltiu a0, a0, 4
 ; RV64M-NEXT:    xori a0, a0, 1
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_urem_odd_setne:
 ; RV32MV:       # %bb.0:
 ; RV32MV-NEXT:    slli a1, a0, 1
-; RV32MV-NEXT:    add a0, a1, a0
 ; RV32MV-NEXT:    neg a0, a0
+; RV32MV-NEXT:    sub a0, a0, a1
 ; RV32MV-NEXT:    andi a0, a0, 15
 ; RV32MV-NEXT:    sltiu a0, a0, 4
 ; RV32MV-NEXT:    xori a0, a0, 1
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_urem_odd_setne:
 ; RV64MV:       # %bb.0:
 ; RV64MV-NEXT:    slliw a1, a0, 1
-; RV64MV-NEXT:    addw a0, a1, a0
 ; RV64MV-NEXT:    negw a0, a0
+; RV64MV-NEXT:    subw a0, a0, a1
 ; RV64MV-NEXT:    andi a0, a0, 15
 ; RV64MV-NEXT:    sltiu a0, a0, 4
 ; RV64MV-NEXT:    xori a0, a0, 1
 ; RV64MV-NEXT:    ret
   %urem = urem i4 %X, 5
   %cmp = icmp ne i4 %urem, 0
   ret i1 %cmp
 }

 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    addi s1, s1, -1
 ; RV32-NEXT:    slli a1, s1, 21
 ; RV32-NEXT:    srli a1, a1, 31
 ; RV32-NEXT:    sb a1, 4(s0)
 ; RV32-NEXT:    andi a1, s3, 2047
 ; RV32-NEXT:    andi a0, a0, 2047
 ; RV32-NEXT:    slli a0, a0, 11
-; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    slli s1, s1, 22
 ; RV32-NEXT:    or a0, a0, s1
+; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    sw a0, 0(s0)
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret

 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    sltiu a0, a0, 2
 ; RV64-NEXT:    addiw s3, s3, -1
 ; RV64-NEXT:    addi a0, a0, -1
 ; RV64-NEXT:    addiw s2, s2, -1
 ; RV64-NEXT:    andi a1, s3, 2047
 ; RV64-NEXT:    andi a2, s2, 2047
 ; RV64-NEXT:    slli a2, a2, 11
-; RV64-NEXT:    or a1, a1, a2
 ; RV64-NEXT:    slli a0, a0, 22
+; RV64-NEXT:    or a0, a2, a0
 ; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    sw a0, 0(s0)
 ; RV64-NEXT:    slli a0, a0, 31
 ; RV64-NEXT:    srli a0, a0, 63
 ; RV64-NEXT:    sb a0, 4(s0)
 ; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload

 ; RV32M-NEXT:    addi a3, a3, -1
 ; RV32M-NEXT:    addi a1, a1, -1
 ; RV32M-NEXT:    slli a4, a1, 21
 ; RV32M-NEXT:    srli a4, a4, 31
 ; RV32M-NEXT:    sb a4, 4(a0)
 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    andi a3, a3, 2047
 ; RV32M-NEXT:    slli a3, a3, 11
-; RV32M-NEXT:    or a2, a2, a3
 ; RV32M-NEXT:    slli a1, a1, 22
+; RV32M-NEXT:    or a1, a3, a1
 ; RV32M-NEXT:    or a1, a2, a1
 ; RV32M-NEXT:    sw a1, 0(a0)
 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_urem_vec:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    lbu a1, 4(a0)
 ; RV64M-NEXT:    lwu a2, 0(a0)

 ; RV64M-NEXT:    andi a2, a2, 2047
 ; RV64M-NEXT:    sltiu a2, a2, 2
 ; RV64M-NEXT:    addiw a1, a1, -1
 ; RV64M-NEXT:    addi a2, a2, -1
 ; RV64M-NEXT:    addiw a3, a3, -1
 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    andi a3, a3, 2047
 ; RV64M-NEXT:    slli a3, a3, 11
-; RV64M-NEXT:    or a1, a1, a3
 ; RV64M-NEXT:    slli a2, a2, 22
+; RV64M-NEXT:    or a2, a3, a2
 ; RV64M-NEXT:    or a1, a1, a2
 ; RV64M-NEXT:    sw a1, 0(a0)
 ; RV64M-NEXT:    slli a1, a1, 31
 ; RV64M-NEXT:    srli a1, a1, 63
 ; RV64M-NEXT:    sb a1, 4(a0)
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_urem_vec:

 ; RV32MV-NEXT:    srli a2, a2, 31
 ; RV32MV-NEXT:    sb a2, 4(a0)
 ; RV32MV-NEXT:    vmv.x.s a2, v8
 ; RV32MV-NEXT:    andi a2, a2, 2047
 ; RV32MV-NEXT:    vslidedown.vi v8, v8, 1
 ; RV32MV-NEXT:    vmv.x.s a3, v8
 ; RV32MV-NEXT:    andi a3, a3, 2047
 ; RV32MV-NEXT:    slli a3, a3, 11
-; RV32MV-NEXT:    or a2, a2, a3
 ; RV32MV-NEXT:    slli a1, a1, 22
+; RV32MV-NEXT:    or a1, a3, a1
 ; RV32MV-NEXT:    or a1, a2, a1
 ; RV32MV-NEXT:    sw a1, 0(a0)
 ; RV32MV-NEXT:    addi sp, sp, 16
 ; RV32MV-NEXT:    ret
 ;
 ; RV64MV-LABEL: test_urem_vec:
 ; RV64MV:       # %bb.0:
 ; RV64MV-NEXT:    addi sp, sp, -16

 ; RV64MV-NEXT:    vmerge.vim v8, v10, -1, v0
 ; RV64MV-NEXT:    vmv.x.s a1, v8
 ; RV64MV-NEXT:    andi a1, a1, 2047
 ; RV64MV-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
 ; RV64MV-NEXT:    vslidedown.vi v9, v8, 1
 ; RV64MV-NEXT:    vmv.x.s a2, v9
 ; RV64MV-NEXT:    andi a2, a2, 2047
 ; RV64MV-NEXT:    slli a2, a2, 11
-; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    vslidedown.vi v8, v8, 2
-; RV64MV-NEXT:    vmv.x.s a2, v8
-; RV64MV-NEXT:    slli a2, a2, 22
+; RV64MV-NEXT:    vmv.x.s a3, v8
+; RV64MV-NEXT:    slli a3, a3, 22
+; RV64MV-NEXT:    or a2, a2, a3
 ; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    sw a1, 0(a0)
 ; RV64MV-NEXT:    slli a1, a1, 31
 ; RV64MV-NEXT:    srli a1, a1, 63
 ; RV64MV-NEXT:    sb a1, 4(a0)
 ; RV64MV-NEXT:    addi sp, sp, 16
 ; RV64MV-NEXT:    ret
   %ld = load <3 x i11>, ptr %X
   %urem = urem <3 x i11> %ld, <i11 6, i11 7, i11 -5>
   %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
   %ext = sext <3 x i1> %cmp to <3 x i11>
   store <3 x i11> %ext, ptr %X
   ret void
 }

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

 ; RV32IM-NEXT:    addi a5, a5, 777
 ; RV32IM-NEXT:    mulhu a6, a4, a5
 ; RV32IM-NEXT:    sub a7, a4, a6
 ; RV32IM-NEXT:    srli a7, a7, 1
 ; RV32IM-NEXT:    add a6, a7, a6
 ; RV32IM-NEXT:    srli a6, a6, 6
 ; RV32IM-NEXT:    li a7, 95
 ; RV32IM-NEXT:    mul t0, a6, a7
-; RV32IM-NEXT:    sub a4, a4, t0
-; RV32IM-NEXT:    mulhu t0, a1, a5
-; RV32IM-NEXT:    sub t1, a1, t0
-; RV32IM-NEXT:    srli t1, t1, 1
-; RV32IM-NEXT:    add t0, t1, t0
-; RV32IM-NEXT:    srli t0, t0, 6
-; RV32IM-NEXT:    mul t1, t0, a7
-; RV32IM-NEXT:    sub a1, a1, t1
-; RV32IM-NEXT:    mulhu t1, a3, a5
-; RV32IM-NEXT:    sub t2, a3, t1
+; RV32IM-NEXT:    mulhu t1, a1, a5
+; RV32IM-NEXT:    sub t2, a1, t1
 ; RV32IM-NEXT:    srli t2, t2, 1
 ; RV32IM-NEXT:    add t1, t2, t1
 ; RV32IM-NEXT:    srli t1, t1, 6
 ; RV32IM-NEXT:    mul t2, t1, a7
-; RV32IM-NEXT:    sub a3, a3, t2
+; RV32IM-NEXT:    mulhu t3, a3, a5
+; RV32IM-NEXT:    sub t4, a3, t3
+; RV32IM-NEXT:    srli t4, t4, 1
+; RV32IM-NEXT:    add t3, t4, t3
+; RV32IM-NEXT:    srli t3, t3, 6
+; RV32IM-NEXT:    mul t4, t3, a7
 ; RV32IM-NEXT:    mulhu a5, a2, a5
-; RV32IM-NEXT:    sub t2, a2, a5
-; RV32IM-NEXT:    srli t2, t2, 1
-; RV32IM-NEXT:    add a5, t2, a5
+; RV32IM-NEXT:    sub t5, a2, a5
+; RV32IM-NEXT:    srli t5, t5, 1
+; RV32IM-NEXT:    add a5, t5, a5
 ; RV32IM-NEXT:    srli a5, a5, 6
 ; RV32IM-NEXT:    mul a7, a5, a7
-; RV32IM-NEXT:    sub a2, a2, a7
-; RV32IM-NEXT:    add a2, a2, a5
-; RV32IM-NEXT:    add a3, a3, t1
-; RV32IM-NEXT:    add a1, a1, t0
-; RV32IM-NEXT:    add a4, a4, a6
+; RV32IM-NEXT:    sub a5, a7, a5
+; RV32IM-NEXT:    sub a2, a2, a5
+; RV32IM-NEXT:    sub a5, t4, t3
+; RV32IM-NEXT:    sub a3, a3, a5
+; RV32IM-NEXT:    sub a5, t2, t1
+; RV32IM-NEXT:    sub a1, a1, a5
+; RV32IM-NEXT:    sub a5, t0, a6
+; RV32IM-NEXT:    sub a4, a4, a5
 ; RV32IM-NEXT:    sh a4, 6(a0)
 ; RV32IM-NEXT:    sh a1, 4(a0)
 ; RV32IM-NEXT:    sh a3, 2(a0)
 ; RV32IM-NEXT:    sh a2, 0(a0)
 ; RV32IM-NEXT:    ret
 ;
 ; RV64I-LABEL: combine_urem_udiv:
 ; RV64I:       # %bb.0:

 ; RV64IM-NEXT:    lhu a1, 16(a1)
 ; RV64IM-NEXT:    mulhu a6, a2, a3
 ; RV64IM-NEXT:    sub a7, a2, a6
 ; RV64IM-NEXT:    srli a7, a7, 1
 ; RV64IM-NEXT:    add a6, a7, a6
 ; RV64IM-NEXT:    srli a6, a6, 6
 ; RV64IM-NEXT:    li a7, 95
 ; RV64IM-NEXT:    mulw t0, a6, a7
-; RV64IM-NEXT:    subw a2, a2, t0
-; RV64IM-NEXT:    mulhu t0, a1, a3
-; RV64IM-NEXT:    sub t1, a1, t0
-; RV64IM-NEXT:    srli t1, t1, 1
-; RV64IM-NEXT:    add t0, t1, t0
-; RV64IM-NEXT:    srli t0, t0, 6
-; RV64IM-NEXT:    mulw t1, t0, a7
-; RV64IM-NEXT:    subw a1, a1, t1
-; RV64IM-NEXT:    mulhu t1, a5, a3
-; RV64IM-NEXT:    sub t2, a5, t1
+; RV64IM-NEXT:    mulhu t1, a1, a3
+; RV64IM-NEXT:    sub t2, a1, t1
 ; RV64IM-NEXT:    srli t2, t2, 1
 ; RV64IM-NEXT:    add t1, t2, t1
 ; RV64IM-NEXT:    srli t1, t1, 6
 ; RV64IM-NEXT:    mulw t2, t1, a7
-; RV64IM-NEXT:    subw a5, a5, t2
+; RV64IM-NEXT:    mulhu t3, a5, a3
+; RV64IM-NEXT:    sub t4, a5, t3
+; RV64IM-NEXT:    srli t4, t4, 1
+; RV64IM-NEXT:    add t3, t4, t3
+; RV64IM-NEXT:    srli t3, t3, 6
+; RV64IM-NEXT:    mulw t4, t3, a7
 ; RV64IM-NEXT:    mulhu a3, a4, a3
-; RV64IM-NEXT:    sub t2, a4, a3
-; RV64IM-NEXT:    srli t2, t2, 1
-; RV64IM-NEXT:    add a3, t2, a3
+; RV64IM-NEXT:    sub t5, a4, a3
+; RV64IM-NEXT:    srli t5, t5, 1
+; RV64IM-NEXT:    add a3, t5, a3
 ; RV64IM-NEXT:    srli a3, a3, 6
 ; RV64IM-NEXT:    mulw a7, a3, a7
-; RV64IM-NEXT:    subw a4, a4, a7
-; RV64IM-NEXT:    addw a3, a4, a3
-; RV64IM-NEXT:    addw a4, a5, t1
-; RV64IM-NEXT:    addw a1, a1, t0
-; RV64IM-NEXT:    addw a2, a2, a6
+; RV64IM-NEXT:    subw a3, a7, a3
+; RV64IM-NEXT:    subw a4, a4, a3
+; RV64IM-NEXT:    subw a3, t4, t3
+; RV64IM-NEXT:    subw a5, a5, a3
+; RV64IM-NEXT:    subw a3, t2, t1
+; RV64IM-NEXT:    subw a1, a1, a3
+; RV64IM-NEXT:    subw a3, t0, a6
+; RV64IM-NEXT:    subw a2, a2, a3
 ; RV64IM-NEXT:    sh a2, 6(a0)
 ; RV64IM-NEXT:    sh a1, 4(a0)
-; RV64IM-NEXT:    sh a4, 2(a0)
-; RV64IM-NEXT:    sh a3, 0(a0)
+; RV64IM-NEXT:    sh a5, 2(a0)
+; RV64IM-NEXT:    sh a4, 0(a0)
 ; RV64IM-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %3 = add <4 x i16> %1, %2
   ret <4 x i16> %3
 }
 
 ; Don't fold for divisors that are a power of two.

llvm/test/CodeGen/RISCV/usub_sat.ll

; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
 
 define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: func2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a4, a0, a2
+; RV32I-NEXT:    add a3, a3, a4
 ; RV32I-NEXT:    sub a3, a1, a3
-; RV32I-NEXT:    sub a3, a3, a4
 ; RV32I-NEXT:    sub a2, a0, a2
 ; RV32I-NEXT:    beq a3, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a3
 ; RV32I-NEXT:    j .LBB1_3
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    sltu a0, a0, a2
 ; RV32I-NEXT:  .LBB1_3:
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    and a0, a1, a2
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a1
 ; RV64I-NEXT:    sltu a0, a0, a1
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func2:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    sltu a4, a0, a2
+; RV32IZbb-NEXT:    add a3, a3, a4
 ; RV32IZbb-NEXT:    sub a3, a1, a3
-; RV32IZbb-NEXT:    sub a3, a3, a4
 ; RV32IZbb-NEXT:    sub a2, a0, a2
 ; RV32IZbb-NEXT:    beq a3, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a1, a3
 ; RV32IZbb-NEXT:    j .LBB1_3
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    sltu a0, a0, a2
 ; RV32IZbb-NEXT:  .LBB1_3:

llvm/test/CodeGen/RISCV/usub_sat_plus.ll

; RV64IZbb-NEXT:    ret
   %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
 }
 
 define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV32I-LABEL: func64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a2, a0, a4
-; RV32I-NEXT:    sub a3, a1, a5
-; RV32I-NEXT:    sub a2, a3, a2
+; RV32I-NEXT:    add a2, a5, a2
+; RV32I-NEXT:    sub a2, a1, a2
 ; RV32I-NEXT:    sub a3, a0, a4
 ; RV32I-NEXT:    beq a2, a1, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    sltu a0, a1, a2
 ; RV32I-NEXT:    j .LBB1_3
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    sltu a0, a0, a3
 ; RV32I-NEXT:  .LBB1_3:
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    and a0, a1, a3
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sub a1, a0, a2
 ; RV64I-NEXT:    sltu a0, a0, a1
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbb-LABEL: func64:
 ; RV32IZbb:       # %bb.0:
 ; RV32IZbb-NEXT:    sltu a2, a0, a4
-; RV32IZbb-NEXT:    sub a3, a1, a5
-; RV32IZbb-NEXT:    sub a2, a3, a2
+; RV32IZbb-NEXT:    add a2, a5, a2
+; RV32IZbb-NEXT:    sub a2, a1, a2
 ; RV32IZbb-NEXT:    sub a3, a0, a4
 ; RV32IZbb-NEXT:    beq a2, a1, .LBB1_2
 ; RV32IZbb-NEXT:  # %bb.1:
 ; RV32IZbb-NEXT:    sltu a0, a1, a2
 ; RV32IZbb-NEXT:    j .LBB1_3
 ; RV32IZbb-NEXT:  .LBB1_2:
 ; RV32IZbb-NEXT:    sltu a0, a0, a3
 ; RV32IZbb-NEXT:  .LBB1_3:

llvm/test/CodeGen/RISCV/vararg.ll

 ; ILP32-ILP32F-FPELIM-NEXT:    sw a6, 24(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a5, 20(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a4, 16(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a3, 12(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, sp, 19
 ; ILP32-ILP32F-FPELIM-NEXT:    andi a0, a0, -8
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a3, sp, 27
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a3, 4(sp)
-; ILP32-ILP32F-FPELIM-NEXT:    lw a3, 4(a0)
-; ILP32-ILP32F-FPELIM-NEXT:    lw a0, 0(a0)
-; ILP32-ILP32F-FPELIM-NEXT:    add a2, a2, a3
-; ILP32-ILP32F-FPELIM-NEXT:    add a0, a1, a0
+; ILP32-ILP32F-FPELIM-NEXT:    lw a3, 0(a0)
+; ILP32-ILP32F-FPELIM-NEXT:    lw a4, 4(a0)
+; ILP32-ILP32F-FPELIM-NEXT:    add a0, a1, a3
 ; ILP32-ILP32F-FPELIM-NEXT:    sltu a1, a0, a1
+; ILP32-ILP32F-FPELIM-NEXT:    add a1, a4, a1
 ; ILP32-ILP32F-FPELIM-NEXT:    add a1, a2, a1
 ; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 32
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va3:
 ; ILP32-ILP32F-WITHFP:       # %bb.0:
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, -48
 ; ILP32-ILP32F-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
 ; ILP32-ILP32F-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
 ; ILP32-ILP32F-WITHFP-NEXT:    addi s0, sp, 24
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a7, 20(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a6, 16(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a5, 12(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a4, 8(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a3, 4(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, s0, 11
 ; ILP32-ILP32F-WITHFP-NEXT:    andi a0, a0, -8
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a3, s0, 19
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a3, -12(s0)
-; ILP32-ILP32F-WITHFP-NEXT:    lw a3, 4(a0)
-; ILP32-ILP32F-WITHFP-NEXT:    lw a0, 0(a0)
-; ILP32-ILP32F-WITHFP-NEXT:    add a2, a2, a3
-; ILP32-ILP32F-WITHFP-NEXT:    add a0, a1, a0
+; ILP32-ILP32F-WITHFP-NEXT:    lw a3, 0(a0)
+; ILP32-ILP32F-WITHFP-NEXT:    lw a4, 4(a0)
+; ILP32-ILP32F-WITHFP-NEXT:    add a0, a1, a3
 ; ILP32-ILP32F-WITHFP-NEXT:    sltu a1, a0, a1
+; ILP32-ILP32F-WITHFP-NEXT:    add a1, a4, a1
 ; ILP32-ILP32F-WITHFP-NEXT:    add a1, a2, a1
 ; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 48
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3:
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM:       # %bb.0:
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a7, 28(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a6, 24(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a5, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a4, 16(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 12(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, sp, 19
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    andi a0, a0, -8
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a3, sp, 27
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 4(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a3, 4(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a2, a2, a3
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a0
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a3, 0(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a4, 4(a0)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a3
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sltu a1, a0, a1
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a4, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a2, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 32
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va3:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -64
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 56(sp)

 ; ILP32-ILP32F-FPELIM-NEXT:    ori a3, a0, 4
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a3, 4(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lw a3, 0(a0)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a4, a0, 8
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a4, 4(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lw a4, 4(a0)
 ; ILP32-ILP32F-FPELIM-NEXT:    add a0, a1, a3
 ; ILP32-ILP32F-FPELIM-NEXT:    sltu a1, a0, a1
-; ILP32-ILP32F-FPELIM-NEXT:    add a2, a2, a4
+; ILP32-ILP32F-FPELIM-NEXT:    add a1, a4, a1
 ; ILP32-ILP32F-FPELIM-NEXT:    add a1, a2, a1
 ; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 32
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va3_va_arg:
 ; ILP32-ILP32F-WITHFP:       # %bb.0:
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, -48
 ; ILP32-ILP32F-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill

 ; ILP32-ILP32F-WITHFP-NEXT:    ori a3, a0, 4
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a3, -12(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    lw a3, 0(a0)
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a4, a0, 8
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a4, -12(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    lw a4, 4(a0)
 ; ILP32-ILP32F-WITHFP-NEXT:    add a0, a1, a3
 ; ILP32-ILP32F-WITHFP-NEXT:    sltu a1, a0, a1
-; ILP32-ILP32F-WITHFP-NEXT:    add a2, a2, a4
+; ILP32-ILP32F-WITHFP-NEXT:    add a1, a4, a1
 ; ILP32-ILP32F-WITHFP-NEXT:    add a1, a2, a1
 ; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 20(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 16(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 48
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va3_va_arg:
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM:       # %bb.0:
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, -48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a7, 44(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a6, 40(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a5, 36(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 28(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, sp, 35
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    andi a0, a0, -8
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a3, a0, 8
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 20(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    fld ft0, 0(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    fsd ft0, 8(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 12(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a3, 8(sp)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a2, a2, a0
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a3
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 8(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a3, 12(sp)
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sltu a1, a0, a1
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a3, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a2, a1
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va3_va_arg:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, -64
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a7, 56(sp)

 ; ILP32-ILP32F-FPELIM-NEXT:    addi a2, a0, 4
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a2, 4(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lw a2, 0(a0)
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a0, a0, 7
 ; ILP32-ILP32F-FPELIM-NEXT:    andi a0, a0, -4
 ; ILP32-ILP32F-FPELIM-NEXT:    addi a3, a0, 4
 ; ILP32-ILP32F-FPELIM-NEXT:    sw a3, 4(sp)
 ; ILP32-ILP32F-FPELIM-NEXT:    lw a0, 0(a0)
-; ILP32-ILP32F-FPELIM-NEXT:    add a1, a1, s0
-; ILP32-ILP32F-FPELIM-NEXT:    add a1, a1, a2
+; ILP32-ILP32F-FPELIM-NEXT:    add a2, s0, a2
+; ILP32-ILP32F-FPELIM-NEXT:    add a0, a2, a0
 ; ILP32-ILP32F-FPELIM-NEXT:    add a0, a1, a0
 ; ILP32-ILP32F-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-FPELIM-NEXT:    addi sp, sp, 48
 ; ILP32-ILP32F-FPELIM-NEXT:    ret
 ;
 ; ILP32-ILP32F-WITHFP-LABEL: va4_va_copy:
 ; ILP32-ILP32F-WITHFP:       # %bb.0:

 ; ILP32-ILP32F-WITHFP-NEXT:    addi a2, a0, 4
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a2, -16(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    lw a2, 0(a0)
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a0, a0, 7
 ; ILP32-ILP32F-WITHFP-NEXT:    andi a0, a0, -4
 ; ILP32-ILP32F-WITHFP-NEXT:    addi a3, a0, 4
 ; ILP32-ILP32F-WITHFP-NEXT:    sw a3, -16(s0)
 ; ILP32-ILP32F-WITHFP-NEXT:    lw a0, 0(a0)
-; ILP32-ILP32F-WITHFP-NEXT:    add a1, a1, s1
-; ILP32-ILP32F-WITHFP-NEXT:    add a1, a1, a2
+; ILP32-ILP32F-WITHFP-NEXT:    add a2, s1, a2
+; ILP32-ILP32F-WITHFP-NEXT:    add a0, a2, a0
 ; ILP32-ILP32F-WITHFP-NEXT:    add a0, a1, a0
 ; ILP32-ILP32F-WITHFP-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; ILP32-ILP32F-WITHFP-NEXT:    addi sp, sp, 64
 ; ILP32-ILP32F-WITHFP-NEXT:    ret
 ;
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va4_va_copy:

 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a2, a0, 4
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a2, 4(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a2, 0(a0)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a0, a0, 7
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    andi a0, a0, -4
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi a3, a0, 4
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    sw a3, 4(sp)
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw a0, 0(a0)
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a1, s0
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a1, a1, a2
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a2, s0, a2
+; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a2, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    add a0, a1, a0
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    addi sp, sp, 48
 ; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-FPELIM-LABEL: va4_va_copy:
 ; LP64-LP64F-LP64D-FPELIM:       # %bb.0:

 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a2, a0, 8
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a2, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ld a2, 0(a0)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, 11
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    andi a0, a0, -4
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a3, a0, 8
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a3, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ld a0, 0(a0)
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addw a1, a1, s0
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addw a1, a1, a2
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addw a2, s0, a2
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addw a0, a2, a0
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addw a0, a1, a0
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    ret
 ;
 ; LP64-LP64F-LP64D-WITHFP-LABEL: va4_va_copy:
 ; LP64-LP64F-LP64D-WITHFP:       # %bb.0:

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a2, a0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, -32(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld a2, 0(a0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, 11
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    andi a0, a0, -4
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a3, a0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a3, -32(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld a0, 0(a0)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a1, a1, s1
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a1, a1, a2
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a2, s1, a2
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a0, a2, a0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a0, a1, a0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 112
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
   %vargs = alloca ptr, align 4
   %wargs = alloca ptr, align 4

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: saddo1.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a5, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a5, a5, a0
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a5, a1, a0
 ; RV32-NEXT:    xor a0, a1, a5
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
 ; RV32-NEXT:    slti a0, a0, 0
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo1.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a3, a0, a1
 ; RV64-NEXT:    slt a0, a3, a0
 ; RV64-NEXT:    slti a1, a1, 0
 ; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    sd a3, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo1.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a5, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
-; RV32ZBA-NEXT:    add a5, a5, a0
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    add a5, a1, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a5
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
 ; RV32ZBA-NEXT:    slti a0, a0, 0
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    ret
entry:
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: uaddo.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a3, a3, a0
+; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    beq a3, a1, .LBB10_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a3, a1
 ; RV32-NEXT:  .LBB10_2: # %entry
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a1
 ; RV64-NEXT:    sltu a0, a1, a0
 ; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a3, a3, a0
+; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    beq a3, a1, .LBB10_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a3, a1
 ; RV32ZBA-NEXT:  .LBB10_2: # %entry
 ; RV32ZBA-NEXT:    sw a2, 0(a4)
 ; RV32ZBA-NEXT:    sw a3, 4(a4)
 ; RV32ZBA-NEXT:    ret
 ;
entry:
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: ssubo.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a5, a0, a2
-; RV32-NEXT:    sub a6, a1, a3
-; RV32-NEXT:    sub a5, a6, a5
+; RV32-NEXT:    add a5, a3, a5
+; RV32-NEXT:    sub a5, a1, a5
 ; RV32-NEXT:    xor a6, a1, a5
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a1, a1, a6
 ; RV32-NEXT:    slti a1, a1, 0
 ; RV32-NEXT:    sub a0, a0, a2
 ; RV32-NEXT:    sw a0, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a3, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
 ; RV64-NEXT:    xor a0, a3, a0
 ; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a5, a0, a2
-; RV32ZBA-NEXT:    sub a6, a1, a3
-; RV32ZBA-NEXT:    sub a5, a6, a5
+; RV32ZBA-NEXT:    add a5, a3, a5
+; RV32ZBA-NEXT:    sub a5, a1, a5
 ; RV32ZBA-NEXT:    xor a6, a1, a5
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    and a1, a1, a6
 ; RV32ZBA-NEXT:    slti a1, a1, 0
 ; RV32ZBA-NEXT:    sub a0, a0, a2
 ; RV32ZBA-NEXT:    sw a0, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    mv a0, a1
entry:
   store i32 %val, ptr %res
   ret i1 %obit
 }
 
 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: usubo.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a5, a0, a2
+; RV32-NEXT:    add a3, a3, a5
 ; RV32-NEXT:    sub a3, a1, a3
-; RV32-NEXT:    sub a3, a3, a5
 ; RV32-NEXT:    sub a2, a0, a2
 ; RV32-NEXT:    beq a3, a1, .LBB18_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
 ; RV32-NEXT:    j .LBB18_3
 ; RV32-NEXT:  .LBB18_2:
 ; RV32-NEXT:    sltu a0, a0, a2
 ; RV32-NEXT:  .LBB18_3: # %entry
 ; RV32-NEXT:    sw a2, 0(a4)
 ; RV32-NEXT:    sw a3, 4(a4)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    sltu a0, a0, a1
 ; RV64-NEXT:    sd a1, 0(a2)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a5, a0, a2
+; RV32ZBA-NEXT:    add a3, a3, a5
 ; RV32ZBA-NEXT:    sub a3, a1, a3
-; RV32ZBA-NEXT:    sub a3, a3, a5
 ; RV32ZBA-NEXT:    sub a2, a0, a2
 ; RV32ZBA-NEXT:    beq a3, a1, .LBB18_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
 ; RV32ZBA-NEXT:    j .LBB18_3
 ; RV32ZBA-NEXT:  .LBB18_2:
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
 ; RV32ZBA-NEXT:  .LBB18_3: # %entry

 ; RV32-NEXT:    srai t4, a3, 31
 ; RV32-NEXT:    mul t5, t4, a0
 ; RV32-NEXT:    add t6, t5, t3
 ; RV32-NEXT:    add s0, t1, t6
 ; RV32-NEXT:    sltu s1, s0, t1
 ; RV32-NEXT:    sltu t0, t1, t0
 ; RV32-NEXT:    sltu a6, a7, a6
 ; RV32-NEXT:    mulhu a7, a1, a3
-; RV32-NEXT:    add a6, a7, a6
 ; RV32-NEXT:    add a6, a6, t0
-; RV32-NEXT:    mulhu a7, a2, t2
-; RV32-NEXT:    add a7, a7, t3
+; RV32-NEXT:    mulhu t0, a2, t2
 ; RV32-NEXT:    mul a3, a3, t2
-; RV32-NEXT:    add a3, a7, a3
+; RV32-NEXT:    add a3, t3, a3
+; RV32-NEXT:    add a3, t0, a3
 ; RV32-NEXT:    mul a1, t4, a1
-; RV32-NEXT:    mulhu a7, t4, a0
-; RV32-NEXT:    add a1, a7, a1
+; RV32-NEXT:    mulhu t0, t4, a0
 ; RV32-NEXT:    add a1, a1, t5
 ; RV32-NEXT:    add a1, a1, a3
 ; RV32-NEXT:    sltu a3, t6, t5
 ; RV32-NEXT:    add a1, a1, a3
+; RV32-NEXT:    add a1, t0, a1
 ; RV32-NEXT:    add a1, a6, a1
 ; RV32-NEXT:    add a1, a1, s1
+; RV32-NEXT:    add a1, a7, a1
 ; RV32-NEXT:    srai a3, a5, 31
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    xor a3, s0, a3
 ; RV32-NEXT:    or a1, a3, a1
 ; RV32-NEXT:    snez a1, a1
 ; RV32-NEXT:    mul a0, a0, a2
 ; RV32-NEXT:    sw a0, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)

 ; RV32ZBA-NEXT:    srai t4, a3, 31
 ; RV32ZBA-NEXT:    mul t5, t4, a0
 ; RV32ZBA-NEXT:    add t6, t5, t3
 ; RV32ZBA-NEXT:    add s0, t1, t6
 ; RV32ZBA-NEXT:    sltu s1, s0, t1
 ; RV32ZBA-NEXT:    sltu t0, t1, t0
 ; RV32ZBA-NEXT:    sltu a6, a7, a6
 ; RV32ZBA-NEXT:    mulhu a7, a1, a3
-; RV32ZBA-NEXT:    add a6, a7, a6
 ; RV32ZBA-NEXT:    add a6, a6, t0
-; RV32ZBA-NEXT:    mulhu a7, a2, t2
-; RV32ZBA-NEXT:    add a7, a7, t3
+; RV32ZBA-NEXT:    mulhu t0, a2, t2
 ; RV32ZBA-NEXT:    mul a3, a3, t2
-; RV32ZBA-NEXT:    add a3, a7, a3
+; RV32ZBA-NEXT:    add a3, t3, a3
+; RV32ZBA-NEXT:    add a3, t0, a3
 ; RV32ZBA-NEXT:    mul a1, t4, a1
-; RV32ZBA-NEXT:    mulhu a7, t4, a0
-; RV32ZBA-NEXT:    add a1, a7, a1
+; RV32ZBA-NEXT:    mulhu t0, t4, a0
 ; RV32ZBA-NEXT:    add a1, a1, t5
 ; RV32ZBA-NEXT:    add a1, a1, a3
 ; RV32ZBA-NEXT:    sltu a3, t6, t5
 ; RV32ZBA-NEXT:    add a1, a1, a3
+; RV32ZBA-NEXT:    add a1, t0, a1
 ; RV32ZBA-NEXT:    add a1, a6, a1
 ; RV32ZBA-NEXT:    add a1, a1, s1
+; RV32ZBA-NEXT:    add a1, a7, a1
 ; RV32ZBA-NEXT:    srai a3, a5, 31
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    xor a3, s0, a3
 ; RV32ZBA-NEXT:    or a1, a3, a1
 ; RV32ZBA-NEXT:    snez a1, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a2
 ; RV32ZBA-NEXT:    sw a0, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
; RV64ZBA-NEXT:    ret
   ret i32 %6
 }
 
 define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, ptr %res) {
 ; RV32-LABEL: umulo.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mul a5, a3, a0
 ; RV32-NEXT:    mul a6, a1, a2
-; RV32-NEXT:    add a5, a6, a5
-; RV32-NEXT:    mulhu a6, a0, a2
-; RV32-NEXT:    add a5, a6, a5
-; RV32-NEXT:    sltu a6, a5, a6
+; RV32-NEXT:    mulhu a7, a0, a2
+; RV32-NEXT:    add a5, a7, a5
+; RV32-NEXT:    add a5, a5, a6
+; RV32-NEXT:    sltu a6, a5, a7
 ; RV32-NEXT:    snez a7, a3
 ; RV32-NEXT:    snez t0, a1
 ; RV32-NEXT:    and a7, t0, a7
 ; RV32-NEXT:    mulhu a1, a1, a2
 ; RV32-NEXT:    snez a1, a1
-; RV32-NEXT:    or a1, a7, a1
 ; RV32-NEXT:    mulhu a3, a3, a0
 ; RV32-NEXT:    snez a3, a3
 ; RV32-NEXT:    or a1, a1, a3
 ; RV32-NEXT:    or a1, a1, a6
+; RV32-NEXT:    or a1, a7, a1
 ; RV32-NEXT:    mul a0, a0, a2
 ; RV32-NEXT:    sw a0, 0(a4)
 ; RV32-NEXT:    sw a5, 4(a4)
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a3, a0, a1
 ; RV64-NEXT:    snez a3, a3
 ; RV64-NEXT:    mul a0, a0, a1
 ; RV64-NEXT:    sd a0, 0(a2)
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a5, a3, a0
 ; RV32ZBA-NEXT:    mul a6, a1, a2
-; RV32ZBA-NEXT:    add a5, a6, a5
-; RV32ZBA-NEXT:    mulhu a6, a0, a2
-; RV32ZBA-NEXT:    add a5, a6, a5
-; RV32ZBA-NEXT:    sltu a6, a5, a6
+; RV32ZBA-NEXT:    mulhu a7, a0, a2
+; RV32ZBA-NEXT:    add a5, a7, a5
+; RV32ZBA-NEXT:    add a5, a5, a6
+; RV32ZBA-NEXT:    sltu a6, a5, a7
 ; RV32ZBA-NEXT:    snez a7, a3
 ; RV32ZBA-NEXT:    snez t0, a1
 ; RV32ZBA-NEXT:    and a7, t0, a7
 ; RV32ZBA-NEXT:    mulhu a1, a1, a2
 ; RV32ZBA-NEXT:    snez a1, a1
-; RV32ZBA-NEXT:    or a1, a7, a1
 ; RV32ZBA-NEXT:    mulhu a3, a3, a0
 ; RV32ZBA-NEXT:    snez a3, a3
 ; RV32ZBA-NEXT:    or a1, a1, a3
 ; RV32ZBA-NEXT:    or a1, a1, a6
+; RV32ZBA-NEXT:    or a1, a7, a1
 ; RV32ZBA-NEXT:    mul a0, a0, a2
 ; RV32ZBA-NEXT:    sw a0, 0(a4)
 ; RV32ZBA-NEXT:    sw a5, 4(a4)
 ; RV32ZBA-NEXT:    mv a0, a1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.i64:
 ; RV64ZBA:       # %bb.0: # %entry
entry:
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: saddo.select.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a4, a1, a3
-; RV32-NEXT:    add a5, a0, a2
-; RV32-NEXT:    sltu a5, a5, a0
-; RV32-NEXT:    add a4, a4, a5
+; RV32-NEXT:    add a4, a0, a2
+; RV32-NEXT:    sltu a4, a4, a0
+; RV32-NEXT:    add a4, a3, a4
+; RV32-NEXT:    add a4, a1, a4
 ; RV32-NEXT:    xor a4, a1, a4
 ; RV32-NEXT:    xor a5, a1, a3
 ; RV32-NEXT:    not a5, a5
 ; RV32-NEXT:    and a4, a5, a4
 ; RV32-NEXT:    bltz a4, .LBB30_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB30_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a2, a2, a0
 ; RV64-NEXT:    slti a3, a1, 0
 ; RV64-NEXT:    bne a3, a2, .LBB30_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB30_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a4, a1, a3
-; RV32ZBA-NEXT:    add a5, a0, a2
-; RV32ZBA-NEXT:    sltu a5, a5, a0
-; RV32ZBA-NEXT:    add a4, a4, a5
+; RV32ZBA-NEXT:    add a4, a0, a2
+; RV32ZBA-NEXT:    sltu a4, a4, a0
+; RV32ZBA-NEXT:    add a4, a3, a4
+; RV32ZBA-NEXT:    add a4, a1, a4
 ; RV32ZBA-NEXT:    xor a4, a1, a4
 ; RV32ZBA-NEXT:    xor a5, a1, a3
 ; RV32ZBA-NEXT:    not a5, a5
 ; RV32ZBA-NEXT:    and a4, a5, a4
 ; RV32ZBA-NEXT:    bltz a4, .LBB30_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
entry:
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @saddo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: saddo.not.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a0, a4, a0
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a0, a1, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
 ; RV32-NEXT:    slti a0, a0, 0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: saddo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    slt a0, a2, a0
 ; RV64-NEXT:    slti a1, a1, 0
 ; RV64-NEXT:    xor a0, a1, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a4, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
-; RV32ZBA-NEXT:    add a0, a4, a0
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    add a0, a1, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
 ; RV32ZBA-NEXT:    slti a0, a0, 0
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
entry:
   %obit = extractvalue {i32, i1} %t, 1
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.select.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a5, a1, a3
 ; RV32-NEXT:    add a4, a0, a2
 ; RV32-NEXT:    sltu a4, a4, a0
-; RV32-NEXT:    add a5, a5, a4
+; RV32-NEXT:    add a5, a3, a4
+; RV32-NEXT:    add a5, a1, a5
 ; RV32-NEXT:    bne a5, a1, .LBB34_3
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    beqz a4, .LBB34_4
 ; RV32-NEXT:  .LBB34_2: # %entry
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB34_3: # %entry
 ; RV32-NEXT:    sltu a4, a5, a1
 ; RV32-NEXT:    bnez a4, .LBB34_2
 ; RV32-NEXT:  .LBB34_4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a2, a0, a1
 ; RV64-NEXT:    bltu a2, a0, .LBB34_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB34_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a5, a1, a3
 ; RV32ZBA-NEXT:    add a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a4, a0
-; RV32ZBA-NEXT:    add a5, a5, a4
+; RV32ZBA-NEXT:    add a5, a3, a4
+; RV32ZBA-NEXT:    add a5, a1, a5
 ; RV32ZBA-NEXT:    bne a5, a1, .LBB34_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    beqz a4, .LBB34_4
 ; RV32ZBA-NEXT:  .LBB34_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB34_3: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a5, a1
 ; RV32ZBA-NEXT:    bnez a4, .LBB34_2
entry:
   %obit = extractvalue {i64, i1} %t, 1
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @uaddo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.not.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
+; RV32-NEXT:    add a2, a1, a2
 ; RV32-NEXT:    beq a2, a1, .LBB35_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
 ; RV32-NEXT:  .LBB35_2: # %entry
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a1, a0, a1
 ; RV64-NEXT:    sltu a0, a1, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
+; RV32ZBA-NEXT:    add a2, a1, a2
 ; RV32ZBA-NEXT:    beq a2, a1, .LBB35_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
 ; RV32ZBA-NEXT:  .LBB35_2: # %entry
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: uaddo.not.i64:
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: ssubo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
-; RV32-NEXT:    sub a5, a1, a3
-; RV32-NEXT:    sub a5, a5, a4
-; RV32-NEXT:    xor a5, a1, a5
-; RV32-NEXT:    xor a4, a1, a3
-; RV32-NEXT:    and a4, a4, a5
+; RV32-NEXT:    add a4, a3, a4
+; RV32-NEXT:    sub a4, a1, a4
+; RV32-NEXT:    xor a4, a1, a4
+; RV32-NEXT:    xor a5, a1, a3
+; RV32-NEXT:    and a4, a5, a4
 ; RV32-NEXT:    bltz a4, .LBB38_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB38_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a3, a0, a1
 ; RV64-NEXT:    slt a3, a3, a0
 ; RV64-NEXT:    bne a2, a3, .LBB38_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB38_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
-; RV32ZBA-NEXT:    sub a5, a1, a3
-; RV32ZBA-NEXT:    sub a5, a5, a4
-; RV32ZBA-NEXT:    xor a5, a1, a5
-; RV32ZBA-NEXT:    xor a4, a1, a3
-; RV32ZBA-NEXT:    and a4, a4, a5
+; RV32ZBA-NEXT:    add a4, a3, a4
+; RV32ZBA-NEXT:    sub a4, a1, a4
+; RV32ZBA-NEXT:    xor a4, a1, a4
+; RV32ZBA-NEXT:    xor a5, a1, a3
+; RV32ZBA-NEXT:    and a4, a5, a4
 ; RV32ZBA-NEXT:    bltz a4, .LBB38_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
 ; RV32ZBA-NEXT:  .LBB38_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.select.i64:
entry:
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @ssub.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: ssub.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a0, a0, a2
-; RV32-NEXT:    sub a2, a1, a3
-; RV32-NEXT:    sub a2, a2, a0
-; RV32-NEXT:    xor a2, a1, a2
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    sub a0, a1, a0
+; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    slti a0, a1, 0
+; RV32-NEXT:    and a0, a1, a0
+; RV32-NEXT:    slti a0, a0, 0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssub.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
 ; RV64-NEXT:    xor a0, a2, a0
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssub.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
-; RV32ZBA-NEXT:    sub a2, a1, a3
-; RV32ZBA-NEXT:    sub a2, a2, a0
-; RV32ZBA-NEXT:    xor a2, a1, a2
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    sub a0, a1, a0
+; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
-; RV32ZBA-NEXT:    and a1, a1, a2
-; RV32ZBA-NEXT:    slti a0, a1, 0
+; RV32ZBA-NEXT:    and a0, a1, a0
+; RV32ZBA-NEXT:    slti a0, a0, 0
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssub.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    sgtz a2, a1
 ; RV64ZBA-NEXT:    sub a1, a0, a1
 ; RV64ZBA-NEXT:    slt a0, a1, a0
entry:
   %ret = xor i1 %obit, true
   ret i1 %ret
 }
 
 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
-; RV32-NEXT:    sub a5, a1, a3
-; RV32-NEXT:    sub a4, a5, a4
+; RV32-NEXT:    add a4, a3, a4
+; RV32-NEXT:    sub a4, a1, a4
 ; RV32-NEXT:    beq a4, a1, .LBB42_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a4, a1, a4
 ; RV32-NEXT:    beqz a4, .LBB42_3
 ; RV32-NEXT:    j .LBB42_4
 ; RV32-NEXT:  .LBB42_2:
 ; RV32-NEXT:    sub a4, a0, a2
 ; RV32-NEXT:    sltu a4, a0, a4

 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB42_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
-; RV32ZBA-NEXT:    sub a5, a1, a3
-; RV32ZBA-NEXT:    sub a4, a5, a4
+; RV32ZBA-NEXT:    add a4, a3, a4
+; RV32ZBA-NEXT:    sub a4, a1, a4
 ; RV32ZBA-NEXT:    beq a4, a1, .LBB42_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a1, a4
 ; RV32ZBA-NEXT:    beqz a4, .LBB42_3
 ; RV32ZBA-NEXT:    j .LBB42_4
 ; RV32ZBA-NEXT:  .LBB42_2:
 ; RV32ZBA-NEXT:    sub a4, a0, a2
 ; RV32ZBA-NEXT:    sltu a4, a0, a4
entry:
   %ret = select i1 %obit, i64 %v1, i64 %v2
   ret i64 %ret
 }
 
 define i1 @usubo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
+; RV32-NEXT:    add a3, a3, a4
 ; RV32-NEXT:    sub a3, a1, a3
-; RV32-NEXT:    sub a3, a3, a4
 ; RV32-NEXT:    beq a3, a1, .LBB43_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB43_2:
 ; RV32-NEXT:    sub a1, a0, a2
 ; RV32-NEXT:    sltu a0, a0, a1
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    sltu a0, a0, a1
 ; RV64-NEXT:    xori a0, a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
+; RV32ZBA-NEXT:    add a3, a3, a4
 ; RV32ZBA-NEXT:    sub a3, a1, a3
-; RV32ZBA-NEXT:    sub a3, a3, a4
 ; RV32ZBA-NEXT:    beq a3, a1, .LBB43_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB43_2:
 ; RV32ZBA-NEXT:    sub a1, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a0, a1

 ; RV32-NEXT:    srai t3, a3, 31
 ; RV32-NEXT:    mul t4, t3, a0
 ; RV32-NEXT:    add t5, t4, t2
 ; RV32-NEXT:    add t6, t0, t5
 ; RV32-NEXT:    sltu s0, t6, t0
 ; RV32-NEXT:    sltu a7, t0, a7
 ; RV32-NEXT:    sltu a5, a6, a5
 ; RV32-NEXT:    mulhu a6, a1, a3
-; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    add a5, a5, a7
-; RV32-NEXT:    mulhu a6, a2, t1
-; RV32-NEXT:    add a6, a6, t2
-; RV32-NEXT:    mul a7, a3, t1
-; RV32-NEXT:    add a6, a6, a7
-; RV32-NEXT:    mul a7, t3, a1
-; RV32-NEXT:    mulhu t0, t3, a0
+; RV32-NEXT:    mulhu a7, a2, t1
+; RV32-NEXT:    mul t0, a3, t1
+; RV32-NEXT:    add t0, t2, t0
+; RV32-NEXT:    add a7, a7, t0
+; RV32-NEXT:    mul t0, t3, a1
+; RV32-NEXT:    mulhu t1, t3, a0
+; RV32-NEXT:    add t0, t0, t4
 ; RV32-NEXT:    add a7, t0, a7
-; RV32-NEXT:    add a7, a7, t4
-; RV32-NEXT:    add a6, a7, a6
-; RV32-NEXT:    sltu a7, t5, t4
-; RV32-NEXT:    add a6, a6, a7
-; RV32-NEXT:    add a5, a5, a6
+; RV32-NEXT:    sltu t0, t5, t4
+; RV32-NEXT:    add a7, a7, t0
+; RV32-NEXT:    add a7, t1, a7
+; RV32-NEXT:    add a5, a5, a7
 ; RV32-NEXT:    add a5, a5, s0
+; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    srai a4, a4, 31
 ; RV32-NEXT:    xor a5, a5, a4
 ; RV32-NEXT:    xor a4, t6, a4
 ; RV32-NEXT:    or a4, a4, a5
 ; RV32-NEXT:    bnez a4, .LBB46_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3

 ; RV32ZBA-NEXT:    srai t3, a3, 31
 ; RV32ZBA-NEXT:    mul t4, t3, a0
 ; RV32ZBA-NEXT:    add t5, t4, t2
 ; RV32ZBA-NEXT:    add t6, t0, t5
 ; RV32ZBA-NEXT:    sltu s0, t6, t0
 ; RV32ZBA-NEXT:    sltu a7, t0, a7
 ; RV32ZBA-NEXT:    sltu a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a6, a1, a3
-; RV32ZBA-NEXT:    add a5, a6, a5
 ; RV32ZBA-NEXT:    add a5, a5, a7
-; RV32ZBA-NEXT:    mulhu a6, a2, t1
-; RV32ZBA-NEXT:    add a6, a6, t2
-; RV32ZBA-NEXT:    mul a7, a3, t1
-; RV32ZBA-NEXT:    add a6, a6, a7
-; RV32ZBA-NEXT:    mul a7, t3, a1
-; RV32ZBA-NEXT:    mulhu t0, t3, a0
+; RV32ZBA-NEXT:    mulhu a7, a2, t1
+; RV32ZBA-NEXT:    mul t0, a3, t1
+; RV32ZBA-NEXT:    add t0, t2, t0
+; RV32ZBA-NEXT:    add a7, a7, t0
+; RV32ZBA-NEXT:    mul t0, t3, a1
+; RV32ZBA-NEXT:    mulhu t1, t3, a0
+; RV32ZBA-NEXT:    add t0, t0, t4
 ; RV32ZBA-NEXT:    add a7, t0, a7
-; RV32ZBA-NEXT:    add a7, a7, t4
-; RV32ZBA-NEXT:    add a6, a7, a6
-; RV32ZBA-NEXT:    sltu a7, t5, t4
-; RV32ZBA-NEXT:    add a6, a6, a7
-; RV32ZBA-NEXT:    add a5, a5, a6
+; RV32ZBA-NEXT:    sltu t0, t5, t4
+; RV32ZBA-NEXT:    add a7, a7, t0
+; RV32ZBA-NEXT:    add a7, t1, a7
+; RV32ZBA-NEXT:    add a5, a5, a7
 ; RV32ZBA-NEXT:    add a5, a5, s0
+; RV32ZBA-NEXT:    add a5, a6, a5
 ; RV32ZBA-NEXT:    srai a4, a4, 31
 ; RV32ZBA-NEXT:    xor a5, a5, a4
 ; RV32ZBA-NEXT:    xor a4, t6, a4
 ; RV32ZBA-NEXT:    or a4, a4, a5
 ; RV32ZBA-NEXT:    bnez a4, .LBB46_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3

 ; RV32-NEXT:    srai t3, a3, 31
 ; RV32-NEXT:    mul t4, t3, a0
 ; RV32-NEXT:    add t5, t4, t2
 ; RV32-NEXT:    add t6, t0, t5
 ; RV32-NEXT:    sltu s0, t6, t0
 ; RV32-NEXT:    sltu a7, t0, a7
 ; RV32-NEXT:    sltu a5, a6, a5
 ; RV32-NEXT:    mulhu a6, a1, a3
-; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    add a5, a5, a7
 ; RV32-NEXT:    mulhu a2, a2, t1
-; RV32-NEXT:    add a2, a2, t2
 ; RV32-NEXT:    mul a3, a3, t1
+; RV32-NEXT:    add a3, t2, a3
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    mul a1, t3, a1
 ; RV32-NEXT:    mulhu a0, t3, a0
-; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    add a0, a0, t4
-; RV32-NEXT:    add a0, a0, a2
-; RV32-NEXT:    sltu a1, t5, t4
+; RV32-NEXT:    add a1, a1, t4
+; RV32-NEXT:    add a1, a1, a2
+; RV32-NEXT:    sltu a2, t5, t4
+; RV32-NEXT:    add a1, a1, a2
 ; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    add a0, a5, a0
 ; RV32-NEXT:    add a0, a0, s0
+; RV32-NEXT:    add a0, a6, a0
 ; RV32-NEXT:    srai a4, a4, 31
 ; RV32-NEXT:    xor a0, a0, a4
 ; RV32-NEXT:    xor a1, t6, a4
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    seqz a0, a0
 ; RV32-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret

 ; RV32ZBA-NEXT:    srai t3, a3, 31
 ; RV32ZBA-NEXT:    mul t4, t3, a0
 ; RV32ZBA-NEXT:    add t5, t4, t2
 ; RV32ZBA-NEXT:    add t6, t0, t5
 ; RV32ZBA-NEXT:    sltu s0, t6, t0
 ; RV32ZBA-NEXT:    sltu a7, t0, a7
 ; RV32ZBA-NEXT:    sltu a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a6, a1, a3
-; RV32ZBA-NEXT:    add a5, a6, a5
 ; RV32ZBA-NEXT:    add a5, a5, a7
 ; RV32ZBA-NEXT:    mulhu a2, a2, t1
-; RV32ZBA-NEXT:    add a2, a2, t2
 ; RV32ZBA-NEXT:    mul a3, a3, t1
+; RV32ZBA-NEXT:    add a3, t2, a3
 ; RV32ZBA-NEXT:    add a2, a2, a3
 ; RV32ZBA-NEXT:    mul a1, t3, a1
 ; RV32ZBA-NEXT:    mulhu a0, t3, a0
-; RV32ZBA-NEXT:    add a0, a0, a1
-; RV32ZBA-NEXT:    add a0, a0, t4
-; RV32ZBA-NEXT:    add a0, a0, a2
-; RV32ZBA-NEXT:    sltu a1, t5, t4
+; RV32ZBA-NEXT:    add a1, a1, t4
+; RV32ZBA-NEXT:    add a1, a1, a2
+; RV32ZBA-NEXT:    sltu a2, t5, t4
+; RV32ZBA-NEXT:    add a1, a1, a2
 ; RV32ZBA-NEXT:    add a0, a0, a1
 ; RV32ZBA-NEXT:    add a0, a5, a0
 ; RV32ZBA-NEXT:    add a0, a0, s0
+; RV32ZBA-NEXT:    add a0, a6, a0
 ; RV32ZBA-NEXT:    srai a4, a4, 31
 ; RV32ZBA-NEXT:    xor a0, a0, a4
 ; RV32ZBA-NEXT:    xor a1, t6, a4
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    seqz a0, a0
 ; RV32ZBA-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBA-NEXT:    addi sp, sp, 16
 ; RV32ZBA-NEXT:    ret
entry:
   ret i1 %ret
 }
 
 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: umulo.select.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mul a4, a3, a0
 ; RV32-NEXT:    mul a5, a1, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    mulhu a5, a0, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    sltu a4, a4, a5
+; RV32-NEXT:    mulhu a6, a0, a2
+; RV32-NEXT:    add a4, a6, a4
+; RV32-NEXT:    add a4, a4, a5
+; RV32-NEXT:    sltu a4, a4, a6
 ; RV32-NEXT:    snez a5, a3
 ; RV32-NEXT:    snez a6, a1
 ; RV32-NEXT:    and a5, a6, a5
 ; RV32-NEXT:    mulhu a6, a1, a2
 ; RV32-NEXT:    snez a6, a6
-; RV32-NEXT:    or a5, a5, a6
-; RV32-NEXT:    mulhu a6, a3, a0
-; RV32-NEXT:    snez a6, a6
-; RV32-NEXT:    or a5, a5, a6
+; RV32-NEXT:    mulhu a7, a3, a0
+; RV32-NEXT:    snez a7, a7
+; RV32-NEXT:    or a6, a6, a7
+; RV32-NEXT:    or a4, a6, a4
 ; RV32-NEXT:    or a4, a5, a4
 ; RV32-NEXT:    bnez a4, .LBB50_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    mv a1, a3
 ; RV32-NEXT:  .LBB50_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.select.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a2, a0, a1
 ; RV64-NEXT:    bnez a2, .LBB50_2
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:  .LBB50_2: # %entry
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.select.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a4, a3, a0
 ; RV32ZBA-NEXT:    mul a5, a1, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    mulhu a5, a0, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    sltu a4, a4, a5
+; RV32ZBA-NEXT:    mulhu a6, a0, a2
+; RV32ZBA-NEXT:    add a4, a6, a4
+; RV32ZBA-NEXT:    add a4, a4, a5
+; RV32ZBA-NEXT:    sltu a4, a4, a6
 ; RV32ZBA-NEXT:    snez a5, a3
 ; RV32ZBA-NEXT:    snez a6, a1
 ; RV32ZBA-NEXT:    and a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a6, a1, a2
 ; RV32ZBA-NEXT:    snez a6, a6
-; RV32ZBA-NEXT:    or a5, a5, a6
-; RV32ZBA-NEXT:    mulhu a6, a3, a0
-; RV32ZBA-NEXT:    snez a6, a6
-; RV32ZBA-NEXT:    or a5, a5, a6
+; RV32ZBA-NEXT:    mulhu a7, a3, a0
+; RV32ZBA-NEXT:    snez a7, a7
+; RV32ZBA-NEXT:    or a6, a6, a7
+; RV32ZBA-NEXT:    or a4, a6, a4
 ; RV32ZBA-NEXT:    or a4, a5, a4
 ; RV32ZBA-NEXT:    bnez a4, .LBB50_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    mv a0, a2
 ; RV32ZBA-NEXT:    mv a1, a3
 ; RV32ZBA-NEXT:  .LBB50_2: # %entry
 ; RV32ZBA-NEXT:    ret
 ;
entry:
   ret i64 %ret
 }
 
 define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: umulo.not.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mul a4, a3, a0
 ; RV32-NEXT:    mul a5, a1, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    mulhu a5, a0, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    sltu a4, a4, a5
+; RV32-NEXT:    mulhu a6, a0, a2
+; RV32-NEXT:    add a4, a6, a4
+; RV32-NEXT:    add a4, a4, a5
+; RV32-NEXT:    sltu a4, a4, a6
 ; RV32-NEXT:    snez a5, a3
 ; RV32-NEXT:    snez a6, a1
 ; RV32-NEXT:    and a5, a6, a5
 ; RV32-NEXT:    mulhu a1, a1, a2
 ; RV32-NEXT:    snez a1, a1
-; RV32-NEXT:    or a1, a5, a1
 ; RV32-NEXT:    mulhu a0, a3, a0
 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    or a0, a0, a4
+; RV32-NEXT:    or a0, a5, a0
 ; RV32-NEXT:    xori a0, a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.not.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a0, a0, a1
 ; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.not.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a4, a3, a0
 ; RV32ZBA-NEXT:    mul a5, a1, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    mulhu a5, a0, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    sltu a4, a4, a5
+; RV32ZBA-NEXT:    mulhu a6, a0, a2
+; RV32ZBA-NEXT:    add a4, a6, a4
+; RV32ZBA-NEXT:    add a4, a4, a5
+; RV32ZBA-NEXT:    sltu a4, a4, a6
 ; RV32ZBA-NEXT:    snez a5, a3
 ; RV32ZBA-NEXT:    snez a6, a1
 ; RV32ZBA-NEXT:    and a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a1, a1, a2
 ; RV32ZBA-NEXT:    snez a1, a1
-; RV32ZBA-NEXT:    or a1, a5, a1
 ; RV32ZBA-NEXT:    mulhu a0, a3, a0
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    or a0, a0, a4
+; RV32ZBA-NEXT:    or a0, a5, a0
 ; RV32ZBA-NEXT:    xori a0, a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: umulo.not.i64:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    mulhu a0, a0, a1
 ; RV64ZBA-NEXT:    seqz a0, a0
 ; RV64ZBA-NEXT:    ret

 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: saddo.br.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a4, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a0, a4, a0
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    add a0, a1, a0
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
 ; RV32-NEXT:    bgez a0, .LBB53_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret

 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB53_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: saddo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a4, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
-; RV32ZBA-NEXT:    add a0, a4, a0
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    add a0, a1, a0
 ; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
 ; RV32ZBA-NEXT:    not a1, a1
 ; RV32ZBA-NEXT:    and a0, a1, a0
 ; RV32ZBA-NEXT:    bgez a0, .LBB53_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret

 
 continue:
   ret i1 true
 }
 
 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: uaddo.br.i64:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    add a3, a1, a3
 ; RV32-NEXT:    add a2, a0, a2
 ; RV32-NEXT:    sltu a0, a2, a0
 ; RV32-NEXT:    add a2, a3, a0
+; RV32-NEXT:    add a2, a1, a2
 ; RV32-NEXT:    beq a2, a1, .LBB55_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
 ; RV32-NEXT:  .LBB55_2: # %entry
 ; RV32-NEXT:    beqz a0, .LBB55_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret

 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB55_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: uaddo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
-; RV32ZBA-NEXT:    add a3, a1, a3
 ; RV32ZBA-NEXT:    add a2, a0, a2
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
 ; RV32ZBA-NEXT:    add a2, a3, a0
+; RV32ZBA-NEXT:    add a2, a1, a2
 ; RV32ZBA-NEXT:    beq a2, a1, .LBB55_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
 ; RV32ZBA-NEXT:  .LBB55_2: # %entry
 ; RV32ZBA-NEXT:    beqz a0, .LBB55_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret

 continue:
   ret i1 true
 }
 
 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: ssubo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a0, a0, a2
-; RV32-NEXT:    sub a2, a1, a3
-; RV32-NEXT:    sub a2, a2, a0
-; RV32-NEXT:    xor a2, a1, a2
+; RV32-NEXT:    add a0, a3, a0
+; RV32-NEXT:    sub a0, a1, a0
+; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
-; RV32-NEXT:    and a1, a1, a2
-; RV32-NEXT:    bgez a1, .LBB57_2
+; RV32-NEXT:    and a0, a1, a0
+; RV32-NEXT:    bgez a0, .LBB57_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB57_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ssubo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    sgtz a2, a1
 ; RV64-NEXT:    sub a1, a0, a1
 ; RV64-NEXT:    slt a0, a1, a0
 ; RV64-NEXT:    beq a2, a0, .LBB57_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB57_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: ssubo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a0, a2
-; RV32ZBA-NEXT:    sub a2, a1, a3
-; RV32ZBA-NEXT:    sub a2, a2, a0
-; RV32ZBA-NEXT:    xor a2, a1, a2
+; RV32ZBA-NEXT:    add a0, a3, a0
+; RV32ZBA-NEXT:    sub a0, a1, a0
+; RV32ZBA-NEXT:    xor a0, a1, a0
 ; RV32ZBA-NEXT:    xor a1, a1, a3
-; RV32ZBA-NEXT:    and a1, a1, a2
-; RV32ZBA-NEXT:    bgez a1, .LBB57_2
+; RV32ZBA-NEXT:    and a0, a1, a0
+; RV32ZBA-NEXT:    bgez a0, .LBB57_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB57_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: ssubo.br.i64:

 continue:
   ret i1 true
 }
 
 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: usubo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    sltu a4, a0, a2
+; RV32-NEXT:    add a3, a3, a4
 ; RV32-NEXT:    sub a3, a1, a3
-; RV32-NEXT:    sub a3, a3, a4
 ; RV32-NEXT:    beq a3, a1, .LBB59_3
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a1, a3
 ; RV32-NEXT:    bnez a0, .LBB59_4
 ; RV32-NEXT:  .LBB59_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB59_3:

 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB59_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    sltu a4, a0, a2
+; RV32ZBA-NEXT:    add a3, a3, a4
 ; RV32ZBA-NEXT:    sub a3, a1, a3
-; RV32ZBA-NEXT:    sub a3, a3, a4
 ; RV32ZBA-NEXT:    beq a3, a1, .LBB59_3
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a1, a3
 ; RV32ZBA-NEXT:    bnez a0, .LBB59_4
 ; RV32ZBA-NEXT:  .LBB59_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB59_3:

 ; RV32-NEXT:    srai t3, a3, 31
 ; RV32-NEXT:    mul t4, t3, a0
 ; RV32-NEXT:    add t5, t4, t2
 ; RV32-NEXT:    add t6, t0, t5
 ; RV32-NEXT:    sltu s0, t6, t0
 ; RV32-NEXT:    sltu a7, t0, a7
 ; RV32-NEXT:    sltu a5, a6, a5
 ; RV32-NEXT:    mulhu a6, a1, a3
-; RV32-NEXT:    add a5, a6, a5
 ; RV32-NEXT:    add a5, a5, a7
 ; RV32-NEXT:    mulhu a2, a2, t1
-; RV32-NEXT:    add a2, a2, t2
 ; RV32-NEXT:    mul a3, a3, t1
+; RV32-NEXT:    add a3, t2, a3
 ; RV32-NEXT:    add a2, a2, a3
 ; RV32-NEXT:    mul a1, t3, a1
 ; RV32-NEXT:    mulhu a0, t3, a0
-; RV32-NEXT:    add a0, a0, a1
-; RV32-NEXT:    add a0, a0, t4
-; RV32-NEXT:    add a0, a0, a2
-; RV32-NEXT:    sltu a1, t5, t4
+; RV32-NEXT:    add a1, a1, t4
+; RV32-NEXT:    add a1, a1, a2
+; RV32-NEXT:    sltu a2, t5, t4
+; RV32-NEXT:    add a1, a1, a2
 ; RV32-NEXT:    add a0, a0, a1
 ; RV32-NEXT:    add a0, a5, a0
 ; RV32-NEXT:    add a0, a0, s0
+; RV32-NEXT:    add a0, a6, a0
 ; RV32-NEXT:    srai a4, a4, 31
 ; RV32-NEXT:    xor a0, a0, a4
 ; RV32-NEXT:    xor a1, t6, a4
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    beqz a0, .LBB61_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    j .LBB61_3

 ; RV32ZBA-NEXT:    srai t3, a3, 31
 ; RV32ZBA-NEXT:    mul t4, t3, a0
 ; RV32ZBA-NEXT:    add t5, t4, t2
 ; RV32ZBA-NEXT:    add t6, t0, t5
 ; RV32ZBA-NEXT:    sltu s0, t6, t0
 ; RV32ZBA-NEXT:    sltu a7, t0, a7
 ; RV32ZBA-NEXT:    sltu a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a6, a1, a3
-; RV32ZBA-NEXT:    add a5, a6, a5
 ; RV32ZBA-NEXT:    add a5, a5, a7
 ; RV32ZBA-NEXT:    mulhu a2, a2, t1
-; RV32ZBA-NEXT:    add a2, a2, t2
 ; RV32ZBA-NEXT:    mul a3, a3, t1
+; RV32ZBA-NEXT:    add a3, t2, a3
 ; RV32ZBA-NEXT:    add a2, a2, a3
 ; RV32ZBA-NEXT:    mul a1, t3, a1
 ; RV32ZBA-NEXT:    mulhu a0, t3, a0
-; RV32ZBA-NEXT:    add a0, a0, a1
-; RV32ZBA-NEXT:    add a0, a0, t4
-; RV32ZBA-NEXT:    add a0, a0, a2
-; RV32ZBA-NEXT:    sltu a1, t5, t4
+; RV32ZBA-NEXT:    add a1, a1, t4
+; RV32ZBA-NEXT:    add a1, a1, a2
+; RV32ZBA-NEXT:    sltu a2, t5, t4
+; RV32ZBA-NEXT:    add a1, a1, a2
 ; RV32ZBA-NEXT:    add a0, a0, a1
 ; RV32ZBA-NEXT:    add a0, a5, a0
 ; RV32ZBA-NEXT:    add a0, a0, s0
+; RV32ZBA-NEXT:    add a0, a6, a0
 ; RV32ZBA-NEXT:    srai a4, a4, 31
 ; RV32ZBA-NEXT:    xor a0, a0, a4
 ; RV32ZBA-NEXT:    xor a1, t6, a4
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    beqz a0, .LBB61_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    j .LBB61_3

 ; RV32-NEXT:    mul t3, t2, a2
 ; RV32-NEXT:    sub t3, t3, a0
 ; RV32-NEXT:    add t4, t1, t3
 ; RV32-NEXT:    sltu t5, t4, t1
 ; RV32-NEXT:    neg t6, a1
 ; RV32-NEXT:    sltu t1, t1, t6
 ; RV32-NEXT:    sltu a4, a6, a4
 ; RV32-NEXT:    mulhu a6, a1, a7
-; RV32-NEXT:    add a4, a6, a4
 ; RV32-NEXT:    add a4, a4, t1
 ; RV32-NEXT:    sltu a5, t3, a5
 ; RV32-NEXT:    mulh a2, t2, a2
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    sub a0, a0, a2
+; RV32-NEXT:    sub a0, a0, a5
 ; RV32-NEXT:    sub a0, t0, a0
-; RV32-NEXT:    sub a0, a0, a1
-; RV32-NEXT:    add a0, a0, a2
-; RV32-NEXT:    add a0, a0, a5
 ; RV32-NEXT:    add a0, a4, a0
 ; RV32-NEXT:    add a0, a0, t5
+; RV32-NEXT:    add a0, a6, a0
 ; RV32-NEXT:    srai a3, a3, 31
 ; RV32-NEXT:    xor a0, a0, a3
 ; RV32-NEXT:    xor a1, t4, a3
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    beqz a0, .LBB62_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret

 ; RV32ZBA-NEXT:    mul t3, t2, a2
 ; RV32ZBA-NEXT:    sub t3, t3, a0
 ; RV32ZBA-NEXT:    add t4, t1, t3
 ; RV32ZBA-NEXT:    sltu t5, t4, t1
 ; RV32ZBA-NEXT:    neg t6, a1
 ; RV32ZBA-NEXT:    sltu t1, t1, t6
 ; RV32ZBA-NEXT:    sltu a4, a6, a4
 ; RV32ZBA-NEXT:    mulhu a6, a1, a7
-; RV32ZBA-NEXT:    add a4, a6, a4
 ; RV32ZBA-NEXT:    add a4, a4, t1
 ; RV32ZBA-NEXT:    sltu a5, t3, a5
 ; RV32ZBA-NEXT:    mulh a2, t2, a2
+; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    sub a0, a0, a2
+; RV32ZBA-NEXT:    sub a0, a0, a5
 ; RV32ZBA-NEXT:    sub a0, t0, a0
-; RV32ZBA-NEXT:    sub a0, a0, a1
-; RV32ZBA-NEXT:    add a0, a0, a2
-; RV32ZBA-NEXT:    add a0, a0, a5
 ; RV32ZBA-NEXT:    add a0, a4, a0
 ; RV32ZBA-NEXT:    add a0, a0, t5
+; RV32ZBA-NEXT:    add a0, a6, a0
 ; RV32ZBA-NEXT:    srai a3, a3, 31
 ; RV32ZBA-NEXT:    xor a0, a0, a3
 ; RV32ZBA-NEXT:    xor a1, t4, a3
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    beqz a0, .LBB62_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
continue:
   ret i1 true
 }
 
 define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-LABEL: umulo.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    mul a4, a3, a0
 ; RV32-NEXT:    mul a5, a1, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    mulhu a5, a0, a2
-; RV32-NEXT:    add a4, a5, a4
-; RV32-NEXT:    sltu a4, a4, a5
+; RV32-NEXT:    mulhu a6, a0, a2
+; RV32-NEXT:    add a4, a6, a4
+; RV32-NEXT:    add a4, a4, a5
+; RV32-NEXT:    sltu a4, a4, a6
 ; RV32-NEXT:    snez a5, a3
 ; RV32-NEXT:    snez a6, a1
 ; RV32-NEXT:    and a5, a6, a5
 ; RV32-NEXT:    mulhu a1, a1, a2
 ; RV32-NEXT:    snez a1, a1
-; RV32-NEXT:    or a1, a5, a1
 ; RV32-NEXT:    mulhu a0, a3, a0
 ; RV32-NEXT:    snez a0, a0
 ; RV32-NEXT:    or a0, a1, a0
 ; RV32-NEXT:    or a0, a0, a4
+; RV32-NEXT:    or a0, a5, a0
 ; RV32-NEXT:    beqz a0, .LBB64_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB64_2: # %continue
 ; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: umulo.br.i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    mulhu a0, a0, a1
 ; RV64-NEXT:    beqz a0, .LBB64_2
 ; RV64-NEXT:  # %bb.1: # %overflow
 ; RV64-NEXT:    li a0, 0
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB64_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    mul a4, a3, a0
 ; RV32ZBA-NEXT:    mul a5, a1, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    mulhu a5, a0, a2
-; RV32ZBA-NEXT:    add a4, a5, a4
-; RV32ZBA-NEXT:    sltu a4, a4, a5
+; RV32ZBA-NEXT:    mulhu a6, a0, a2
+; RV32ZBA-NEXT:    add a4, a6, a4
+; RV32ZBA-NEXT:    add a4, a4, a5
+; RV32ZBA-NEXT:    sltu a4, a4, a6
 ; RV32ZBA-NEXT:    snez a5, a3
 ; RV32ZBA-NEXT:    snez a6, a1
 ; RV32ZBA-NEXT:    and a5, a6, a5
 ; RV32ZBA-NEXT:    mulhu a1, a1, a2
 ; RV32ZBA-NEXT:    snez a1, a1
-; RV32ZBA-NEXT:    or a1, a5, a1
 ; RV32ZBA-NEXT:    mulhu a0, a3, a0
 ; RV32ZBA-NEXT:    snez a0, a0
 ; RV32ZBA-NEXT:    or a0, a1, a0
 ; RV32ZBA-NEXT:    or a0, a0, a4
+; RV32ZBA-NEXT:    or a0, a5, a0
 ; RV32ZBA-NEXT:    beqz a0, .LBB64_2
 ; RV32ZBA-NEXT:  # %bb.1: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret
 ; RV32ZBA-NEXT:  .LBB64_2: # %continue
 ; RV32ZBA-NEXT:    li a0, 1
 ; RV32ZBA-NEXT:    ret
 ;
continue:
   ret i1 true
 }
 
 define zeroext i1 @umulo2.br.i64(i64 %v1) {
 ; RV32-LABEL: umulo2.br.i64:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    add a2, a0, a0
 ; RV32-NEXT:    sltu a0, a2, a0
-; RV32-NEXT:    add a2, a1, a1
-; RV32-NEXT:    add a2, a2, a0
+; RV32-NEXT:    add a2, a1, a0
+; RV32-NEXT:    add a2, a1, a2
 ; RV32-NEXT:    beq a2, a1, .LBB65_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sltu a0, a2, a1
 ; RV32-NEXT:  .LBB65_2: # %entry
 ; RV32-NEXT:    beqz a0, .LBB65_4
 ; RV32-NEXT:  # %bb.3: # %overflow
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    ret

 ; RV64-NEXT:  .LBB65_2: # %continue
 ; RV64-NEXT:    li a0, 1
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: umulo2.br.i64:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    add a2, a0, a0
 ; RV32ZBA-NEXT:    sltu a0, a2, a0
-; RV32ZBA-NEXT:    add a2, a1, a1
-; RV32ZBA-NEXT:    add a2, a2, a0
+; RV32ZBA-NEXT:    add a2, a1, a0
+; RV32ZBA-NEXT:    add a2, a1, a2
 ; RV32ZBA-NEXT:    beq a2, a1, .LBB65_2
 ; RV32ZBA-NEXT:  # %bb.1: # %entry
 ; RV32ZBA-NEXT:    sltu a0, a2, a1
 ; RV32ZBA-NEXT:  .LBB65_2: # %entry
 ; RV32ZBA-NEXT:    beqz a0, .LBB65_4
 ; RV32ZBA-NEXT:  # %bb.3: # %overflow
 ; RV32ZBA-NEXT:    li a0, 0
 ; RV32ZBA-NEXT:    ret