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[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
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Authored by reames on Dec 14 2022, 7:58 AM.

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Summary

This is a follow up to patch discussion on D139656. As noted there, M2/M4/M8 versions of these instructions don't actually exist, and using them results in overly constrained register allocation.

In that review, we'd talked about moving towards a variant of the instructions which ignored LMUL. I decided to see what happened if we just stopped generating the high LMUL variants, and the results are surprisingly neutral. I only see one minor thing which looks like a real regression among all the churn. I think this is worth doing now to loosen register allocation constraints, and avoid digging our hole around these instructions deeper while thinking about the right model change.

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Event Timeline

reames created this revision.Dec 14 2022, 7:58 AM
reames requested review of this revision.Dec 14 2022, 7:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 14 2022, 7:58 AM
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craig.topper accepted this revision.Dec 14 2022, 10:15 AM

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
2838

Hoist XLenVT above the if to share?

This revision is now accepted and ready to land.Dec 14 2022, 10:15 AM
This revision was landed with ongoing or failed builds.Dec 14 2022, 10:53 AM
This revision was automatically updated to reflect the committed changes.