[lld][ARM] support absolute thunks for Armv4T Thumb and interworking

[stuij]

Summary

changes:

• BLX: The Arm architecture versions that support the branch and link instruction (BLX), can rewrite BLs in place when a state change from Arm<->Thumb is required. Armv4T does not have BLX and so needs thunks for state changes.
• v4T Thumb long branches needed their own thunk. We could have used the v6M implementation, but v6M doesn't have Arm state and must resolve to rather inefficient stack reshuffling. We also can't reuse v7 thumb thunks as they use MOVV/MOVT, which wasn't available yet for v4T.
• Remove the `lack of BLX' warning. LLVM only supports Arm Architecture versions upwards of v4, which we now all support in LLD.
• renamed existing thunks to better reflect their use: ARMV5ABSLongThunk -> ARMV5LongLdrPcThunk, ARMV5PILongThunk -> ARMV4PILongThunk
• removed isCompatibleWith method from ARMV5ABSLongThunk and ARMV5PILongThunk, as they were identical to the ARMThunk parent class implementation.

Support for (efficient) position independent thunks for v4T will be added in a
follow-up patch, including possible related thunk renaming and code comment
cleanup.

[MaskRay]

(On a trip until Dec 15, with limited time using a computer)

add linker support for Armv4(T) absolute relocations

What are the "absolute relocations"? They usually refer to R_ARM_ABS32 and other relocation types that are represented as R_ABS in lld.

"linker" in the subject isn't useful. The directory is all about the linker implementation.

If this is about supporting additional thunks, a more useful subject may be "Support thunks for ..."

Does the support make GBA and NDS programs with mixed A32/T32 code linkable with lld? If yes, that'll be great... I've played many GBA/NDS games in the past...

[stuij]

renamed commit message

[stuij]

In D139888#3991052, @MaskRay wrote:

What are the "absolute relocations"? They usually refer to R_ARM_ABS32 and other relocation types that are represented as R_ABS in lld.

"linker" in the subject isn't useful. The directory is all about the linker implementation.

Thanks. Yes you're right, this is about making R_ARM_CALL and R_ARM_THUMB_CALL work with non-PIC thunks. Previously I actually had "thunks" in the subject and didn't have "linker", but then at the last minute late at night for reasons of bad judgement I guess, I decided to go with relocation and added linker :) I changed the subject to follow your suggestion.

Does the support make GBA and NDS programs with mixed A32/T32 code linkable with lld? If yes, that'll be great... I've played many GBA/NDS games in the past...

Yes, indeed it does :) And inexplicably I didn't even bother to test-drive this code on a GBA program. But now I did and I'm staring at a red screen written by Thumb code called from Arm created by an all-LLVM toolchain :)

[peter.smith]

What are the "absolute relocations"? They usually refer to R_ARM_ABS32 and other relocation types that are represented as R_ABS in lld.

When I added the Thunk support I borrowed terminology from Arm's linker. It uses ABS as short for ABSOLUTE which was its term for Non-PI or position dependent.

Does the support make GBA and NDS programs with mixed A32/T32 code linkable with lld? If yes, that'll be great... I've played many GBA/NDS games in the past...

GBA is v4T so in theory this should make it possible as I think the existing homebrew dev-kits are based on GCC. NDS has a v5T and a v4T, not sure what the development story was for it, whether the software used v4T exclusively or the chips were programmed independently.

A few small comments, but overall looking good to me.

For v4T PI thunks I think the V4 Thumb to Arm is essentially

P:  bx px 
     b #-6
     ldr ip, [pc, #0] ; L2
L1: add pc, pc, ip
L2: .word s - (p + (L1-p) + 8)

The Arm to Thumb looks like it can reuse the existing v5 PI Thunk.

lld/ELF/Thunks.cpp

242

Is this extra new line intentional?

664–665

It looks like the original naming convention for Thunks has broken down a bit. When I first saw the sequence I left a comment that you can't use this for V4 as it can't handle interworking, only saw the ARMLongBXThunk later.

As I understand it the thunk has a code sequence that is V4 ABS (non-interworking), but V5 ABS (interworking). The new v4 ABS Long BX thunk is only needed for V4 interworking.

Although a more significant name change, perhaps:
ARMV4V5LongLdrPcThunk
ARMV4LongBxThunk

Not sure what the capitalisation should be for Ldr and Bx. As instructions they need to be all one case, but this makes it difficult to read the class name.

693

perhaps worth a comment: Arm recommended sequence to follow bx pc. As it looks strange, and in theory anything can be used as it is never executed, but it can make a difference if run on a CPU with speculative execution.

1142

I think it will be worth separating what is not supported, from what is supported inefficiently.
TODO: Support PIC interworking thunks for V4T.
TODO: More efficient PIC non-interworking thunks for V4T.

1144

This would be useful as it looks like there is a potential problem with the existing implementation for V5T and below as it always uses the 16 MiB V6+ Thumb branch range. This puts it at risk of relocation out of range errors if there is more than 4 MiB of code in a single output section.

1153

I think the ARMV5PILongThunk can work for V4T as well here.

P:   ldr ip, [pc, #4] ; L2
L1: add ip, pc, ip
      bx ip
L2: .word S - (P + (L1 - P) + 8)

The entry is Arm state so no BLX required, and the LDR is just loading an offset, the state change is done by the bx ip.

1229–1230

Possible to rerrange to:

if (config->armJ1J2BranchEncoding)
  return addThunkV6M(reloc, s, a);
else if (config->armHasBlx)
  return addThunkArmv5v6(reloc, s, a);
return addThunkArmv4(reloc, s, a);

Should be similar but could be easier to read.

[stuij]

NDS has a v5T and a v4T, not sure what the development story was for it, whether the software used v4T exclusively or the chips were programmed independently.

The official devkit didn't allow programmers to write for the arm7tdmi directly actually. It was mainly used to control hardware and you had to use an API to talk to it from the Arm9 (which is horrible to program for btw, as cost-saving measures meant that you can only run it at full speed when interfacing with TCM and caches). For home-brew devkits of course anything goes and you can program them both. They communicate through an interconnect FIFO. And yes, the most popular home-brew devkit is based on current GCC.

[stuij]

lld/ELF/Thunks.cpp

1144

I have a separate fix for that issue btw.

[stuij]

addressed various review comments

lld/ELF/Thunks.cpp

242

no. removed.

1153

ah right. thanks.

[stuij]

lld/ELF/Thunks.cpp

664–665

As I understand it the thunk has a code sequence that is V4 ABS (non-interworking), but V5 ABS (interworking). The new v4 ABS Long BX thunk is only needed for V4 interworking.

Correct, LDR doesn't do state change for Armv4T.

Regarding naming, V6 also uses the V5 thunks, so the thunk name would become:
ARMV4V5V6LongLdrPcThunk

Similarly for PI thunks that would become:
ARMV4V5V6PILongThunk

I *think* I'm ok with this as it does make the intent clear, but it's not pretty. Thoughts?

[peter.smith]

Thanks for the updates. One more suggestion on the naming, but I've not got a strong opinion.

lld/ELF/Thunks.cpp

664–665

Likely that the best naming scheme means renaming everything, which is not ideal as it will mean updating a lot of tests.

I think the requirement is probably the best so V7 requires Arm V7 etc. This would imply that only ARMV4PILongThunk is needed.

The awkward case is the LongLdrPcThunk as that can be used in Arm state for non-interworking. This would end up with a monstrosity like ARMV5AndNotInterworkingV4LongLdrPcThunk. It is probably less confusing to say ARMV5LongLdrPcThunk with a comment that says can be used for ARMV4T if not interworking.

Probably best err on the side of readable names with the one exception rather than precise but unreadable names.

[stuij]

lld/ELF/Thunks.cpp

664–665

Right, so we're back to minimum arch requirement encoding so to speak. Yes I'd prefer that. And can live with ARMV5LongLdrPcThunk.

So the name changes included in this patch would then be:
ARMV4PILongThunk
ARMV5LongLdrPcThunk
ARMV4ABSLongBxThunk (as there will also be an ARMV4PILongBxThunk in follow-up patch)

[peter.smith]

lld/ELF/Thunks.cpp

664–665

Yes that looks good to me.

[stuij]

change thunk names to agreed upon wording

[stuij]

lld/ELF/Thunks.cpp

664–665

changed the thunk names

[stuij]

edit commit message to reflect thunk renaming

[peter.smith]

Thanks for the updates, I'm happy from the Arm side. Will be worth waiting some time to give MaskRay some time to take a look.

[MaskRay]

lld/ELF/Thunks.cpp

737

delete blank line.

753

756

delete blank line.

777

delete blank line.

795

S - (P + (L1 - P) + 8) can be simplified

1157

ditto below

1232

lld/test/ELF/arm-bl-v4t.s

3

Use split-file %s %t. See some new tests

22

/// for non-RUN non-CHECK comments

lld/test/ELF/arm-bx-v4t.s

60

FAR-LABEL: <target>: (omit addresses so that diagnostics will be better in case of an error)

74

Align (omit addresses so that diagnostics will be better in case of an error))

[MaskRay]

Remove the `lack of BLX' warning. LLVM only supports Arm Architecture versions upwards of v4, which we now all support in LLD.

renamed existing thunks to better reflect their use: ARMV5ABSLongThunk -> ARMV5LongLdrPcThunk, ARMV5PILongThunk -> ARMV4PILongThunk

s/renamed/rename. Just use imperative sentences

We also can't reuse v7 thumb thunks as they use MOVV/MOVT, which wasn't available yet for v4T.

... not supported by v4T.

[stuij]

addressed review comments

[stuij]

lld/ELF/Thunks.cpp

795

This is Peter's comment. I assume he went for descriptive, rather than succinct. He's on vacation for a couple of weeks, but I'll ask him when he gets back.

lld/test/ELF/arm-bl-v4t.s

3

Ah, I like that. Thanks, and thanks for implementing it :) Much cleaner and easier to debug.

lld/test/ELF/arm-bx-v4t.s

60

Thanks, fixed. I took aarch64-thunk-reuse.s as a model for how this should look.

[MaskRay]

Looks great!

lld/ELF/Thunks.cpp

1164

1168

Delete else. Also, when the code is similarly beautiful with a positive or a negative condition, prefer a positive condition.

lld/ELF/Arch/ARM.cpp

bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
   case R_ARM_JUMP24:
     // Source is ARM, all PLT entries are ARM so no interworking required.
     // Otherwise we need to interwork if STT_FUNC Symbol has bit 0 set (Thumb).
     if (s.isFunc() && expr == R_PC && (s.getVA() & 1))
       return true;
     [[fallthrough]];
   case R_ARM_CALL: {
     uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA() : s.getVA();
-    return !inBranchRange(type, branchAddr, dst + a);
+    return !inBranchRange(type, branchAddr, dst + a) ||
+        (!config->armHasBlx && (s.getVA() & 1));
   }
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
     // Source is Thumb, all PLT entries are ARM so interworking is required.
     // Otherwise we need to interwork if STT_FUNC Symbol has bit 0 clear (ARM).
     if (expr == R_PLT_PC || (s.isFunc() && (s.getVA() & 1) == 0))
       return true;
     [[fallthrough]];
   case R_ARM_THM_CALL: {
     uint64_t dst = (expr == R_PLT_PC) ? s.getPltVA() : s.getVA();
-    return !inBranchRange(type, branchAddr, dst + a);
+    return !inBranchRange(type, branchAddr, dst + a) ||
+        (!config->armHasBlx && (s.getVA() & 1) == 0);;
   }
   }
   return false;
 }
 
 uint32_t ARM::getThunkSectionSpacing() const {
   // The placing of pre-created ThunkSections is controlled by the value
   // thunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to

lld/ELF/Driver.cpp

void LinkerDriver::link(opt::InputArgList &args) {
   // For example if an OS can use 4k or 64k page sizes and 4k is more common
   // than 64k then commonPageSize is set to 4k. commonPageSize can be used for
   // optimizations such as DATA_SEGMENT_ALIGN in linker scripts. LLD's use of it
   // is limited to writing trap instructions on the last executable segment.
   config->commonPageSize = getCommonPageSize(args);
 
   config->imageBase = getImageBase(args);
 
-  if (config->emachine == EM_ARM) {
-    // FIXME: These warnings can be removed when lld only uses these features
-    // when the input objects have been compiled with an architecture that
-    // supports them.
-    if (config->armHasBlx == false)
-      warn("lld uses blx instruction, no object with architecture supporting "
-           "feature detected");
-  }
-
   // This adds a .comment section containing a version string.
   if (!config->relocatable)
     ctx.inputSections.push_back(createCommentSection());
 
   // Split SHF_MERGE and .eh_frame sections into pieces in preparation for garbage collection.
   invokeELFT(splitSections);
 
   // Garbage collection and removal of shared symbols from unused shared objects.

lld/ELF/Thunks.cpp

 public:
   ThumbV7PILongThunk(Symbol &dest, int64_t addend) : ThumbThunk(dest, addend) {}
 
   uint32_t sizeLong() override { return 12; }
   void writeLong(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
 };
 
-// Implementations of Thunks for older Arm architectures that do not support
-// the movt/movw instructions. These thunks require at least Architecture v5
-// as used on processors such as the Arm926ej-s. There are no Thumb entry
-// points as there is no Thumb branch instruction on these architecture that
-// can result in a thunk
-class ARMV5ABSLongThunk final : public ARMThunk {
+// Implementations of Thunks for Arm v6-M. Only Thumb instructions are permitted
+class ThumbV6MABSLongThunk final : public ThumbThunk {
+public:
+  ThumbV6MABSLongThunk(Symbol &dest, int64_t addend)
+      : ThumbThunk(dest, addend) {}
+
+  uint32_t sizeLong() override { return 12; }
+  void writeLong(uint8_t *buf) override;
+  void addSymbols(ThunkSection &isec) override;
+};
+
+class ThumbV6MPILongThunk final : public ThumbThunk {
+public:
+  ThumbV6MPILongThunk(Symbol &dest, int64_t addend)
+      : ThumbThunk(dest, addend) {}
+
+  uint32_t sizeLong() override { return 16; }
+  void writeLong(uint8_t *buf) override;
+  void addSymbols(ThunkSection &isec) override;
+};
+
+// Architectures v4, v5 and v6 do not support the movt/movw instructions. v5 and
+// v6 support BLX to which BL instructions can be rewritten inline. There are no
+// Thumb entrypoints for v5 and v6 as there is no Thumb branch instruction on
+// these architecture that can result in a thunk.
+
+// LDR on v5 and v6 can switch processor state, so for v5 and v6,
+// ARMV5LongLdrPcThunk can be used for both Arm->Arm and Arm->Thumb calls. v4
+// can also use this thunk, but only for Arm->Arm calls.
+class ARMV5LongLdrPcThunk final : public ARMThunk {
 public:
-  ARMV5ABSLongThunk(Symbol &dest, int64_t addend) : ARMThunk(dest, addend) {}
+  ARMV5LongLdrPcThunk(Symbol &dest, int64_t addend) : ARMThunk(dest, addend) {}
 
   uint32_t sizeLong() override { return 8; }
   void writeLong(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
-  bool isCompatibleWith(const InputSection &isec,
-                        const Relocation &rel) const override;
 };
 
-class ARMV5PILongThunk final : public ARMThunk {
+class ARMV4PILongThunk final : public ARMThunk {
 public:
-  ARMV5PILongThunk(Symbol &dest, int64_t addend) : ARMThunk(dest, addend) {}
+  ARMV4PILongThunk(Symbol &dest, int64_t addend) : ARMThunk(dest, addend) {}
 
   uint32_t sizeLong() override { return 16; }
   void writeLong(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
-  bool isCompatibleWith(const InputSection &isec,
-                        const Relocation &rel) const override;
 };
 
-// Implementations of Thunks for Arm v6-M. Only Thumb instructions are permitted
-class ThumbV6MABSLongThunk final : public ThumbThunk {
+// Implementations of Thunks for v4. BLX is not supported, and loads
+// will not invoke Arm/Thumb state changes.
+class ARMV4ABSLongBXThunk final : public ARMThunk {
 public:
-  ThumbV6MABSLongThunk(Symbol &dest, int64_t addend)
+  ARMV4ABSLongBXThunk(Symbol &dest, int64_t addend) : ARMThunk(dest, addend) {}
+
+  uint32_t sizeLong() override { return 12; }
+  void writeLong(uint8_t *buf) override;
+  void addSymbols(ThunkSection &isec) override;
+};
+
+class ThumbV4ABSLongBXThunk final : public ThumbThunk {
+public:
+  ThumbV4ABSLongBXThunk(Symbol &dest, int64_t addend)
       : ThumbThunk(dest, addend) {}
 
   uint32_t sizeLong() override { return 12; }
   void writeLong(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
 };
 
-class ThumbV6MPILongThunk final : public ThumbThunk {
+class ThumbV4ABSLongThunk final : public ThumbThunk {
 public:
-  ThumbV6MPILongThunk(Symbol &dest, int64_t addend)
+  ThumbV4ABSLongThunk(Symbol &dest, int64_t addend)
       : ThumbThunk(dest, addend) {}
 
   uint32_t sizeLong() override { return 16; }
   void writeLong(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
 };
 
 // MIPS LA25 thunk
 class MipsThunk final : public Thunk {
 public:
   MipsThunk(Symbol &dest) : Thunk(dest, 0) {}
 
   uint32_t size() override { return 16; }
   void writeTo(uint8_t *buf) override;
   void addSymbols(ThunkSection &isec) override;
   InputSection *getTargetInputSection() const override;
const uint8_t data[] = {
     0x00, 0x00, 0x00, 0xea, // b S
   };
   memcpy(buf, data, sizeof(data));
   target->relocateNoSym(buf, R_ARM_JUMP24, offset);
 }
 
 bool ARMThunk::isCompatibleWith(const InputSection &isec,
                                 const Relocation &rel) const {
+  // v4T does not have BLX, so also deny R_ARM_THM_CALL
+  if (!config->armHasBlx && rel.type == R_ARM_THM_CALL)
+    return false;
+
   // Thumb branch relocations can't use BLX
   return rel.type != R_ARM_THM_JUMP19 && rel.type != R_ARM_THM_JUMP24;
 }
 
 // This function returns true if the target is Thumb and is within 2^25, and
 // it has not previously returned false (see comment for mayUseShortThunk).
 bool ThumbThunk::getMayUseShortThunk() {
   if (!mayUseShortThunk)
const uint8_t data[] = {
       0x00, 0xf0, 0x00, 0xb0, // b.w S
   };
   memcpy(buf, data, sizeof(data));
   target->relocateNoSym(buf, R_ARM_THM_JUMP24, offset);
 }
 
 bool ThumbThunk::isCompatibleWith(const InputSection &isec,
                                   const Relocation &rel) const {
+  // v4T does not have BLX, so also deny R_ARM_CALL
+  if (!config->armHasBlx && rel.type == R_ARM_CALL)
+    return false;
+
   // ARM branch relocations can't use BLX
   return rel.type != R_ARM_JUMP24 && rel.type != R_ARM_PC24 && rel.type != R_ARM_PLT32;
 }
 
 void ARMV7ABSLongThunk::writeLong(uint8_t *buf) {
   const uint8_t data[] = {
       0x00, 0xc0, 0x00, 0xe3, // movw         ip,:lower16:S
       0x00, 0xc0, 0x40, 0xe3, // movt         ip,:upper16:S
void ThumbV7PILongThunk::writeLong(uint8_t *buf) {
   target->relocateNoSym(buf + 4, R_ARM_THM_MOVT_PREL, offset);
 }
 
 void ThumbV7PILongThunk::addSymbols(ThunkSection &isec) {
   addSymbol(saver().save("__ThumbV7PILongThunk_" + destination.getName()),
             STT_FUNC, 1, isec);
   addSymbol("$t", STT_NOTYPE, 0, isec);
 }
 
-void ARMV5ABSLongThunk::writeLong(uint8_t *buf) {
-  const uint8_t data[] = {
-      0x04, 0xf0, 0x1f, 0xe5, //     ldr pc, [pc,#-4] ; L1
-      0x00, 0x00, 0x00, 0x00, // L1: .word S
-  };
-  memcpy(buf, data, sizeof(data));
-  target->relocateNoSym(buf + 4, R_ARM_ABS32, getARMThunkDestVA(destination));
-}
-
-void ARMV5ABSLongThunk::addSymbols(ThunkSection &isec) {
-  addSymbol(saver().save("__ARMv5ABSLongThunk_" + destination.getName()),
-            STT_FUNC, 0, isec);
-  addSymbol("$a", STT_NOTYPE, 0, isec);
-  addSymbol("$d", STT_NOTYPE, 4, isec);
-}
-
-bool ARMV5ABSLongThunk::isCompatibleWith(const InputSection &isec,
-                                         const Relocation &rel) const {
-  // Thumb branch relocations can't use BLX
-  return rel.type != R_ARM_THM_JUMP19 && rel.type != R_ARM_THM_JUMP24;
-}
-
-void ARMV5PILongThunk::writeLong(uint8_t *buf) {
-  const uint8_t data[] = {
-      0x04, 0xc0, 0x9f, 0xe5, // P:  ldr ip, [pc,#4] ; L2
-      0x0c, 0xc0, 0x8f, 0xe0, // L1: add ip, pc, ip
-      0x1c, 0xff, 0x2f, 0xe1, //     bx ip
-      0x00, 0x00, 0x00, 0x00, // L2: .word S - (P + (L1 - P) + 8)
-  };
-  uint64_t s = getARMThunkDestVA(destination);
-  uint64_t p = getThunkTargetSym()->getVA() & ~0x1;
-  memcpy(buf, data, sizeof(data));
-  target->relocateNoSym(buf + 12, R_ARM_REL32, s - p - 12);
-}
-
-void ARMV5PILongThunk::addSymbols(ThunkSection &isec) {
-  addSymbol(saver().save("__ARMV5PILongThunk_" + destination.getName()),
-            STT_FUNC, 0, isec);
-  addSymbol("$a", STT_NOTYPE, 0, isec);
-  addSymbol("$d", STT_NOTYPE, 12, isec);
-}
-
-bool ARMV5PILongThunk::isCompatibleWith(const InputSection &isec,
-                                        const Relocation &rel) const {
-  // Thumb branch relocations can't use BLX
-  return rel.type != R_ARM_THM_JUMP19 && rel.type != R_ARM_THM_JUMP24;
-}
-
 void ThumbV6MABSLongThunk::writeLong(uint8_t *buf) {
   // Most Thumb instructions cannot access the high registers r8 - r15. As the
   // only register we can corrupt is r12 we must instead spill a low register
   // to the stack to use as a scratch register. We push r1 even though we
   // don't need to get some space to use for the return address.
   const uint8_t data[] = {
       0x03, 0xb4,            // push {r0, r1} ; Obtain scratch registers
       0x01, 0x48,            // ldr r0, [pc, #4] ; L1
       0x01, 0x90,            // str r0, [sp, #4] ; SP + 4 = S
void ThumbV6MABSLongThunk::addSymbols(ThunkSection &isec) {
   addSymbol("$t", STT_NOTYPE, 0, isec);
   addSymbol("$d", STT_NOTYPE, 8, isec);
 }
 
 void ThumbV6MPILongThunk::writeLong(uint8_t *buf) {
   // Most Thumb instructions cannot access the high registers r8 - r15. As the
   // only register we can corrupt is ip (r12) we must instead spill a low
   // register to the stack to use as a scratch register.
   const uint8_t data[] = {
       0x01, 0xb4,             // P:  push {r0}        ; Obtain scratch register
       0x02, 0x48,             //     ldr r0, [pc, #8] ; L2
       0x84, 0x46,             //     mov ip, r0       ; high to low register
       0x01, 0xbc,             //     pop {r0}         ; restore scratch register
       0xe7, 0x44,             // L1: add pc, ip       ; transfer control
       0xc0, 0x46,             //     nop              ; pad to 4-byte boundary
       0x00, 0x00, 0x00, 0x00, // L2: .word S - (P + (L1 - P) + 4)
   };
   uint64_t s = getARMThunkDestVA(destination);
   uint64_t p = getThunkTargetSym()->getVA() & ~0x1;
   memcpy(buf, data, sizeof(data));
   target->relocateNoSym(buf + 12, R_ARM_REL32, s - p - 12);
 }
 
 void ThumbV6MPILongThunk::addSymbols(ThunkSection &isec) {
   addSymbol(saver().save("__Thumbv6MPILongThunk_" + destination.getName()),
             STT_FUNC, 1, isec);
   addSymbol("$t", STT_NOTYPE, 0, isec);
   addSymbol("$d", STT_NOTYPE, 12, isec);
 }
 
+void ARMV5LongLdrPcThunk::writeLong(uint8_t *buf) {
+  const uint8_t data[] = {
+      0x04, 0xf0, 0x1f, 0xe5, // ldr pc, [pc,#-4] ; L1
+      0x00, 0x00, 0x00, 0x00, // L1: .word S
+  };
+  memcpy(buf, data, sizeof(data));
+  target->relocateNoSym(buf + 4, R_ARM_ABS32, getARMThunkDestVA(destination));
+}
+
+void ARMV5LongLdrPcThunk::addSymbols(ThunkSection &isec) {
+  addSymbol(saver().save("__ARMv5LongLdrPcThunk_" + destination.getName()),
+            STT_FUNC, 0, isec);
+  addSymbol("$a", STT_NOTYPE, 0, isec);
+  addSymbol("$d", STT_NOTYPE, 4, isec);
+}
+
+void ARMV4ABSLongBXThunk::writeLong(uint8_t *buf) {
+  const uint8_t data[] = {
+      0x00, 0xc0, 0x9f, 0xe5, // ldr r12, [pc] ; L1
+      0x1c, 0xff, 0x2f, 0xe1, // bx r12
+      0x00, 0x00, 0x00, 0x00, // L1: .word S
+  };
+  memcpy(buf, data, sizeof(data));
+  target->relocateNoSym(buf + 8, R_ARM_ABS32, getARMThunkDestVA(destination));
+}
+
+void ARMV4ABSLongBXThunk::addSymbols(ThunkSection &isec) {
+  addSymbol(saver().save("__ARMv4ABSLongBXThunk_" + destination.getName()),
+            STT_FUNC, 0, isec);
+  addSymbol("$a", STT_NOTYPE, 0, isec);
+  addSymbol("$d", STT_NOTYPE, 8, isec);
+}
+
+void ThumbV4ABSLongBXThunk::writeLong(uint8_t *buf) {
+  const uint8_t data[] = {
+      0x78, 0x47,             // bx pc
+      0xfd, 0xe7,             // b #-6 ; Arm recommended sequence to follow bx pc
+      0x04, 0xf0, 0x1f, 0xe5, // ldr pc, [pc, #-4] ; L1
+      0x00, 0x00, 0x00, 0x00, // L1: .word S
+  };
+  memcpy(buf, data, sizeof(data));
+  target->relocateNoSym(buf + 8, R_ARM_ABS32, getARMThunkDestVA(destination));
+}
+
+void ThumbV4ABSLongBXThunk::addSymbols(ThunkSection &isec) {
+  addSymbol(saver().save("__Thumbv4ABSLongBXThunk_" + destination.getName()),
+            STT_FUNC, 1, isec);
+  addSymbol("$t", STT_NOTYPE, 0, isec);
+  addSymbol("$a", STT_NOTYPE, 4, isec);
+  addSymbol("$d", STT_NOTYPE, 8, isec);
+}
+
+void ThumbV4ABSLongThunk::writeLong(uint8_t *buf) {
+  const uint8_t data[] = {
+      0x78, 0x47,             // bx pc
+      0xfd, 0xe7,             // b #-6 ; Arm recommended sequence to follow bx pc
+      0x00, 0xc0, 0x9f, 0xe5, // ldr r12, [pc] ; L1
+      0x1c, 0xff, 0x2f, 0xe1, // bx r12
+      0x00, 0x00, 0x00, 0x00, // L1: .word S
+  };
+  memcpy(buf, data, sizeof(data));
+  target->relocateNoSym(buf + 12, R_ARM_ABS32, getARMThunkDestVA(destination));
+}
+
+void ThumbV4ABSLongThunk::addSymbols(ThunkSection &isec) {
+  addSymbol(saver().save("__Thumbv4ABSLongThunk_" + destination.getName()),
+            STT_FUNC, 1, isec);
+  addSymbol("$t", STT_NOTYPE, 0, isec);
+  addSymbol("$a", STT_NOTYPE, 4, isec);
+  addSymbol("$d", STT_NOTYPE, 12, isec);
+}
+
+void ARMV4PILongThunk::writeLong(uint8_t *buf) {
+  const uint8_t data[] = {
+      0x04, 0xc0, 0x9f, 0xe5, // P:  ldr ip, [pc,#4] ; L2
+      0x0c, 0xc0, 0x8f, 0xe0, // L1: add ip, pc, ip
+      0x1c, 0xff, 0x2f, 0xe1, //     bx ip
+      0x00, 0x00, 0x00, 0x00, // L2: .word S - (P + (L1 - P) + 8)
+  };
+  uint64_t s = getARMThunkDestVA(destination);
+  uint64_t p = getThunkTargetSym()->getVA() & ~0x1;
+  memcpy(buf, data, sizeof(data));
+  target->relocateNoSym(buf + 12, R_ARM_REL32, s - p - 12);
+}
+
+void ARMV4PILongThunk::addSymbols(ThunkSection &isec) {
+  addSymbol(saver().save("__ARMv4PILongThunk_" + destination.getName()),
+            STT_FUNC, 0, isec);
+  addSymbol("$a", STT_NOTYPE, 0, isec);
+  addSymbol("$d", STT_NOTYPE, 12, isec);
+}
+
 // Write MIPS LA25 thunk code to call PIC function from the non-PIC one.
 void MipsThunk::writeTo(uint8_t *buf) {
   uint64_t s = destination.getVA();
   write32(buf, 0x3c190000); // lui   $25, %hi(func)
   write32(buf + 4, 0x08000000 | (s >> 2)); // j     func
   write32(buf + 8, 0x27390000); // addiu $25, $25, %lo(func)
   write32(buf + 12, 0x00000000); // nop
   target->relocateNoSym(buf, R_MIPS_HI16, s);
static Thunk *addThunkAArch64(RelType type, Symbol &s, int64_t a) {
   if (type != R_AARCH64_CALL26 && type != R_AARCH64_JUMP26 &&
       type != R_AARCH64_PLT32)
     fatal("unrecognized relocation type");
   if (config->picThunk)
     return make<AArch64ADRPThunk>(s, a);
   return make<AArch64ABSLongThunk>(s, a);
 }
 
-// Creates a thunk for Thumb-ARM interworking.
-// Arm Architectures v5 and v6 do not support Thumb2 technology. This means
+// Creates a thunk for long branches or Thumb-ARM interworking.
+// Arm Architectures v4t does not support Thumb2 technology, and does not
+// support BLX or LDR Arm/Thumb state switching. This means that
+// - MOVT and MOVW instructions cannot be used.
+// - We can't rewrite BL in place to BLX. We will need thunks.
+//
+// TODO: Support PIC interworking thunks for V4T.
+// TODO: More efficient PIC non-interworking thunks for V4T.
+// TODO: use B for short Thumb->Arm thunks instead of LDR (this doesn't work for
+//       Arm->Thumb, as in Arm state no BX PC trick; it doesn't switch state).
+static Thunk *addThunkArmv4(RelType reloc, Symbol &s, int64_t a) {
+  bool thumb_target = s.getVA(a) & 1;
+
+  switch (reloc) {
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_JUMP24:
+  case R_ARM_CALL:
+    if (config->picThunk)
+      // can be used for both Arm->Arm and Arm->Thumb
+      return make<ARMV4PILongThunk>(s, a);
+    if (thumb_target)
+      return make<ARMV4ABSLongBXThunk>(s, a);
+    return make<ARMV5LongLdrPcThunk>(s, a);
+  case R_ARM_THM_CALL:
+    if (config->picThunk && !thumb_target)
+      fatal("PIC relocations across state change not supported for Armv4T");
+    if (config->picThunk && thumb_target)
+      return make<ThumbV6MPILongThunk>(s, a);
+    if (thumb_target)
+      return make<ThumbV4ABSLongThunk>(s, a);
+    return make<ThumbV4ABSLongBXThunk>(s, a);
+  }
+  fatal("relocation " + toString(reloc) + " to " + toString(s) +
+        " not supported for Armv4 or Armv4T target");
+}
+
+// Creates a thunk for Thumb-ARM interworking compatible with Armv5 and Armv6.
+// Arm Architectures v5 and v6 do not support Thumb2 technology. This means that
 // - MOVT and MOVW instructions cannot be used
 // - Only Thumb relocation that can generate a Thunk is a BL, this can always
 //   be transformed into a BLX
-static Thunk *addThunkPreArmv7(RelType reloc, Symbol &s, int64_t a) {
+static Thunk *addThunkArmv5v6(RelType reloc, Symbol &s, int64_t a) {
   switch (reloc) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
   case R_ARM_CALL:
   case R_ARM_THM_CALL:
     if (config->picThunk)
-      return make<ARMV5PILongThunk>(s, a);
-    return make<ARMV5ABSLongThunk>(s, a);
+      return make<ARMV4PILongThunk>(s, a);
+    return make<ARMV5LongLdrPcThunk>(s, a);
   }
   fatal("relocation " + toString(reloc) + " to " + toString(s) +
         " not supported for Armv5 or Armv6 targets");
 }
 
 // Create a thunk for Thumb long branch on V6-M.
 // Arm Architecture v6-M only supports Thumb instructions. This means
 // - MOVT and MOVW instructions cannot be used.
static Thunk *addThunkArm(RelType reloc, Symbol &s, int64_t a) {
   // - Branch and link relocations can change state, can select Thunks from
   //   either Arm or Thumb.
   // Position independent Thunks if we require position independent code.
 
   // Handle architectures that have restrictions on the instructions that they
   // can use in Thunks. The flags below are set by reading the BuildAttributes
   // of the input objects. InputFiles.cpp contains the mapping from ARM
   // architecture to flag.
   if (!config->armHasMovtMovw) {
-    if (!config->armJ1J2BranchEncoding)
-      return addThunkPreArmv7(reloc, s, a);
+    if (config->armJ1J2BranchEncoding)
       return addThunkV6M(reloc, s, a);
+    if (config->armHasBlx)
+      return addThunkArmv5v6(reloc, s, a);
+    return addThunkArmv4(reloc, s, a);
   }
 
   switch (reloc) {
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_JUMP24:
   case R_ARM_CALL:
     if (config->picThunk)

lld/test/ELF/arm-bl-v4t.s

+// REQUIRES: arm
+// RUN: rm -rf %t && split-file %s %t
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv4t-none-linux-gnueabi %t/a.s -o %t/a.o
+// RUN: ld.lld %t/a.o --script %t/far.lds -o %t/a-far
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-far | FileCheck %s --check-prefixes=FAR
+// RUN: ld.lld %t/a.o --script %t/near.lds -o %t/a-near
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-near | FileCheck %s --check-prefixes=NEAR
+
+/// On Armv4T there is no blx instruction so long branch/exchange looks slightly
+/// different.
+
+#--- a.s
+ .text
+ .syntax unified
+ .cpu    arm7tdmi
+
+ .section .low, "ax", %progbits
+ .arm
+ .globl _start
+ .type   _start,%function
+ .p2align       2
+_start:
+  bl target
+  bx lr
+
+ .thumb
+ .globl thumb_start
+ .type  thumb_start,%function
+ .p2align       2
+thumb_start:
+  bl thumb_target
+  bx lr
+
+// FAR-LABEL: <_start>:
+// FAR-NEXT:   1000000:       bl  0x1000010 <__ARMv5LongLdrPcThunk_target> @ imm = #8
+// FAR-NEXT:                  bx  lr
+// FAR-EMPTY:
+// FAR-LABEL: <thumb_start>:
+// FAR-NEXT:   1000008:       bl  0x1000018 <__Thumbv4ABSLongThunk_thumb_target> @ imm = #12
+// FAR-NEXT:                  bx  lr
+// FAR-NEXT:                  bmi 0xffffba                @ imm = #-88
+// FAR-EMPTY:
+// FAR-NEXT:  <__ARMv5LongLdrPcThunk_target>:
+// FAR-NEXT:   1000010:       ldr pc, [pc, #-4]           @ 0x1000014 <__ARMv5LongLdrPcThunk_target+0x4>
+// FAR-EMPTY: 
+// FAR-NEXT:  <$d>:
+// FAR-NEXT:   1000014: 00 00 00 06   .word 0x06000000
+// FAR-EMPTY:
+// FAR-NEXT:  <__Thumbv4ABSLongThunk_thumb_target>:
+// FAR-NEXT:   1000018:       bx  pc
+// FAR-NEXT:                  b 0x1000018 <__Thumbv4ABSLongThunk_thumb_target> @ imm = #-6
+// FAR-EMPTY:
+// FAR-NEXT:  <$a>:
+// FAR-NEXT:   100001c:       ldr r12, [pc]               @ 0x1000024 <__Thumbv4ABSLongThunk_thumb_target+0xc>
+// FAR-NEXT:                  bx  r12
+// FAR-EMPTY:
+// FAR-NEXT:  <$d>:
+// FAR-NEXT:   1000024: 05 00 00 06   .word 0x06000005
+
+// NEAR-LABEL: <_start>:
+// NEAR-NEXT:  1000000:       bl  0x100000c <thumb_start+0x4> @ imm = #4
+// NEAR-NEXT:                 bx  lr
+// NEAR-EMPTY:
+// NEAR-LABEL: <thumb_start>:
+// NEAR-NEXT:  1000008:       bl  0x1000012 <thumb_target> @ imm = #6
+// NEAR-NEXT:                 bx  lr
+
+.section .high, "ax", %progbits
+ .arm
+ .globl target
+ .type target,%function
+target:
+  bx lr
+
+.thumb
+ .globl thumb_target
+ .type thumb_target,%function
+thumb_target:
+  bx lr
+
+// FAR-LABEL: <target>:
+// FAR-NEXT:   6000000:       bx  lr
+// FAR-EMPTY:
+// FAR-LABEL: <thumb_target>:
+// FAR-NEXT:   6000004:       bx  lr
+
+// NEAR-LABEL: <target>:
+// NEAR-LABEL:  100000e:        bx  lr
+// NEAR-EMPTY:
+// NEAR-NEXT: <thumb_target>:
+// NEAR-NEXT:  1000012:       bx  lr
+
+                                     
+#--- far.lds
+SECTIONS {
+  . = SIZEOF_HEADERS;
+  .low 0x01000000 : { *(.low) }
+  .high 0x06000000 : { *(.high) }
+}
+
+#--- near.lds
+SECTIONS {
+  . = SIZEOF_HEADERS;
+  .all 0x01000000 : { *(.low) *(.high) }
+}

lld/test/ELF/arm-bl-v6.s

  .thumb
  .section .text.2, "ax", %progbits
  .globl thumbfunc
  .type thumbfunc,%function
 thumbfunc:
  bl farthumbfunc
 
 // CHECK-THUMB1: <thumbfunc>:
-// CHECK-THUMB1-NEXT:    21008: f200 e800     blx 0x22100c <__ARMv5ABSLongThunk_farthumbfunc>
+// CHECK-THUMB1-NEXT:    21008: f200 e800     blx 0x22100c <__ARMv5LongLdrPcThunk_farthumbfunc>
 /// 6 Megabytes, enough to make farthumbfunc out of range of caller
 /// on a v6 Arm, but not on a v7 Arm.
 
  .section .text.3, "ax", %progbits
  .space 0x200000
-// CHECK-ARM2: <__ARMv5ABSLongThunk_farthumbfunc>:
+// CHECK-ARM2: <__ARMv5LongLdrPcThunk_farthumbfunc>:
 // CHECK-ARM2-NEXT:   22100c:   e51ff004        ldr     pc, [pc, #-4]
 // CHECK-ARM2: <$d>:
 // CHECK-ARM2-NEXT:   221010:   01 20 62 00     .word   0x00622001
  .section .text.4, "ax", %progbits
  .space 0x200000
 
  .section .text.5, "ax", %progbits
  .space 0x200000

lld/test/ELF/arm-blx-v4t.s

-// REQUIRES: arm
-// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=arm-none-linux-gnueabi %s -o %t
-// RUN: ld.lld %t -o /dev/null 2>&1 | FileCheck %s
-
-// On Arm v4t there is no blx instruction so all interworking must go via
-// a thunk. At present we don't support v4t so we give a warning for unsupported
-// features.
-
-// CHECK: warning: lld uses blx instruction, no object with architecture supporting feature detected
-
- .text
- .syntax unified
- .cpu   arm7tdmi
- .arm
- .globl _start
- .type   _start,%function
- .p2align       2
-_start:
-  bl thumbfunc
-  bx lr
-
- .thumb
- .section .text.2, "ax", %progbits
- .globl thumbfunc
- .type thumbfunc,%function
-thumbfunc:
- bx lr

lld/test/ELF/arm-blx.s

 // REQUIRES: arm
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
-// RUN: llvm-mc -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-thumb-abs.s -o %tfar
 // RUN: echo "SECTIONS { \
 // RUN:          . = 0xb4; \
 // RUN:          .callee1 : { *(.callee_low) } \
 // RUN:          .callee2 : { *(.callee_arm_low) } \
 // RUN:          .caller : { *(.text) } \
 // RUN:          .callee3 : { *(.callee_high) } \
 // RUN:          .callee4 : { *(.callee_arm_high) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %tfar -o %t2

lld/test/ELF/arm-bx-v4t.s

+// REQUIRES: arm
+// RUN: rm -rf %t && split-file %s %t
+// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv4t-none-linux-gnueabi %t/a.s -o %t/a.o
+// RUN: ld.lld %t/a.o --script %t/far.lds -o %t/a-far
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-far | FileCheck %s --check-prefixes=FAR
+// RUN: ld.lld %t/a.o --script %t/near.lds -o %t/a-near
+// RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn --triple=armv4t-none-linux-gnueabi %t/a-near | FileCheck %s --check-prefixes=NEAR
+
+/// On Arm v4t there is no blx instruction so all interworking must go via
+/// a thunk.
+
+#--- a.s
+ .text
+ .syntax unified
+ .cpu    arm7tdmi
+
+ .section .low, "ax", %progbits
+ .arm
+ .globl _start
+ .type   _start,%function
+ .p2align       2
+_start:
+  bl target
+  bx lr
+
+// FAR-LABEL: <_start>:
+// FAR-NEXT:   1000000:       bl      0x1000008 <__ARMv4ABSLongBXThunk_target> @ imm = #0
+// FAR-NEXT:                  bx      lr
+// FAR-EMPTY:
+// FAR-NEXT:  <__ARMv4ABSLongBXThunk_target>:
+// FAR-NEXT:   1000008:       ldr     r12, [pc]               @ 0x1000010 <__ARMv4ABSLongBXThunk_target+0x8>
+// FAR-NEXT:                  bx      r12
+// FAR-EMPTY:
+// FAR-NEXT:  <$d>:
+// FAR-NEXT:   1000010: 01 00 00 06   .word   0x06000001
+
+// NEAR-LABEL: <_start>:
+// NEAR-NEXT:   1000000:       bl      0x1000008 <__ARMv4ABSLongBXThunk_target> @ imm = #0
+// NEAR-NEXT:                  bx      lr
+// NEAR-EMPTY:
+// NEAR-NEXT:  <__ARMv4ABSLongBXThunk_target>:
+// NEAR-NEXT:   1000008:       ldr     r12, [pc]               @ 0x1000010 <__ARMv4ABSLongBXThunk_target+0x8>
+// NEAR-NEXT:                  bx      r12
+// NEAR-EMPTY:
+// NEAR-NEXT:  <$d>:
+// NEAR-NEXT:  1000010: 15 00 00 01   .word   0x01000015
+
+
+.section .high, "ax", %progbits
+.thumb
+ .globl target
+ .type target,%function
+target:
+  bl _start
+  bx lr
+
+// FAR-LABEL: <target>:
+// FAR-NEXT:   6000000:       bl      0x6000008 <__Thumbv4ABSLongBXThunk__start> @ imm = #4
+// FAR-NEXT:                  bx      lr
+// FAR-NEXT:                  bmi     0x5ffffb2 <__ARMv4ABSLongBXThunk_target+0x4ffffaa> @ imm = #-88
+// FAR-EMPTY:
+// FAR-NEXT:  <__Thumbv4ABSLongBXThunk__start>:
+// FAR-NEXT:   6000008:       bx      pc
+// FAR-NEXT:                  b       0x6000008 <__Thumbv4ABSLongBXThunk__start> @ imm = #-6
+// FAR-EMPTY:
+// FAR-NEXT:  <$a>:
+// FAR-NEXT:   600000c:       ldr     pc, [pc, #-4]           @ 0x6000010 <__Thumbv4ABSLongBXThunk__start+0x8>
+// FAR-EMPTY:
+// FAR-NEXT: <$d>:
+// FAR-NEXT:  6000010: 00 00 00 01   .word   0x01000000
+
+// NEAR-LABEL: <target>:
+// NEAR-NEXT:   1000014:       bl      0x100001c <__Thumbv4ABSLongBXThunk__start> @ imm = #4
+// NEAR-NEXT:   1000018:       bx      lr
+// NEAR-NEXT:   100001a:       bmi     0xffffc6                @ imm = #-88
+// NEAR-EMPTY:
+// NEAR-NEXT:  <__Thumbv4ABSLongBXThunk__start>:
+// NEAR-NEXT:   100001c:       bx      pc
+// NEAR-NEXT:   100001e:       b       0x100001c <__Thumbv4ABSLongBXThunk__start> @ imm = #-6
+// NEAR-EMPTY:
+// NEAR-NEXT:  <$a>:
+// NEAR-NEXT:   1000020:       ldr     pc, [pc, #-4]           @ 0x1000024 <__Thumbv4ABSLongBXThunk__start+0x8>
+// NEAR-EMPTY:
+// NEAR-NEXT:  <$d>:
+// NEAR-NEXT:   1000024: 00 00 00 01   .word   0x01000000
+
+#--- far.lds
+SECTIONS {
+  . = SIZEOF_HEADERS;
+  .low 0x01000000 : { *(.low) }
+  .high 0x06000000 : { *(.high) }
+}
+
+#--- near.lds
+SECTIONS {
+  . = SIZEOF_HEADERS;
+  .all 0x01000000 : { *(.low) *(.high) }
+}

lld/test/ELF/arm-thumb-interwork-thunk-v5.s

// support for the blx instruction for Thumb BL and BLX to an Arm symbol.
         .balign 0x1000
 _start:
         b thumb_func
         bl thumb_func
         blx thumb_func
         bx lr
 
 // CHECK: <_start>:
-// CHECK-NEXT: 21000: ea000003        b       0x21014 <__ARMv5ABSLongThunk_thumb_func>
+// CHECK-NEXT: 21000: ea000003        b       0x21014 <__ARMv5LongLdrPcThunk_thumb_func>
 // CHECK-NEXT: 21004: fa000001        blx     0x21010 <thumb_func>
 // CHECK-NEXT: 21008: fa000000        blx     0x21010 <thumb_func>
 // CHECK-NEXT: 2100c: e12fff1e        bx      lr
 
 // CHECK: <thumb_func>:
 // CHECK-NEXT: 21010: 4770    bx      lr
 
-// CHECK: <__ARMv5ABSLongThunk_thumb_func>:
+// CHECK: <__ARMv5LongLdrPcThunk_thumb_func>:
 // CHECK-NEXT: 21014: e51ff004        ldr     pc, [pc, #-4]
 // CHECK: <$d>:
 // CHECK-NEXT: 21018: 11 10 02 00     .word   0x00021011
 
 // CHECK-PI: <_start>:
-// CHECK-PI-NEXT: 11000: ea000003        b       0x11014 <__ARMV5PILongThunk_thumb_func>
+// CHECK-PI-NEXT: 11000: ea000003        b       0x11014 <__ARMv4PILongThunk_thumb_func>
 // CHECK-PI-NEXT: 11004: fa000001        blx     0x11010 <thumb_func>
 // CHECK-PI-NEXT: 11008: fa000000        blx     0x11010 <thumb_func>
 // CHECK-PI-NEXT: 1100c: e12fff1e        bx      lr
 
 // CHECK-PI: <thumb_func>:
 // CHECK-PI-NEXT: 11010: 4770    bx      lr
 
-// CHECK-PI: <__ARMV5PILongThunk_thumb_func>:
+// CHECK-PI: <__ARMv4PILongThunk_thumb_func>:
 // CHECK-PI-NEXT: 11014: e59fc004        ldr     r12, [pc, #4]
 // CHECK-PI-NEXT: 11018: e08fc00c        add     r12, pc, r12
 // CHECK-PI-NEXT: 1101c: e12fff1c        bx      r12
 // CHECK-PI: <$d>:
 // CHECK-PI-NEXT: 11020: f1 ff ff ff     .word   0xfffffff1
 
         .section .text.1, "ax", %progbits
         .thumb
         .hidden thumb_func
         .type thumb_func, %function
 thumb_func:
         bx lr

lld/test/ELF/arm-thunk-multipass-plt.s

needsplt:
         .space (1024 * 1024)
 
         .section .text.06, "ax", %progbits
         .space (1024 * 1024)
 
         .section .text.07, "ax", %progbits
         .space (1024 * 1024)
 /// 0xd00040 = preemptible@plt
-// CHECK:      0070000c <__ARMV5PILongThunk_preemptible>:
+// CHECK:      0070000c <__ARMv4PILongThunk_preemptible>:
 // CHECK-NEXT:   70000c: b       0xd00040
 
         .section .text.08, "ax", %progbits
         .space (1024 * 1024) - 4
 
         .section .text.10, "ax", %progbits
         .balign 2
         bl preemptible
         bl preemptible2
-// CHECK-CALL: 80000c: blx     0x70000c <__ARMV5PILongThunk_preemptible>
+// CHECK-CALL: 80000c: blx     0x70000c <__ARMv4PILongThunk_preemptible>
         .balign 2
         .globl preemptible
         .type preemptible, %function
 preemptible:
         bx lr
         .globl preemptible2
         .type preemptible2, %function
 preemptible2: