[X86] Support -march=sierraforest, grandridge, graniterapids.

[FreddyYe]

llvm/include/llvm/Support/X86TargetParser.def

96

FYI: gcc is going to land the sierraforest patch. They are going to add such E-core based CPUs to CPU_TYPE list but not this one, like the previous atom series e.g. tremont, silvermont and so on. It's functionally correct, so I'm ok to this change. WDYT

[FreddyYe]

llvm/include/llvm/Support/X86TargetParser.def

96

FYI: gcc is going to land the sierraforest patch. They are going to add such E-core based CPUs to CPU_TYPE list but not this one, like the previous atom series e.g. tremont, silvermont and so on. It's functionally correct, so I'm ok to this change. WDYT

ping.

[RKSimon]

llvm/lib/Target/X86/X86.td

1532

SLMModel explicitly doesn't have support for AVX/AVX2 - I think you should investigate forking SLMModel and creating a AlderlakeEModel for all of these

Also, should these be here or moved up below tremont and the other atom cores?

[FreddyYe]

Address comments.

[FreddyYe]

Rebase and add missing supports in cpu_model.c

[FreddyYe]

llvm/lib/Target/X86/X86.td

1532

Yeah, SLMModel's coverage is not right here. From view of coverage, AlderlakePModel is better here. Maybe we could use AlderlakePModel first? When sierraforest and grandridge's instruction perf info is more detailed or we can test from a real machine, we can then add a new Model and replaced here. Same for SRFTuning and GRRTuning.

[FreddyYe]

gcc has landed related patch: Sierraforest, Graniterapids and Grandrdige. We can follow their CPU list order now.

[FreddyYe]

Added ZHAOXIN_FAM7H.

[pengfei]

llvm/include/llvm/Support/X86TargetParser.def

96

Is this to match with GCC?

llvm/lib/Support/X86TargetParser.cpp

385

Is VP2INTERSECT supported by graniterapids?

[FreddyYe]

Address comments. THX for review!

[skan]

llvm/lib/Target/X86/X86.td

949

Why is this differnt from FeaturesGraniteRapids in X86TargetParser.cpp?

[FreddyYe]

Address comments. THX fore review!

llvm/include/llvm/Support/X86TargetParser.def

96

Yes.

llvm/lib/Target/X86/X86.td

949

Good catch!

[pengfei]

LGTM.

[MaskRay]

Drop trailing period from subject.

clang/test/Preprocessor/predefined-arch-macros.c

1792

Prefer --target= to legacy -target for new tests.

Consider refactoring the long CHECK lines to use delta encoding:

RUN: ... | FileCheck %s --check-prefixes=A
RUN: ... | FileCheck %s --check-prefixes=A,B
RUN: ... | FileCheck %s --check-prefixes=A,B,C

for better maintenance.

clang/docs/ReleaseNotes.rst

 - Support ISA of ``AVX-NE-CONVERT``.
   * Support intrinsic of ``_mm(256)_bcstnebf16_ps``.
   * Support intrinsic of ``_mm(256)_bcstnesh_ps``.
   * Support intrinsic of ``_mm(256)_cvtneebf16_ps``.
   * Support intrinsic of ``_mm(256)_cvtneeph_ps``.
   * Support intrinsic of ``_mm(256)_cvtneobf16_ps``.
   * Support intrinsic of ``_mm(256)_cvtneoph_ps``.
   * Support intrinsic of ``_mm(256)_cvtneps_avx_pbh``.
+* ``-march=sierraforest``, ``-march=graniterapids`` and ``-march=grandridge`` are now supported.
 
 WebAssembly Support in Clang
 ----------------------------
 
 The -mcpu=generic configuration now enables sign-ext and mutable-globals. These
 proposals are standardized and available in all major engines.
 
 DWARF Support in Clang

clang/lib/Basic/Targets/X86.cpp

void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_Cooperlake:
   case CK_Cannonlake:
   case CK_IcelakeClient:
   case CK_Rocketlake:
   case CK_IcelakeServer:
   case CK_Tigerlake:
   case CK_SapphireRapids:
   case CK_Alderlake:
+  case CK_Sierraforest:
+  case CK_Grandridge:
+  case CK_Graniterapids:
     // FIXME: Historically, we defined this legacy name, it would be nice to
     // remove it at some point. We've never exposed fine-grained names for
     // recent primary x86 CPUs, and we should keep it that way.
     defineCPUMacros(Builder, "corei7");
     break;
   case CK_KNL:
     defineCPUMacros(Builder, "knl");
     break;
switch (CPU) {
     case CK_Cooperlake:
     case CK_Cannonlake:
     case CK_Tigerlake:
     case CK_SapphireRapids:
     case CK_IcelakeClient:
     case CK_Rocketlake:
     case CK_IcelakeServer:
     case CK_Alderlake:
+    case CK_Sierraforest:
+    case CK_Grandridge:
+    case CK_Graniterapids:
     case CK_KNL:
     case CK_KNM:
     // K7
     case CK_Athlon:
     case CK_AthlonXP:
     // K8
     case CK_K8:
     case CK_K8SSE3:

clang/test/CodeGen/attr-target-mv.c

 int __attribute__((target("arch=icelake-client"))) foo(void) {return 6;}
 int __attribute__((target("arch=icelake-server"))) foo(void) {return 7;}
 int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;}
 int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
 int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
 int __attribute__((target("arch=alderlake"))) foo(void) {return 11;}
 int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;}
 int __attribute__((target("arch=core2"))) foo(void) {return 13;}
+int __attribute__((target("arch=sierraforest"))) foo(void) {return 14;}
+int __attribute__((target("arch=grandridge"))) foo(void) {return 15;}
+int __attribute__((target("arch=graniterapids"))) foo(void) {return 16;}
 int __attribute__((target("default"))) foo(void) { return 2; }
 
 int bar(void) {
   return foo();
 }
 
 inline int __attribute__((target("sse4.2"))) foo_inline(void) { return 0; }
 inline int __attribute__((target("arch=sandybridge"))) foo_inline(void);

 // LINUX: define{{.*}} i32 @foo.arch_sapphirerapids()
 // LINUX: ret i32 10
 // LINUX: define{{.*}} i32 @foo.arch_alderlake()
 // LINUX: ret i32 11
 // LINUX: define{{.*}} i32 @foo.arch_rocketlake()
 // LINUX: ret i32 12
 // LINUX: define{{.*}} i32 @foo.arch_core2()
 // LINUX: ret i32 13
+// LINUX: define{{.*}} i32 @foo.arch_sierraforest()
+// LINUX: ret i32 14
+// LINUX: define{{.*}} i32 @foo.arch_grandridge()
+// LINUX: ret i32 15
+// LINUX: define{{.*}} i32 @foo.arch_graniterapids()
+// LINUX: ret i32 16
 // LINUX: define{{.*}} i32 @foo()
 // LINUX: ret i32 2
 // LINUX: define{{.*}} i32 @bar()
 // LINUX: call i32 @foo.ifunc()
 
 // WINDOWS: define dso_local i32 @foo.sse4.2()
 // WINDOWS: ret i32 0
 // WINDOWS: define dso_local i32 @foo.arch_ivybridge()

 // WINDOWS: define dso_local i32 @foo.arch_sapphirerapids()
 // WINDOWS: ret i32 10
 // WINDOWS: define dso_local i32 @foo.arch_alderlake()
 // WINDOWS: ret i32 11
 // WINDOWS: define dso_local i32 @foo.arch_rocketlake()
 // WINDOWS: ret i32 12
 // WINDOWS: define dso_local i32 @foo.arch_core2()
 // WINDOWS: ret i32 13
+// WINDOWS: define{{.*}} i32 @foo.arch_sierraforest()
+// WINDOWS: ret i32 14
+// WINDOWS: define{{.*}} i32 @foo.arch_grandridge()
+// WINDOWS: ret i32 15
+// WINDOWS: define{{.*}} i32 @foo.arch_graniterapids()
+// WINDOWS: ret i32 16
 // WINDOWS: define dso_local i32 @foo()
 // WINDOWS: ret i32 2
 // WINDOWS: define dso_local i32 @bar()
 // WINDOWS: call i32 @foo.resolver()
 
 // LINUX: define weak_odr ptr @foo.resolver() comdat
 // LINUX: call void @__cpu_indicator_init()
 // LINUX: ret ptr @foo.arch_sandybridge

clang/test/CodeGen/target-builtin-noerror.c

void verifycpustrings(void) {
   (void)__builtin_cpu_is("btver2");
   (void)__builtin_cpu_is("cannonlake");
   (void)__builtin_cpu_is("cascadelake");
   (void)__builtin_cpu_is("cooperlake");
   (void)__builtin_cpu_is("core2");
   (void)__builtin_cpu_is("corei7");
   (void)__builtin_cpu_is("goldmont");
   (void)__builtin_cpu_is("goldmont-plus");
+  (void)__builtin_cpu_is("grandridge");
+  (void)__builtin_cpu_is("graniterapids");
   (void)__builtin_cpu_is("haswell");
   (void)__builtin_cpu_is("icelake-client");
   (void)__builtin_cpu_is("icelake-server");
   (void)__builtin_cpu_is("intel");
   (void)__builtin_cpu_is("istanbul");
   (void)__builtin_cpu_is("ivybridge");
   (void)__builtin_cpu_is("knl");
   (void)__builtin_cpu_is("knm");
   (void)__builtin_cpu_is("nehalem");
   (void)__builtin_cpu_is("rocketlake");
   (void)__builtin_cpu_is("sandybridge");
   (void)__builtin_cpu_is("shanghai");
+  (void)__builtin_cpu_is("sierraforest");
   (void)__builtin_cpu_is("silvermont");
   (void)__builtin_cpu_is("skylake");
   (void)__builtin_cpu_is("skylake-avx512");
   (void)__builtin_cpu_is("slm");
   (void)__builtin_cpu_is("tigerlake");
   (void)__builtin_cpu_is("sapphirerapids");
   (void)__builtin_cpu_is("tremont");
   (void)__builtin_cpu_is("westmere");
   (void)__builtin_cpu_is("znver1");
   (void)__builtin_cpu_is("znver2");
   (void)__builtin_cpu_is("znver3");
 }

clang/test/Driver/x86-march.c

 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=goldmont-plus 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=goldmont-plus
 // goldmont-plus: "-target-cpu" "goldmont-plus"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=tremont 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=tremont
 // tremont: "-target-cpu" "tremont"
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=sierraforest 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=sierraforest
+// sierraforest: "-target-cpu" "sierraforest"
+//
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=grandridge 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=grandridge
+// grandridge: "-target-cpu" "grandridge"
+//
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=graniterapids 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=graniterapids
+// graniterapids: "-target-cpu" "graniterapids"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=sapphirerapids 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=sapphirerapids
 // sapphirerapids: "-target-cpu" "sapphirerapids"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=k8 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=k8
 // k8: "-target-cpu" "k8"

clang/test/Misc/target-invalid-cpu-note.c

 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
 // ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
 // AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
 // TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16,  apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, grace{{$}}
 
 // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
 // X86: error: unknown target CPU 'not-a-cpu'
-// X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4, geode{{$}}
+// X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4, geode{{$}}
 
 // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64
 // X86_64: error: unknown target CPU 'not-a-cpu'
-// X86_64-NEXT: note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
+// X86_64-NEXT: note: valid target CPU values are: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, sierraforest, grandridge, graniterapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, x86-64-v2, x86-64-v3, x86-64-v4{{$}}
 
 // RUN: not %clang_cc1 -triple i386--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86
 // TUNE_X86: error: unknown target CPU 'not-a-cpu'
-// TUNE_X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
+// TUNE_X86-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
 
 // RUN: not %clang_cc1 -triple x86_64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86_64
 // TUNE_X86_64: error: unknown target CPU 'not-a-cpu'
-// TUNE_X86_64-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
+// TUNE_X86_64-NEXT: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3, i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3, pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott, nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake, icelake-client, rocketlake, icelake-server, tigerlake, sapphirerapids, alderlake, sierraforest, grandridge, graniterapids, knl, knm, lakemont, k6, k6-2, k6-3, athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, znver3, x86-64, geode{{$}}
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
 // NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, sm_80, sm_86, sm_87, sm_89, sm_90, gfx600, gfx601, gfx602, gfx700, gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103{{$}}
 
 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix R600
 // R600: error: unknown target CPU 'not-a-cpu'
 // R600-NEXT: note: valid target CPU values are: r600, rv630, rv635, r630, rs780, rs880, rv610, rv620, rv670, rv710, rv730, rv740, rv770, cedar, palm, cypress, hemlock, juniper, redwood, sumo, sumo2, barts, caicos, aruba, cayman, turks{{$}}

clang/test/Preprocessor/predefined-arch-macros.c

 // CHECK_SPR_M64: #define __amd64 1
 // CHECK_SPR_M64: #define __amd64__ 1
 // CHECK_SPR_M64: #define __corei7 1
 // CHECK_SPR_M64: #define __corei7__ 1
 // CHECK_SPR_M64: #define __tune_corei7__ 1
 // CHECK_SPR_M64: #define __x86_64 1
 // CHECK_SPR_M64: #define __x86_64__ 1
 
+// RUN: %clang -march=graniterapids -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GNR_M32
+// CHECK_GNR_M32: #define __AES__ 1
+// CHECK_GNR_M32: #define __AMXBF16__ 1
+// CHECK_GNR_M32: #define __AMXFP16__ 1
+// CHECK_GNR_M32: #define __AMXINT8__ 1
+// CHECK_GNR_M32: #define __AMXTILE__ 1
+// CHECK_GNR_M32: #define __AVX2__ 1
+// CHECK_GNR_M32: #define __AVX512BF16__ 1
+// CHECK_GNR_M32: #define __AVX512BITALG__ 1
+// CHECK_GNR_M32: #define __AVX512BW__ 1
+// CHECK_GNR_M32: #define __AVX512CD__ 1
+// CHECK_GNR_M32: #define __AVX512DQ__ 1
+// CHECK_GNR_M32: #define __AVX512FP16__ 1
+// CHECK_GNR_M32: #define __AVX512F__ 1
+// CHECK_GNR_M32: #define __AVX512IFMA__ 1
+// CHECK_GNR_M32: #define __AVX512VBMI2__ 1
+// CHECK_GNR_M32: #define __AVX512VBMI__ 1
+// CHECK_GNR_M32: #define __AVX512VL__ 1
+// CHECK_GNR_M32: #define __AVX512VNNI__ 1
+// CHECK_GNR_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_GNR_M32: #define __AVXVNNI__ 1
+// CHECK_GNR_M32: #define __AVX__ 1
+// CHECK_GNR_M32: #define __BMI2__ 1
+// CHECK_GNR_M32: #define __BMI__ 1
+// CHECK_GNR_M32: #define __CLDEMOTE__ 1
+// CHECK_GNR_M32: #define __CLFLUSHOPT__ 1
+// CHECK_GNR_M32: #define __CLWB__ 1
+// CHECK_GNR_M32: #define __ENQCMD__ 1
+// CHECK_GNR_M32: #define __F16C__ 1
+// CHECK_GNR_M32: #define __FMA__ 1
+// CHECK_GNR_M32: #define __GFNI__ 1
+// CHECK_GNR_M32: #define __INVPCID__ 1
+// CHECK_GNR_M32: #define __LZCNT__ 1
+// CHECK_GNR_M32: #define __MMX__ 1
+// CHECK_GNR_M32: #define __MOVBE__ 1
+// CHECK_GNR_M32: #define __PCLMUL__ 1
+// CHECK_GNR_M32: #define __PCONFIG__ 1
+// CHECK_GNR_M32: #define __PKU__ 1
+// CHECK_GNR_M32: #define __POPCNT__ 1
+// CHECK_GNR_M32: #define __PREFETCHI__ 1
+// CHECK_GNR_M32: #define __PRFCHW__ 1
+// CHECK_GNR_M32: #define __PTWRITE__ 1
+// CHECK_GNR_M32: #define __RDPID__ 1
+// CHECK_GNR_M32: #define __RDRND__ 1
+// CHECK_GNR_M32: #define __RDSEED__ 1
+// CHECK_GNR_M32: #define __SERIALIZE__ 1
+// CHECK_GNR_M32: #define __SGX__ 1
+// CHECK_GNR_M32: #define __SHA__ 1
+// CHECK_GNR_M32: #define __SHSTK__ 1
+// CHECK_GNR_M32: #define __SSE2__ 1
+// CHECK_GNR_M32: #define __SSE3__ 1
+// CHECK_GNR_M32: #define __SSE4_1__ 1
+// CHECK_GNR_M32: #define __SSE4_2__ 1
+// CHECK_GNR_M32: #define __SSE__ 1
+// CHECK_GNR_M32: #define __SSSE3__ 1
+// CHECK_GNR_M32: #define __TSXLDTRK__ 1
+// CHECK_GNR_M32: #define __UINTR__ 1
+// CHECK_GNR_M32: #define __VAES__ 1
+// CHECK_GNR_M32: #define __VPCLMULQDQ__ 1
+// CHECK_GNR_M32: #define __WAITPKG__ 1
+// CHECK_GNR_M32: #define __WBNOINVD__ 1
+// CHECK_GNR_M32: #define __XSAVEC__ 1
+// CHECK_GNR_M32: #define __XSAVEOPT__ 1
+// CHECK_GNR_M32: #define __XSAVES__ 1
+// CHECK_GNR_M32: #define __XSAVE__ 1
+// CHECK_GNR_M32: #define __corei7 1
+// CHECK_GNR_M32: #define __corei7__ 1
+// CHECK_GNR_M32: #define __i386 1
+// CHECK_GNR_M32: #define __i386__ 1
+// CHECK_GNR_M32: #define __tune_corei7__ 1
+// CHECK_GNR_M32: #define i386 1
+
+// RUN: %clang -march=graniterapids -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GNR_M64
+// CHECK_GNR_M64: #define __AES__ 1
+// CHECK_GNR_M64: #define __AMXBF16__ 1
+// CHECK_GNR_M64: #define __AMXFP16__ 1
+// CHECK_GNR_M64: #define __AMXINT8__ 1
+// CHECK_GNR_M64: #define __AMXTILE__ 1
+// CHECK_GNR_M64: #define __AVX2__ 1
+// CHECK_GNR_M64: #define __AVX512BF16__ 1
+// CHECK_GNR_M64: #define __AVX512BITALG__ 1
+// CHECK_GNR_M64: #define __AVX512BW__ 1
+// CHECK_GNR_M64: #define __AVX512CD__ 1
+// CHECK_GNR_M64: #define __AVX512DQ__ 1
+// CHECK_GNR_M64: #define __AVX512FP16__ 1
+// CHECK_GNR_M64: #define __AVX512F__ 1
+// CHECK_GNR_M64: #define __AVX512IFMA__ 1
+// CHECK_GNR_M64: #define __AVX512VBMI2__ 1
+// CHECK_GNR_M64: #define __AVX512VBMI__ 1
+// CHECK_GNR_M64: #define __AVX512VL__ 1
+// CHECK_GNR_M64: #define __AVX512VNNI__ 1
+// CHECK_GNR_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_GNR_M64: #define __AVXVNNI__ 1
+// CHECK_GNR_M64: #define __AVX__ 1
+// CHECK_GNR_M64: #define __BMI2__ 1
+// CHECK_GNR_M64: #define __BMI__ 1
+// CHECK_GNR_M64: #define __CLDEMOTE__ 1
+// CHECK_GNR_M64: #define __CLFLUSHOPT__ 1
+// CHECK_GNR_M64: #define __CLWB__ 1
+// CHECK_GNR_M64: #define __ENQCMD__ 1
+// CHECK_GNR_M64: #define __F16C__ 1
+// CHECK_GNR_M64: #define __FMA__ 1
+// CHECK_GNR_M64: #define __GFNI__ 1
+// CHECK_GNR_M64: #define __INVPCID__ 1
+// CHECK_GNR_M64: #define __LZCNT__ 1
+// CHECK_GNR_M64: #define __MMX__ 1
+// CHECK_GNR_M64: #define __MOVBE__ 1
+// CHECK_GNR_M64: #define __PCLMUL__ 1
+// CHECK_GNR_M64: #define __PCONFIG__ 1
+// CHECK_GNR_M64: #define __PKU__ 1
+// CHECK_GNR_M64: #define __POPCNT__ 1
+// CHECK_GNR_M64: #define __PREFETCHI__ 1
+// CHECK_GNR_M64: #define __PRFCHW__ 1
+// CHECK_GNR_M64: #define __PTWRITE__ 1
+// CHECK_GNR_M64: #define __RDPID__ 1
+// CHECK_GNR_M64: #define __RDRND__ 1
+// CHECK_GNR_M64: #define __RDSEED__ 1
+// CHECK_GNR_M64: #define __SERIALIZE__ 1
+// CHECK_GNR_M64: #define __SGX__ 1
+// CHECK_GNR_M64: #define __SHA__ 1
+// CHECK_GNR_M64: #define __SHSTK__ 1
+// CHECK_GNR_M64: #define __SSE2__ 1
+// CHECK_GNR_M64: #define __SSE3__ 1
+// CHECK_GNR_M64: #define __SSE4_1__ 1
+// CHECK_GNR_M64: #define __SSE4_2__ 1
+// CHECK_GNR_M64: #define __SSE__ 1
+// CHECK_GNR_M64: #define __SSSE3__ 1
+// CHECK_GNR_M64: #define __TSXLDTRK__ 1
+// CHECK_GNR_M64: #define __UINTR__ 1
+// CHECK_GNR_M64: #define __VAES__ 1
+// CHECK_GNR_M64: #define __VPCLMULQDQ__ 1
+// CHECK_GNR_M64: #define __WAITPKG__ 1
+// CHECK_GNR_M64: #define __WBNOINVD__ 1
+// CHECK_GNR_M64: #define __XSAVEC__ 1
+// CHECK_GNR_M64: #define __XSAVEOPT__ 1
+// CHECK_GNR_M64: #define __XSAVES__ 1
+// CHECK_GNR_M64: #define __XSAVE__ 1
+// CHECK_GNR_M64: #define __amd64 1
+// CHECK_GNR_M64: #define __amd64__ 1
+// CHECK_GNR_M64: #define __corei7 1
+// CHECK_GNR_M64: #define __corei7__ 1
+// CHECK_GNR_M64: #define __tune_corei7__ 1
+// CHECK_GNR_M64: #define __x86_64 1
+// CHECK_GNR_M64: #define __x86_64__ 1
+
 // RUN: %clang -march=alderlake -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_ADL_M32
 // CHECK_ADL_M32: #define __ADX__ 1
 // CHECK_ADL_M32: #define __AES__ 1
 // CHECK_ADL_M32: #define __AVX2__ 1
 // CHECK_ADL_M32-NOT: AVX512
 // CHECK_ADL_M32: #define __AVXVNNI__ 1

 // CHECK_LAKEMONT_M32: #define __pentium__ 1
 // CHECK_LAKEMONT_M32: #define __tune_lakemont__ 1
 // CHECK_LAKEMONT_M32: #define i386 1
 // RUN: not %clang -march=lakemont -m64 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck %s -check-prefix=CHECK_LAKEMONT_M64
 // CHECK_LAKEMONT_M64: error:
 
+// RUN: %clang -march=sierraforest -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
+// CHECK_SRF_M32: #define __ADX__ 1
+// CHECK_SRF_M32: #define __AES__ 1
+// CHECK_SRF_M32: #define __AVX2__ 1
+// CHECK_SRF_M32-NOT: AVX512
+// CHECK_SRF_M32: #define __AVXIFMA__ 1
+// CHECK_SRF_M32: #define __AVXNECONVERT__ 1
+// CHECK_SRF_M32: #define __AVXVNNIINT8__ 1
+// CHECK_SRF_M32: #define __AVXVNNI__ 1
+// CHECK_SRF_M32: #define __AVX__ 1
+// CHECK_SRF_M32: #define __BMI2__ 1
+// CHECK_SRF_M32: #define __BMI__ 1
+// CHECK_SRF_M32: #define __CLDEMOTE__ 1
+// CHECK_SRF_M32: #define __CLFLUSHOPT__ 1
+// CHECK_SRF_M32: #define __CLWB__ 1
+// CHECK_SRF_M32: #define __CMPCCXADD__ 1
+// CHECK_SRF_M32: #define __F16C__ 1
+// CHECK_SRF_M32: #define __FMA__ 1
+// CHECK_SRF_M32: #define __FSGSBASE__ 1
+// CHECK_SRF_M32: #define __FXSR__ 1
+// CHECK_SRF_M32: #define __GFNI__ 1
+// CHECK_SRF_M32: #define __HRESET__ 1
+// CHECK_SRF_M32: #define __INVPCID__ 1
+// CHECK_SRF_M32: #define __KL__ 1
+// CHECK_SRF_M32: #define __LZCNT__ 1
+// CHECK_SRF_M32: #define __MMX__ 1
+// CHECK_SRF_M32: #define __MOVBE__ 1
+// CHECK_SRF_M32: #define __MOVDIR64B__ 1
+// CHECK_SRF_M32: #define __MOVDIRI__ 1
+// CHECK_SRF_M32: #define __PCLMUL__ 1
+// CHECK_SRF_M32: #define __PCONFIG__ 1
+// CHECK_SRF_M32: #define __PKU__ 1
+// CHECK_SRF_M32: #define __POPCNT__ 1
+// CHECK_SRF_M32: #define __PRFCHW__ 1
+// CHECK_SRF_M32: #define __PTWRITE__ 1
+// CHECK_SRF_M32: #define __RDPID__ 1
+// CHECK_SRF_M32: #define __RDRND__ 1
+// CHECK_SRF_M32: #define __RDSEED__ 1
+// CHECK_SRF_M32: #define __SERIALIZE__ 1
+// CHECK_SRF_M32: #define __SGX__ 1
+// CHECK_SRF_M32: #define __SHA__ 1
+// CHECK_SRF_M32: #define __SHSTK__ 1
+// CHECK_SRF_M32: #define __SSE2__ 1
+// CHECK_SRF_M32: #define __SSE3__ 1
+// CHECK_SRF_M32: #define __SSE4_1__ 1
+// CHECK_SRF_M32: #define __SSE4_2__ 1
+// CHECK_SRF_M32: #define __SSE_MATH__ 1
+// CHECK_SRF_M32: #define __SSE__ 1
+// CHECK_SRF_M32: #define __SSSE3__ 1
+// CHECK_SRF_M32: #define __VAES__ 1
+// CHECK_SRF_M32: #define __VPCLMULQDQ__ 1
+// CHECK_SRF_M32: #define __WAITPKG__ 1
+// CHECK_SRF_M32: #define __WIDEKL__ 1
+// CHECK_SRF_M32: #define __XSAVEC__ 1
+// CHECK_SRF_M32: #define __XSAVEOPT__ 1
+// CHECK_SRF_M32: #define __XSAVES__ 1
+// CHECK_SRF_M32: #define __XSAVE__ 1
+// CHECK_SRF_M32: #define __corei7 1
+// CHECK_SRF_M32: #define __corei7__ 1
+// CHECK_SRF_M32: #define __i386 1
+// CHECK_SRF_M32: #define __i386__ 1
+// CHECK_SRF_M32: #define __tune_corei7__ 1
+// CHECK_SRF_M32: #define i386 1
+
+// RUN: %clang -march=sierraforest -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
+// CHECK_SRF_M64: #define __ADX__ 1
+// CHECK_SRF_M64: #define __AES__ 1
+// CHECK_SRF_M64: #define __AVX2__ 1
+// CHECK_SRF_M64-NOT: AVX512
+// CHECK_SRF_M64: #define __AVXIFMA__ 1
+// CHECK_SRF_M64: #define __AVXNECONVERT__ 1
+// CHECK_SRF_M64: #define __AVXVNNIINT8__ 1
+// CHECK_SRF_M64: #define __AVXVNNI__ 1
+// CHECK_SRF_M64: #define __AVX__ 1
+// CHECK_SRF_M64: #define __BMI2__ 1
+// CHECK_SRF_M64: #define __BMI__ 1
+// CHECK_SRF_M64: #define __CLDEMOTE__ 1
+// CHECK_SRF_M64: #define __CLFLUSHOPT__ 1
+// CHECK_SRF_M64: #define __CLWB__ 1
+// CHECK_SRF_M64: #define __CMPCCXADD__ 1
+// CHECK_SRF_M64: #define __F16C__ 1
+// CHECK_SRF_M64: #define __FMA__ 1
+// CHECK_SRF_M64: #define __FSGSBASE__ 1
+// CHECK_SRF_M64: #define __FXSR__ 1
+// CHECK_SRF_M64: #define __GFNI__ 1
+// CHECK_SRF_M64: #define __HRESET__ 1
+// CHECK_SRF_M64: #define __INVPCID__ 1
+// CHECK_SRF_M64: #define __KL__ 1
+// CHECK_SRF_M64: #define __LZCNT__ 1
+// CHECK_SRF_M64: #define __MMX__ 1
+// CHECK_SRF_M64: #define __MOVBE__ 1
+// CHECK_SRF_M64: #define __MOVDIR64B__ 1
+// CHECK_SRF_M64: #define __MOVDIRI__ 1
+// CHECK_SRF_M64: #define __PCLMUL__ 1
+// CHECK_SRF_M64: #define __PCONFIG__ 1
+// CHECK_SRF_M64: #define __PKU__ 1
+// CHECK_SRF_M64: #define __POPCNT__ 1
+// CHECK_SRF_M64: #define __PRFCHW__ 1
+// CHECK_SRF_M64: #define __PTWRITE__ 1
+// CHECK_SRF_M64: #define __RDPID__ 1
+// CHECK_SRF_M64: #define __RDRND__ 1
+// CHECK_SRF_M64: #define __RDSEED__ 1
+// CHECK_SRF_M64: #define __SERIALIZE__ 1
+// CHECK_SRF_M64: #define __SGX__ 1
+// CHECK_SRF_M64: #define __SHA__ 1
+// CHECK_SRF_M64: #define __SHSTK__ 1
+// CHECK_SRF_M64: #define __SSE2_MATH__ 1
+// CHECK_SRF_M64: #define __SSE2__ 1
+// CHECK_SRF_M64: #define __SSE3__ 1
+// CHECK_SRF_M64: #define __SSE4_1__ 1
+// CHECK_SRF_M64: #define __SSE4_2__ 1
+// CHECK_SRF_M64: #define __SSE_MATH__ 1
+// CHECK_SRF_M64: #define __SSE__ 1
+// CHECK_SRF_M64: #define __SSSE3__ 1
+// CHECK_SRF_M64: #define __VAES__ 1
+// CHECK_SRF_M64: #define __VPCLMULQDQ__ 1
+// CHECK_SRF_M64: #define __WAITPKG__ 1
+// CHECK_SRF_M64: #define __WIDEKL__ 1
+// CHECK_SRF_M64: #define __XSAVEC__ 1
+// CHECK_SRF_M64: #define __XSAVEOPT__ 1
+// CHECK_SRF_M64: #define __XSAVES__ 1
+// CHECK_SRF_M64: #define __XSAVE__ 1
+// CHECK_SRF_M64: #define __amd64 1
+// CHECK_SRF_M64: #define __amd64__ 1
+// CHECK_SRF_M64: #define __corei7 1
+// CHECK_SRF_M64: #define __corei7__ 1
+// CHECK_SRF_M64: #define __tune_corei7__ 1
+// CHECK_SRF_M64: #define __x86_64 1
+// CHECK_SRF_M64: #define __x86_64__ 1
+
+// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GRR_M32
+// CHECK_GRR_M32: #define __ADX__ 1
+// CHECK_GRR_M32: #define __AES__ 1
+// CHECK_GRR_M32: #define __AVX2__ 1
+// CHECK_GRR_M32-NOT: AVX512
+// CHECK_GRR_M32: #define __AVXIFMA__ 1
+// CHECK_GRR_M32: #define __AVXNECONVERT__ 1
+// CHECK_GRR_M32: #define __AVXVNNIINT8__ 1
+// CHECK_GRR_M32: #define __AVXVNNI__ 1
+// CHECK_GRR_M32: #define __AVX__ 1
+// CHECK_GRR_M32: #define __BMI2__ 1
+// CHECK_GRR_M32: #define __BMI__ 1
+// CHECK_GRR_M32: #define __CLDEMOTE__ 1
+// CHECK_GRR_M32: #define __CLFLUSHOPT__ 1
+// CHECK_GRR_M32: #define __CLWB__ 1
+// CHECK_GRR_M32: #define __CMPCCXADD__ 1
+// CHECK_GRR_M32: #define __F16C__ 1
+// CHECK_GRR_M32: #define __FMA__ 1
+// CHECK_GRR_M32: #define __FSGSBASE__ 1
+// CHECK_GRR_M32: #define __FXSR__ 1
+// CHECK_GRR_M32: #define __GFNI__ 1
+// CHECK_GRR_M32: #define __HRESET__ 1
+// CHECK_GRR_M32: #define __INVPCID__ 1
+// CHECK_GRR_M32: #define __KL__ 1
+// CHECK_GRR_M32: #define __LZCNT__ 1
+// CHECK_GRR_M32: #define __MMX__ 1
+// CHECK_GRR_M32: #define __MOVBE__ 1
+// CHECK_GRR_M32: #define __MOVDIR64B__ 1
+// CHECK_GRR_M32: #define __MOVDIRI__ 1
+// CHECK_GRR_M32: #define __PCLMUL__ 1
+// CHECK_GRR_M32: #define __PCONFIG__ 1
+// CHECK_GRR_M32: #define __PKU__ 1
+// CHECK_GRR_M32: #define __POPCNT__ 1
+// CHECK_GRR_M32: #define __PRFCHW__ 1
+// CHECK_GRR_M32: #define __PTWRITE__ 1
+// CHECK_GRR_M32: #define __RAOINT__ 1
+// CHECK_GRR_M32: #define __RDPID__ 1
+// CHECK_GRR_M32: #define __RDRND__ 1
+// CHECK_GRR_M32: #define __RDSEED__ 1
+// CHECK_GRR_M32: #define __SERIALIZE__ 1
+// CHECK_GRR_M32: #define __SGX__ 1
+// CHECK_GRR_M32: #define __SHA__ 1
+// CHECK_GRR_M32: #define __SHSTK__ 1
+// CHECK_GRR_M32: #define __SSE2__ 1
+// CHECK_GRR_M32: #define __SSE3__ 1
+// CHECK_GRR_M32: #define __SSE4_1__ 1
+// CHECK_GRR_M32: #define __SSE4_2__ 1
+// CHECK_GRR_M32: #define __SSE_MATH__ 1
+// CHECK_GRR_M32: #define __SSE__ 1
+// CHECK_GRR_M32: #define __SSSE3__ 1
+// CHECK_GRR_M32: #define __VAES__ 1
+// CHECK_GRR_M32: #define __VPCLMULQDQ__ 1
+// CHECK_GRR_M32: #define __WAITPKG__ 1
+// CHECK_GRR_M32: #define __WIDEKL__ 1
+// CHECK_GRR_M32: #define __XSAVEC__ 1
+// CHECK_GRR_M32: #define __XSAVEOPT__ 1
+// CHECK_GRR_M32: #define __XSAVES__ 1
+// CHECK_GRR_M32: #define __XSAVE__ 1
+// CHECK_GRR_M32: #define __corei7 1
+// CHECK_GRR_M32: #define __corei7__ 1
+// CHECK_GRR_M32: #define __i386 1
+// CHECK_GRR_M32: #define __i386__ 1
+// CHECK_GRR_M32: #define __tune_corei7__ 1
+// CHECK_GRR_M32: #define i386 1
+
+// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GRR_M64
+// CHECK_GRR_M64: #define __ADX__ 1
+// CHECK_GRR_M64: #define __AES__ 1
+// CHECK_GRR_M64: #define __AVX2__ 1
+// CHECK_GRR_M64-NOT: AVX512
+// CHECK_GRR_M64: #define __AVXIFMA__ 1
+// CHECK_GRR_M64: #define __AVXNECONVERT__ 1
+// CHECK_GRR_M64: #define __AVXVNNIINT8__ 1
+// CHECK_GRR_M64: #define __AVXVNNI__ 1
+// CHECK_GRR_M64: #define __AVX__ 1
+// CHECK_GRR_M64: #define __BMI2__ 1
+// CHECK_GRR_M64: #define __BMI__ 1
+// CHECK_GRR_M64: #define __CLDEMOTE__ 1
+// CHECK_GRR_M64: #define __CLFLUSHOPT__ 1
+// CHECK_GRR_M64: #define __CLWB__ 1
+// CHECK_GRR_M64: #define __CMPCCXADD__ 1
+// CHECK_GRR_M64: #define __F16C__ 1
+// CHECK_GRR_M64: #define __FMA__ 1
+// CHECK_GRR_M64: #define __FSGSBASE__ 1
+// CHECK_GRR_M64: #define __FXSR__ 1
+// CHECK_GRR_M64: #define __GFNI__ 1
+// CHECK_GRR_M64: #define __HRESET__ 1
+// CHECK_GRR_M64: #define __INVPCID__ 1
+// CHECK_GRR_M64: #define __KL__ 1
+// CHECK_GRR_M64: #define __LZCNT__ 1
+// CHECK_GRR_M64: #define __MMX__ 1
+// CHECK_GRR_M64: #define __MOVBE__ 1
+// CHECK_GRR_M64: #define __MOVDIR64B__ 1
+// CHECK_GRR_M64: #define __MOVDIRI__ 1
+// CHECK_GRR_M64: #define __PCLMUL__ 1
+// CHECK_GRR_M64: #define __PCONFIG__ 1
+// CHECK_GRR_M64: #define __PKU__ 1
+// CHECK_GRR_M64: #define __POPCNT__ 1
+// CHECK_GRR_M64: #define __PRFCHW__ 1
+// CHECK_GRR_M64: #define __PTWRITE__ 1
+// CHECK_GRR_M64: #define __RAOINT__ 1
+// CHECK_GRR_M64: #define __RDPID__ 1
+// CHECK_GRR_M64: #define __RDRND__ 1
+// CHECK_GRR_M64: #define __RDSEED__ 1
+// CHECK_GRR_M64: #define __SERIALIZE__ 1
+// CHECK_GRR_M64: #define __SGX__ 1
+// CHECK_GRR_M64: #define __SHA__ 1
+// CHECK_GRR_M64: #define __SHSTK__ 1
+// CHECK_GRR_M64: #define __SSE2_MATH__ 1
+// CHECK_GRR_M64: #define __SSE2__ 1
+// CHECK_GRR_M64: #define __SSE3__ 1
+// CHECK_GRR_M64: #define __SSE4_1__ 1
+// CHECK_GRR_M64: #define __SSE4_2__ 1
+// CHECK_GRR_M64: #define __SSE_MATH__ 1
+// CHECK_GRR_M64: #define __SSE__ 1
+// CHECK_GRR_M64: #define __SSSE3__ 1
+// CHECK_GRR_M64: #define __VAES__ 1
+// CHECK_GRR_M64: #define __VPCLMULQDQ__ 1
+// CHECK_GRR_M64: #define __WAITPKG__ 1
+// CHECK_GRR_M64: #define __WIDEKL__ 1
+// CHECK_GRR_M64: #define __XSAVEC__ 1
+// CHECK_GRR_M64: #define __XSAVEOPT__ 1
+// CHECK_GRR_M64: #define __XSAVES__ 1
+// CHECK_GRR_M64: #define __XSAVE__ 1
+// CHECK_GRR_M64: #define __amd64 1
+// CHECK_GRR_M64: #define __amd64__ 1
+// CHECK_GRR_M64: #define __corei7 1
+// CHECK_GRR_M64: #define __corei7__ 1
+// CHECK_GRR_M64: #define __tune_corei7__ 1
+// CHECK_GRR_M64: #define __x86_64 1
+// CHECK_GRR_M64: #define __x86_64__ 1
+
 // RUN: %clang -march=geode -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GEODE_M32
 // CHECK_GEODE_M32: #define __3dNOW_A__ 1
 // CHECK_GEODE_M32: #define __3dNOW__ 1
 // CHECK_GEODE_M32: #define __MMX__ 1
 // CHECK_GEODE_M32: #define __geode 1
 // CHECK_GEODE_M32: #define __geode__ 1

compiler-rt/lib/builtins/cpu_model.c

enum ProcessorTypes {
   AMD_BTVER1,
   AMD_BTVER2,
   AMDFAM17H,
   INTEL_KNM,
   INTEL_GOLDMONT,
   INTEL_GOLDMONT_PLUS,
   INTEL_TREMONT,
   AMDFAM19H,
+  INTEL_SIERRAFOREST,
+  INTEL_GRANDRIDGE,
   CPU_TYPE_MAX
 };
 
 enum ProcessorSubtypes {
   INTEL_COREI7_NEHALEM = 1,
   INTEL_COREI7_WESTMERE,
   INTEL_COREI7_SANDYBRIDGE,
   AMDFAM10H_BARCELONA,
enum ProcessorSubtypes {
   AMDFAM17H_ZNVER2,
   INTEL_COREI7_CASCADELAKE,
   INTEL_COREI7_TIGERLAKE,
   INTEL_COREI7_COOPERLAKE,
   INTEL_COREI7_SAPPHIRERAPIDS,
   INTEL_COREI7_ALDERLAKE,
   AMDFAM19H_ZNVER3,
   INTEL_COREI7_ROCKETLAKE,
+  ZHAOXIN_FAM7H_LUJIAZUI,
+  AMDFAM19H_ZNVER4,
+  INTEL_COREI7_GRANITERAPIDS,
   CPU_SUBTYPE_MAX
 };
 
 enum ProcessorFeatures {
   FEATURE_CMOV = 0,
   FEATURE_MMX,
   FEATURE_POPCNT,
   FEATURE_SSE,
case 6:
 
     // Sapphire Rapids:
     case 0x8f:
       CPU = "sapphirerapids";
       *Type = INTEL_COREI7;
       *Subtype = INTEL_COREI7_SAPPHIRERAPIDS;
       break;
 
+    // Graniterapids:
+    case 0xae:
+    case 0xad:
+      CPU = "graniterapids";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_GRANITERAPIDS;
+      break;
+
     case 0x1c: // Most 45 nm Intel Atom processors
     case 0x26: // 45 nm Atom Lincroft
     case 0x27: // 32 nm Atom Medfield
     case 0x35: // 32 nm Atom Midview
     case 0x36: // 32 nm Atom Midview
       CPU = "bonnell";
       *Type = INTEL_BONNELL;
       break;
case 0x7a:
       CPU = "goldmont-plus";
       *Type = INTEL_GOLDMONT_PLUS;
       break;
     case 0x86:
       CPU = "tremont";
       *Type = INTEL_TREMONT;
       break;
 
+    // Sierraforest:
+    case 0xaf:
+      CPU = "sierraforest";
+      *Type = INTEL_SIERRAFOREST;
+      break;
+
+    // Grandridge:
+    case 0xb6:
+      CPU = "grandridge";
+      *Type = INTEL_GRANDRIDGE;
+      break;
+
     case 0x57:
       CPU = "knl";
       *Type = INTEL_KNL;
       break;
 
     case 0x85:
       CPU = "knm";
       *Type = INTEL_KNM;

llvm/docs/ReleaseNotes.rst

 
 * Add support for the ``RDMSRLIST and WRMSRLIST`` instructions.
 * Add support for the ``WRMSRNS`` instruction.
 * Support ISA of ``AMX-FP16`` which contains ``tdpfp16ps`` instruction.
 * Support ISA of ``CMPCCXADD``.
 * Support ISA of ``AVX-IFMA``.
 * Support ISA of ``AVX-VNNI-INT8``.
 * Support ISA of ``AVX-NE-CONVERT``.
+* ``-mcpu=sierraforest``, ``-mcpu=graniterapids`` and ``-mcpu=grandridge`` are now supported.
 
 Changes to the OCaml bindings
 -----------------------------
 
 
 Changes to the C API
 --------------------
 

llvm/include/llvm/Support/X86TargetParser.h

enum CPUKind {
   CK_Cooperlake,
   CK_Cannonlake,
   CK_IcelakeClient,
   CK_Rocketlake,
   CK_IcelakeServer,
   CK_Tigerlake,
   CK_SapphireRapids,
   CK_Alderlake,
+  CK_Sierraforest,
+  CK_Grandridge,
+  CK_Graniterapids,
   CK_KNL,
   CK_KNM,
   CK_Lakemont,
   CK_K6,
   CK_K6_2,
   CK_K6_3,
   CK_Athlon,
   CK_AthlonXP,

llvm/include/llvm/Support/X86TargetParser.def

 X86_CPU_TYPE(AMD_BTVER1,          "btver1")
 X86_CPU_TYPE(AMD_BTVER2,          "btver2")
 X86_CPU_TYPE(AMDFAM17H,           "amdfam17h")
 X86_CPU_TYPE(INTEL_KNM,           "knm")
 X86_CPU_TYPE(INTEL_GOLDMONT,      "goldmont")
 X86_CPU_TYPE(INTEL_GOLDMONT_PLUS, "goldmont-plus")
 X86_CPU_TYPE(INTEL_TREMONT,       "tremont")
 X86_CPU_TYPE(AMDFAM19H,           "amdfam19h")
+X86_CPU_TYPE(INTEL_SIERRAFOREST,  "sierraforest")
+X86_CPU_TYPE(INTEL_GRANDRIDGE,    "grandridge")
 
 // Alternate names supported by __builtin_cpu_is and target multiversioning.
 X86_CPU_TYPE_ALIAS(INTEL_BONNELL,    "atom")
 X86_CPU_TYPE_ALIAS(AMDFAM10H,        "amdfam10")
 X86_CPU_TYPE_ALIAS(AMDFAM15H,        "amdfam15")
 X86_CPU_TYPE_ALIAS(INTEL_SILVERMONT, "slm")
 
 #undef X86_CPU_TYPE_ALIAS

 X86_CPU_SUBTYPE(AMDFAM17H_ZNVER2,            "znver2")
 X86_CPU_SUBTYPE(INTEL_COREI7_CASCADELAKE,    "cascadelake")
 X86_CPU_SUBTYPE(INTEL_COREI7_TIGERLAKE,      "tigerlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_COOPERLAKE,     "cooperlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids")
 X86_CPU_SUBTYPE(INTEL_COREI7_ALDERLAKE,      "alderlake")
 X86_CPU_SUBTYPE(AMDFAM19H_ZNVER3,            "znver3")
 X86_CPU_SUBTYPE(INTEL_COREI7_ROCKETLAKE,     "rocketlake")
+X86_CPU_SUBTYPE(ZHAOXIN_FAM7H_LUJIAZUI,      "zhaoxin_fam7h_lujiazui")
+X86_CPU_SUBTYPE(AMDFAM19H_ZNVER4,            "znver4")
+X86_CPU_SUBTYPE(INTEL_COREI7_GRANITERAPIDS,  "graniterapids")
 #undef X86_CPU_SUBTYPE
 
 // This macro is used for cpu types present in compiler-rt/libgcc. The third
 // parameter PRIORITY is as required by the attribute 'target' checking. Note
 // that not all are supported/prioritized by GCC, so synchronization with GCC's
 // implementation may require changing some existing values.
 //
 // We cannot just re-sort the list though because its order is dictated by the

llvm/lib/Support/Host.cpp

case 6:
     // Alderlake:
     case 0x97:
     case 0x9a:
       CPU = "alderlake";
       *Type = X86::INTEL_COREI7;
       *Subtype = X86::INTEL_COREI7_ALDERLAKE;
       break;
 
+    // Graniterapids:
+    case 0xae:
+    case 0xad:
+      CPU = "graniterapids";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
+      break;
+
     // Icelake Xeon:
     case 0x6a:
     case 0x6c:
       CPU = "icelake-server";
       *Type = X86::INTEL_COREI7;
       *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
       break;
 
case 0x7a:
       CPU = "goldmont-plus";
       *Type = X86::INTEL_GOLDMONT_PLUS;
       break;
     case 0x86:
       CPU = "tremont";
       *Type = X86::INTEL_TREMONT;
       break;
 
+    // Sierraforest:
+    case 0xaf:
+      CPU = "sierraforest";
+      *Type = X86::INTEL_SIERRAFOREST;
+      break;
+
+    // Grandridge:
+    case 0xb6:
+      CPU = "grandridge";
+      *Type = X86::INTEL_GRANDRIDGE;
+      break;
+
     // Xeon Phi (Knights Landing + Knights Mill):
     case 0x57:
       CPU = "knl";
       *Type = X86::INTEL_KNL;
       break;
     case 0x85:
       CPU = "knm";
       *Type = X86::INTEL_KNM;

llvm/lib/Support/X86TargetParser.cpp

constexpr FeatureBitset FeaturesTigerlake =
     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
     FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
 constexpr FeatureBitset FeaturesSapphireRapids =
     FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
     FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
     FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
     FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
     FeatureWAITPKG;
+constexpr FeatureBitset FeaturesGraniteRapids =
+    FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
 constexpr FeatureBitset FeaturesSilvermont =
     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
 constexpr FeatureBitset FeaturesGoldmont =
     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
     FeatureXSAVEOPT | FeatureXSAVES;
 constexpr FeatureBitset FeaturesGoldmontPlus =
     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
 constexpr FeatureBitset FeaturesTremont =
     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
 constexpr FeatureBitset FeaturesAlderlake =
     FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
     FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
     FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
     FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
     FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
+constexpr FeatureBitset FeaturesSierraforest =
+    FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
+    FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
+constexpr FeatureBitset FeaturesGrandridge =
+    FeaturesSierraforest | FeatureRAOINT;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
 
 // K6 processor.
 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
 
constexpr ProcInfo Processors[] = {
   // Icelake server microarchitecture based processors.
   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
   // Tigerlake microarchitecture based processors.
   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
   // Sapphire Rapids microarchitecture based processors.
   { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
   // Alderlake microarchitecture based processors.
   { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
+  // Sierraforest microarchitecture based processors.
+  { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest },
+  // Grandridge microarchitecture based processors.
+  { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge },
+  // Graniterapids microarchitecture based processors.
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512VP2INTERSECT, FeaturesGraniteRapids },
   // Knights Landing processor.
   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
   // Knights Mill processor.
   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
   // Lakemont microarchitecture based processors.
   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
   // K6 architecture processors.
   { {"k6"}, CK_K6, ~0U, FeaturesK6 },

llvm/lib/Target/X86/X86.td

list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps,
                                                 TuningPERMFalseDeps,
                                                 TuningRANGEFalseDeps,
                                                 TuningGETMANTFalseDeps,
                                                 TuningMULLQFalseDeps];
   list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning);
   list<SubtargetFeature> SPRFeatures =
     !listconcat(ICXFeatures, SPRAdditionalFeatures);
 
+  // Graniterapids
+  list<SubtargetFeature> GNRAdditionalFeatures = [FeatureAMXTILE,
+                                                  FeatureAMXINT8,
+                                                  FeatureAMXBF16,
+                                                  FeatureBF16];
+  list<SubtargetFeature> GNRFeatures =
+    !listconcat(SPRFeatures, GNRAdditionalFeatures);
+
   // Atom
   list<SubtargetFeature> AtomFeatures = [FeatureX87,
                                          FeatureCX8,
                                          FeatureCMOV,
                                          FeatureMMX,
                                          FeatureSSSE3,
                                          FeatureFXSR,
                                          FeatureNOPL,
list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,
                                                   FeatureMOVDIRI,
                                                   FeatureMOVDIR64B,
                                                   FeatureWAITPKG];
   list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps];
   list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
   list<SubtargetFeature> ADLFeatures =
     !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
+  // Sierraforest
+  list<SubtargetFeature> SRFAdditionalFeatures = [FeatureCMPCCXADD,
+                                                  FeatureAVXIFMA,
+                                                  FeatureAVXNECONVERT,
+                                                  FeatureAVXVNNIINT8];
+  list<SubtargetFeature> SRFFeatures =
+    !listconcat(ADLFeatures, SRFAdditionalFeatures);
+
+  // Grandridge
+  list<SubtargetFeature> GRRAdditionalFeatures = [FeatureRAOINT];
+  list<SubtargetFeature> GRRFeatures =
+    !listconcat(SRFFeatures, GRRAdditionalFeatures);
+
   // Knights Landing
   list<SubtargetFeature> KNLFeatures = [FeatureX87,
                                         FeatureCX8,
                                         FeatureCMOV,
                                         FeatureMMX,
                                         FeatureFXSR,
                                         FeatureNOPL,
                                         FeatureX86_64,

 }
 
 def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
                 ProcessorFeatures.GLMTuning>;
 def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
                 ProcessorFeatures.GLPTuning>;
 def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
                 ProcessorFeatures.TRMTuning>;
+def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
+                ProcessorFeatures.TRMTuning>;
+def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+                ProcessorFeatures.TRMTuning>;
 
 // "Arrandale" along with corei3 and corei5
 foreach P = ["nehalem", "corei7"] in {
   def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
                   ProcessorFeatures.NHMTuning>;
 }
 
 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge

 def : ProcModel<"icelake-server", IceLakeModel,
                 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", IceLakeModel,
                 ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
 def : ProcModel<"sapphirerapids", SkylakeServerModel,
                 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
 def : ProcModel<"alderlake", AlderlakePModel,
                 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
+def : ProcModel<"graniterapids", SkylakeServerModel,
+                ProcessorFeatures.GNRFeatures, ProcessorFeatures.SPRTuning>;
 
 // AMD CPUs.
 
 def : Proc<"k6",   [FeatureX87, FeatureCX8, FeatureMMX],
                    [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
                    [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],
                    [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;

llvm/test/CodeGen/X86/cpus-intel.ll

 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nehalem 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=corei7 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=westmere 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sandybridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=slm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
 }