[AArch64][SME2] Add rudimentary LLVM support for aarch64_svcount.
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Authored by sdesmalen on Oct 27 2022, 10:01 AM.

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Reviewers

efriedma
t.p.northover
aemerson
paulwalker-arm

Summary

The aarch64_svcount opaque type is a scalable type. This patch adds AArch64
CodeGen support such that the type can be passed and returned to/from
functions, and also adds support to use this type in load/store operations
and PHI nodes.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

sdesmalen created this revision.Oct 27 2022, 10:01 AM

Herald added a project: Restricted Project. · View Herald TranscriptOct 27 2022, 10:01 AM

Herald added subscribers: ecnelises, hiraditya, kristof.beyls. · View Herald Transcript

sdesmalen requested review of this revision.Oct 27 2022, 10:01 AM

Herald added a project: Restricted Project. · View Herald TranscriptOct 27 2022, 10:01 AM

Herald added subscribers: llvm-commits, alextsao1999. · View Herald Transcript

sdesmalen added a parent revision: D136861: [IR] Add LLVM IR support for aarch64_svcount opaque type..Oct 27 2022, 10:01 AM

sdesmalen added a child revision: D136863: [AArch64][SME] Add support for conditional select for svcount..Oct 27 2022, 10:04 AM

sdesmalen added reviewers: efriedma, t.p.northover, aemerson, paulwalker-arm.Oct 27 2022, 10:43 AM

sdesmalen added a subscriber: sagarkulkarni19.

Harbormaster completed remote builds in B194691: Diff 471203.Oct 27 2022, 12:28 PM

sdesmalen mentioned this in D137556: [POC] Clang implementation for AArch64 SME and some SME2 builtins.Nov 7 2022, 7:58 AM

Revision Contents
Changeset List

Path

Size

llvm/

include/

llvm/

Analysis/

ScalarEvolution.h

6 lines

CodeGen/

ValueTypes.h

2 lines

IR/

Type.h

2 lines

Support/

MachineValueType.h

4 lines

lib/

Analysis/

Loads.cpp

2 lines

ScalarEvolution.cpp

16 lines

CodeGen/

CodeGenPrepare.cpp

2 lines

LowLevelType.cpp

2 lines

SelectionDAG/

DAGCombiner.cpp

6 lines

SelectionDAGBuilder.cpp

2 lines

ValueTypes.cpp

6 lines

IR/

DataLayout.cpp

1 line

Support/

LowLevelType.cpp

2 lines

Target/

AArch64/

AArch64CallingConvention.td

6 lines

AArch64ISelLowering.cpp

31 lines

AArch64RegisterInfo.td

2 lines

AArch64SVEInstrInfo.td

2 lines

GISel/

AArch64CallLowering.cpp

11 lines

Transforms/

Scalar/

SROA.cpp

2 lines

test/

CodeGen/

AArch64/

sme-aarch64-svcount-O3.ll

39 lines

sme-aarch64-svcount.ll

117 lines

Transforms/

InstCombine/

AArch64/

sme-svcount.ll

12 lines

SROA/

aarch64-sme-svcount.ll

15 lines

utils/

TableGen/

CodeGenTarget.cpp

1 line

Diff 471203

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llvm/include/llvm/Analysis/ScalarEvolution.h

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llvm/include/llvm/CodeGen/ValueTypes.h

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llvm/include/llvm/IR/Type.h

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llvm/include/llvm/Support/MachineValueType.h

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llvm/lib/Analysis/Loads.cpp

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llvm/lib/Analysis/ScalarEvolution.cpp

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llvm/lib/CodeGen/CodeGenPrepare.cpp

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llvm/lib/CodeGen/LowLevelType.cpp

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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

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llvm/lib/CodeGen/ValueTypes.cpp

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llvm/lib/IR/DataLayout.cpp

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llvm/lib/Support/LowLevelType.cpp

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llvm/lib/Target/AArch64/AArch64CallingConvention.td

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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

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llvm/lib/Target/AArch64/AArch64RegisterInfo.td

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llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

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llvm/lib/Transforms/Scalar/SROA.cpp

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llvm/test/CodeGen/AArch64/sme-aarch64-svcount-O3.ll

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llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll

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llvm/test/Transforms/InstCombine/AArch64/sme-svcount.ll

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llvm/test/Transforms/SROA/aarch64-sme-svcount.ll

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llvm/utils/TableGen/CodeGenTarget.cpp

[AArch64][SME2] Add rudimentary LLVM support for aarch64_svcount.Needs ReviewPublicActions

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Diff Detail

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Revision ContentsChangeset List

Diff 471203

llvm/include/llvm/Analysis/ScalarEvolution.h

llvm/include/llvm/CodeGen/ValueTypes.h

llvm/include/llvm/IR/Type.h

llvm/include/llvm/Support/MachineValueType.h

llvm/lib/Analysis/Loads.cpp

llvm/lib/Analysis/ScalarEvolution.cpp

llvm/lib/CodeGen/CodeGenPrepare.cpp

llvm/lib/CodeGen/LowLevelType.cpp

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

llvm/lib/CodeGen/ValueTypes.cpp

llvm/lib/IR/DataLayout.cpp

llvm/lib/Support/LowLevelType.cpp

llvm/lib/Target/AArch64/AArch64CallingConvention.td

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

llvm/lib/Transforms/Scalar/SROA.cpp

llvm/test/CodeGen/AArch64/sme-aarch64-svcount-O3.ll

llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll

llvm/test/Transforms/InstCombine/AArch64/sme-svcount.ll

llvm/test/Transforms/SROA/aarch64-sme-svcount.ll

llvm/utils/TableGen/CodeGenTarget.cpp

[AArch64][SME2] Add rudimentary LLVM support for aarch64_svcount.
Needs ReviewPublic
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Revision Contents
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