[RISCV] Use vslide1up for inserting bottom element into splat vector

[reames]

Summary

This patch adds a DAG combine to replace a vmv.s.x into a splat vector with a vslide1up instead. This relies on the fact that we can shift a splat without changing any of the active lanes, and vslide1up has separate source and destination vector registers. This allows vslide1up to be tail agnostic whereas vmv.s.x has to be tail undisturbed. This in turn avoids the need for a vsetvli toggle.

One downside to this conversation is that vslide1up has a restriction that the source and destination vector registers can't overlap. This increases register pressure locally, and particularly at very high LMUL, could force an additional spill for a value live over the vslide1up. I think this is net worthwhile, but I'm curious what others think.

There are several TODOs noted in the patch. I plan on implementing the vmv.s.f and narrower element types in a follow up patch. I don't plan to bother with the wider VL one.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9735

Noticed when glancing through other code that I hadn't handled the vmv.v.i case here. Consider that added to the todo list above.

[craig.topper]

The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9735

There is no VMV_V_I_VL. So doesn't this already handle vmv.v.i?

9736

I think the VT match is guaranteed by the rules we have defined for RISCVISD::VSLIDE1UP_VL.

def SDTRVVSlide1 : SDTypeProfile<1, 5, [                                         
  SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>,            
  SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>,         
  SDTCisVT<5, XLenVT>                                                            
]>;

[reames]

In D135794#3854627, @craig.topper wrote:

The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.

Had not considered this point. Would it be reasonable to restrict this to LMUL1 types?

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9735

Well, empirically no. I see examples of vmv.v.i patterns which would match this conceptually, but aren't being caught by this one. Haven't looked into why yet.

[craig.topper]

In D135794#3855633, @reames wrote:

In D135794#3854627, @craig.topper wrote:

The slide1up may be more expensive than vmv.s.x as LMUL increases. The upper elements will get shifted even though they are all the same. Despite vmv.s.x having an LMUL typed result in SelectionDAG and MachineIR it only reads and writes one LMUL==1 vector register.

Had not considered this point. Would it be reasonable to restrict this to LMUL1 types?

I think that's going to depend on the microarchitecture. If the ALU width is less than VLEN bits, a vslide1up could still require more ALU cycles than vmv.s.x.

The cases that replace a vmv and a vmv.s.x are interesting. On an architecture without renaming or move elimination, the vmv might be considered an ALU op.

[reames]

Going to set this aside for now. I'd been thinking of this as a broadly applicable canonicalization to address usage of TU, but as Craig has pointed out, this is likely to be much narrower in scope due to micro-architectural differences, and the lmul=1 restriction. Given that, likely impact isn't enough to justify pushing this right now, will return to it once larger items are addressed.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case ISD::SPLAT_VECTOR: {
     // Only perform this combine on legal MVT types.
     if (!isTypeLegal(VT))
       break;
     if (auto Gather = matchSplatAsGather(N->getOperand(0), VT.getSimpleVT(), N,
                                          DAG, Subtarget))
       return Gather;
     break;
   }
+  case RISCVISD::VMV_S_X_VL: {
+    // TODO: Generalize this for VMV_S_F_VL as well.
+    SDLoc DL(N);
+    MVT VT = N->getSimpleValueType(0);
+    SDValue SrcVec = N->getOperand(0);
+    SDValue VL = N->getOperand(2);
+    // If we have an insert into a splat, we can use a slide1up instead as
+    // sliding the splat doesn't change any of the lanes, and this lets us
+    // avoid a tail undisturbed instruction (and thus a likely vsetvli
+    // toggle).  TODO: Can relax type check to allow any smaller element
+    // type which repeats at the larger type, even with float vs integer
+    // mismatch.  Can also allow a source vector with a larger VL.
+    if (SrcVec.getOpcode() == RISCVISD::VMV_V_X_VL &&
+        SrcVec.getSimpleValueType() == VT && SrcVec.getOperand(2) == VL) {
+      return DAG.getNode(RISCVISD::VSLIDE1UP_VL, DL, VT, DAG.getUNDEF(VT),
+                         SrcVec, N->getOperand(1),
+                         getAllOnesMask(VT, VL, DL, DAG), VL);
+    }
+    break;
+  }
   case RISCVISD::VMV_V_X_VL: {
     // Tail agnostic VMV.V.X only demands the vector element bitwidth from the
     // scalar input.
     unsigned ScalarSize = N->getOperand(1).getValueSizeInBits();
     unsigned EltWidth = N->getValueType(0).getScalarSizeInBits();
     if (ScalarSize > EltWidth && N->getOperand(0).isUndef())
       if (SimplifyDemandedLowBitsHelper(1, EltWidth))
         return SDValue(N, 0);

llvm/test/CodeGen/RISCV/fold-vector-cmp.ll

 ; CHECK-NOV-NEXT:    li a0, 1
 ; CHECK-NOV-NEXT:    ret
 ;
 ; CHECK-V-LABEL: test:
 ; CHECK-V:       # %bb.0:
 ; CHECK-V-NEXT:    lui a1, 524288
 ; CHECK-V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-V-NEXT:    vmv.v.x v8, a1
-; CHECK-V-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
-; CHECK-V-NEXT:    vmv.s.x v8, a0
+; CHECK-V-NEXT:    vslide1up.vx v9, v8, a0
 ; CHECK-V-NEXT:    addiw a0, a1, 2
-; CHECK-V-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-V-NEXT:    vmslt.vx v0, v8, a0
+; CHECK-V-NEXT:    vmslt.vx v0, v9, a0
 ; CHECK-V-NEXT:    vmv.v.i v8, 0
 ; CHECK-V-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-V-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
 ; CHECK-V-NEXT:    vslidedown.vi v8, v8, 1
 ; CHECK-V-NEXT:    vmv.x.s a0, v8
 ; CHECK-V-NEXT:    ret
   %t2 = insertelement <2 x i32> <i32 poison, i32 -2147483648>, i32 %call.i, i64 0
   %t3 = icmp slt <2 x i32> %t2, <i32 -2147483646, i32 -2147483646>
   %t4 = zext <2 x i1> %t3 to <2 x i32>
   %t6 = extractelement <2 x i32> %t4, i64 1
   ret i32 %t6
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll

 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
 ; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
 ; CHECK-NEXT:    vslidedown.vi v9, v8, 1
 ; CHECK-NEXT:    vmv.x.s a0, v9
 ; CHECK-NEXT:    vmv.x.s a1, v8
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmv.v.x v8, a1
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
-; CHECK-NEXT:    vmv.s.x v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vand.vi v8, v8, 1
+; CHECK-NEXT:    vslide1up.vx v9, v8, a0
+; CHECK-NEXT:    vand.vi v8, v9, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
   %res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a)
   ret <2 x i1> %res
 }
 
 define <4 x i1> @reverse_v4i1(<4 x i1> %a) {
 ; CHECK-LABEL: reverse_v4i1:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32ELEN32-LABEL: bitcast_i64_v4i16:
 ; RV32ELEN32:       # %bb.0:
 ; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
-; RV32ELEN32-NEXT:    vmv.v.x v8, a1
-; RV32ELEN32-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    vmv.v.x v9, a1
+; RV32ELEN32-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32ELEN32-NEXT:    ret
 ;
 ; RV64ELEN32-LABEL: bitcast_i64_v4i16:
 ; RV64ELEN32:       # %bb.0:
 ; RV64ELEN32-NEXT:    addi sp, sp, -16
 ; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
 ; RV64ELEN32-NEXT:    sd a0, 8(sp)
 ; RV64ELEN32-NEXT:    addi a0, sp, 8

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
 ;
 ; RV32ELEN32-LABEL: bitcast_i64_v2i32:
 ; RV32ELEN32:       # %bb.0:
 ; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
-; RV32ELEN32-NEXT:    vmv.v.x v8, a1
-; RV32ELEN32-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    vmv.v.x v9, a1
+; RV32ELEN32-NEXT:    vslide1up.vx v8, v9, a0
 ; RV32ELEN32-NEXT:    ret
 ;
 ; RV64ELEN32-LABEL: bitcast_i64_v2i32:
 ; RV64ELEN32:       # %bb.0:
 ; RV64ELEN32-NEXT:    addi sp, sp, -16
 ; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
 ; RV64ELEN32-NEXT:    sd a0, 8(sp)
 ; RV64ELEN32-NEXT:    addi a0, sp, 8

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll

 ; RV32-NEXT:    vfmv.f.s ft2, v8
 ; RV32-NEXT:    feq.d a0, ft2, ft2
 ; RV32-NEXT:    beqz a0, .LBB10_4
 ; RV32-NEXT:  # %bb.3:
 ; RV32-NEXT:    fmax.d ft0, ft2, ft0
 ; RV32-NEXT:    fmin.d ft0, ft0, ft1
 ; RV32-NEXT:    fcvt.w.d a0, ft0, rtz
 ; RV32-NEXT:  .LBB10_4:
-; RV32-NEXT:    vsetivli zero, 2, e8, mf8, tu, ma
-; RV32-NEXT:    vmv.s.x v9, a0
-; RV32-NEXT:    vse8.v v9, (a1)
+; RV32-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; RV32-NEXT:    vslide1up.vx v8, v9, a0
+; RV32-NEXT:    vse8.v v8, (a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: fp2si_v2f64_v2i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vslidedown.vi v9, v8, 1

 ; RV64-NEXT:    vfmv.f.s ft2, v8
 ; RV64-NEXT:    feq.d a0, ft2, ft2
 ; RV64-NEXT:    beqz a0, .LBB10_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    fmax.d ft0, ft2, ft0
 ; RV64-NEXT:    fmin.d ft0, ft0, ft1
 ; RV64-NEXT:    fcvt.l.d a0, ft0, rtz
 ; RV64-NEXT:  .LBB10_4:
-; RV64-NEXT:    vsetivli zero, 2, e8, mf8, tu, ma
-; RV64-NEXT:    vmv.s.x v9, a0
-; RV64-NEXT:    vse8.v v9, (a1)
+; RV64-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
+; RV64-NEXT:    vslide1up.vx v8, v9, a0
+; RV64-NEXT:    vse8.v v8, (a1)
 ; RV64-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %d = call <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double> %a)
   store <2 x i8> %d, <2 x i8>* %y
   ret void
 }
 declare <2 x i8> @llvm.fptosi.sat.v2i8.v2f64(<2 x double>)
 

 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV32-NEXT:    vslidedown.vi v8, v8, 1
 ; RV32-NEXT:    vfmv.f.s ft1, v8
 ; RV32-NEXT:    fmax.d ft1, ft1, ft2
 ; RV32-NEXT:    fmin.d ft0, ft1, ft0
 ; RV32-NEXT:    fcvt.wu.d a2, ft0, rtz
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; RV32-NEXT:    vmv.v.x v8, a2
-; RV32-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
-; RV32-NEXT:    vmv.s.x v8, a0
-; RV32-NEXT:    vse8.v v8, (a1)
+; RV32-NEXT:    vslide1up.vx v9, v8, a0
+; RV32-NEXT:    vse8.v v9, (a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: fp2ui_v2f64_v2i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV64-NEXT:    fld ft0, %lo(.LCPI11_0)(a0)
 ; RV64-NEXT:    vfmv.f.s ft1, v8
 ; RV64-NEXT:    fmv.d.x ft2, zero
 ; RV64-NEXT:    fmax.d ft1, ft1, ft2
 ; RV64-NEXT:    fmin.d ft1, ft1, ft0
 ; RV64-NEXT:    fcvt.lu.d a0, ft1, rtz
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; RV64-NEXT:    vslidedown.vi v8, v8, 1
 ; RV64-NEXT:    vfmv.f.s ft1, v8
 ; RV64-NEXT:    fmax.d ft1, ft1, ft2
 ; RV64-NEXT:    fmin.d ft0, ft1, ft0
 ; RV64-NEXT:    fcvt.lu.d a2, ft0, rtz
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; RV64-NEXT:    vmv.v.x v8, a2
-; RV64-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
-; RV64-NEXT:    vmv.s.x v8, a0
-; RV64-NEXT:    vse8.v v8, (a1)
+; RV64-NEXT:    vslide1up.vx v9, v8, a0
+; RV64-NEXT:    vse8.v v9, (a1)
 ; RV64-NEXT:    ret
   %a = load <2 x double>, <2 x double>* %x
   %d = call <2 x i8> @llvm.fptoui.sat.v2i8.v2f64(<2 x double> %a)
   store <2 x i8> %d, <2 x i8>* %y
   ret void
 }
 declare <2 x i8> @llvm.fptoui.sat.v2i8.v2f64(<2 x double>)
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

 ; RV32-LABEL: insertelt_v3i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    lw a3, 16(a0)
 ; RV32-NEXT:    addi a4, a0, 20
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; RV32-NEXT:    vlse32.v v10, (a4), zero
-; RV32-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32-NEXT:    vmv.s.x v10, a3
+; RV32-NEXT:    vslide1up.vx v12, v10, a3
 ; RV32-NEXT:    vsetvli zero, zero, e64, m2, tu, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 2
+; RV32-NEXT:    vslideup.vi v8, v12, 2
 ; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
 ; RV32-NEXT:    vmv.v.i v10, 0
 ; RV32-NEXT:    vslide1up.vx v12, v10, a2
 ; RV32-NEXT:    vslide1up.vx v10, v12, a1
 ; RV32-NEXT:    vsetivli zero, 3, e64, m2, tu, ma
 ; RV32-NEXT:    vslideup.vi v8, v10, 2
 ; RV32-NEXT:    sw a1, 16(a0)
 ; RV32-NEXT:    sw a2, 20(a0)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: buildvec_dominant0_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a1, %hi(.LCPI20_0)
 ; RV64-NEXT:    ld a1, %lo(.LCPI20_0)(a1)
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, -1
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; RV64-NEXT:    vmv.s.x v8, a1
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    vslide1up.vx v9, v8, a1
+; RV64-NEXT:    vse64.v v9, (a0)
 ; RV64-NEXT:    ret
   store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
   ret void
 }
 
 define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize {
 ; RV32-LABEL: buildvec_dominant1_optsize_v2i32:
 ; RV32:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
   ret <8 x i8> %shuff
 }
 
 define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
 ; CHECK-LABEL: splat_ve4_ins_i0ve2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.i v10, 4
+; CHECK-NEXT:    vmv.v.i v9, 4
 ; CHECK-NEXT:    li a0, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, tu, ma
-; CHECK-NEXT:    vmv.s.x v10, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vslide1up.vx v10, v9, a0
 ; CHECK-NEXT:    vrgather.vv v9, v8, v10
 ; CHECK-NEXT:    vmv1r.v v8, v9
 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 2, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
   ret <8 x i8> %shuff
 }
 
 define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {

 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
   ret <8 x i8> %shuff
 }
 
 define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
 ; CHECK-LABEL: splat_ve2_we0_ins_i0ve4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.i v11, 2
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.v.i v10, 2
 ; CHECK-NEXT:    li a0, 4
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, tu, ma
-; CHECK-NEXT:    vmv.s.x v11, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, mu
+; CHECK-NEXT:    vslide1up.vx v11, v10, a0
 ; CHECK-NEXT:    li a0, 66
 ; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vv v10, v8, v11
 ; CHECK-NEXT:    vrgather.vi v10, v9, 0, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
   ret <8 x i8> %shuff

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 ; CHECK-NEXT:    vmv.s.x v0, a1
 ; CHECK-NEXT:    vmv.v.i v10, 3
 ; CHECK-NEXT:    vmerge.vim v10, v10, 2, v0
 ; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vi v10, v9, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    vmv.v.i v11, 0
 ; CHECK-NEXT:    lui a1, 1048568
-; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, ma
-; CHECK-NEXT:    vmv.v.i v12, 0
-; CHECK-NEXT:    vmv.s.x v12, a1
+; CHECK-NEXT:    vslide1up.vx v12, v11, a1
 ; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, ma
 ; CHECK-NEXT:    vslideup.vi v11, v9, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
 ; CHECK-NEXT:    lui a1, %hi(.LCPI53_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI53_0)
 ; CHECK-NEXT:    vle16.v v9, (a1)
 ; CHECK-NEXT:    vsrl.vv v11, v8, v11
 ; CHECK-NEXT:    vmulhu.vv v9, v11, v9

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV64-NEXT:    lui a1, %hi(.LCPI55_0)
 ; RV64-NEXT:    addi a1, a1, %lo(.LCPI55_0)
 ; RV64-NEXT:    vlse64.v v8, (a1), zero
 ; RV64-NEXT:    lui a1, %hi(.LCPI55_1)
 ; RV64-NEXT:    ld a1, %lo(.LCPI55_1)(a1)
 ; RV64-NEXT:    vle64.v v9, (a0)
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; RV64-NEXT:    vmv.s.x v8, a1
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; RV64-NEXT:    vmulhu.vv v8, v9, v8
+; RV64-NEXT:    vslide1up.vx v10, v8, a1
+; RV64-NEXT:    vmulhu.vv v8, v9, v10
 ; RV64-NEXT:    vid.v v9
 ; RV64-NEXT:    vadd.vi v9, v9, 1
 ; RV64-NEXT:    vsrl.vv v8, v8, v9
 ; RV64-NEXT:    vse64.v v8, (a0)
 ; RV64-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = udiv <2 x i64> %a, <i64 3, i64 5>
   store <2 x i64> %b, <2 x i64>* %x

 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV32-NEXT:    vle64.v v8, (a0)
 ; RV32-NEXT:    lui a1, 349525
 ; RV32-NEXT:    addi a2, a1, 1365
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.x v9, a2
 ; RV32-NEXT:    addi a1, a1, 1366
-; RV32-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32-NEXT:    vmv.s.x v9, a1
+; RV32-NEXT:    vslide1up.vx v10, v9, a1
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT:    vmulh.vv v9, v8, v9
+; RV32-NEXT:    vmulh.vv v9, v8, v10
 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; RV32-NEXT:    vid.v v10
 ; RV32-NEXT:    vsrl.vi v10, v10, 1
 ; RV32-NEXT:    vrsub.vi v10, v10, 0
 ; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV32-NEXT:    vmadd.vv v10, v8, v9
 ; RV32-NEXT:    li a1, 1
 ; RV32-NEXT:    vmv.s.x v8, a1

 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
 ; RV64-NEXT:    lui a1, %hi(.LCPI59_0)
 ; RV64-NEXT:    addi a1, a1, %lo(.LCPI59_0)
 ; RV64-NEXT:    vlse64.v v8, (a1), zero
 ; RV64-NEXT:    lui a1, %hi(.LCPI59_1)
 ; RV64-NEXT:    ld a1, %lo(.LCPI59_1)(a1)
 ; RV64-NEXT:    vle64.v v9, (a0)
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; RV64-NEXT:    vmv.s.x v8, a1
-; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; RV64-NEXT:    vmulh.vv v8, v9, v8
+; RV64-NEXT:    vslide1up.vx v10, v8, a1
+; RV64-NEXT:    vmulh.vv v8, v9, v10
 ; RV64-NEXT:    vid.v v10
 ; RV64-NEXT:    vrsub.vi v11, v10, 0
 ; RV64-NEXT:    vmadd.vv v11, v9, v8
 ; RV64-NEXT:    li a1, 63
 ; RV64-NEXT:    vsrl.vx v8, v11, a1
 ; RV64-NEXT:    vsra.vv v9, v11, v10
 ; RV64-NEXT:    vadd.vv v8, v9, v8
 ; RV64-NEXT:    vse64.v v8, (a0)

 ; LMULMAX1-RV32-NEXT:    vdivu.vv v8, v8, v10
 ; LMULMAX1-RV32-NEXT:    vse64.v v8, (a0)
 ; LMULMAX1-RV32-NEXT:    vse64.v v9, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: mulhu_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle64.v v8, (a0)
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
-; LMULMAX1-RV64-NEXT:    vle64.v v9, (a1)
-; LMULMAX1-RV64-NEXT:    vmv.v.i v10, 0
+; LMULMAX1-RV64-NEXT:    vle64.v v8, (a1)
+; LMULMAX1-RV64-NEXT:    vmv.v.i v9, 0
 ; LMULMAX1-RV64-NEXT:    li a2, -1
+; LMULMAX1-RV64-NEXT:    lui a3, %hi(.LCPI156_0)
+; LMULMAX1-RV64-NEXT:    addi a3, a3, %lo(.LCPI156_0)
+; LMULMAX1-RV64-NEXT:    vlse64.v v10, (a3), zero
+; LMULMAX1-RV64-NEXT:    lui a3, %hi(.LCPI156_1)
+; LMULMAX1-RV64-NEXT:    ld a3, %lo(.LCPI156_1)(a3)
 ; LMULMAX1-RV64-NEXT:    slli a2, a2, 63
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; LMULMAX1-RV64-NEXT:    vmv.s.x v10, a2
-; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI156_0)
-; LMULMAX1-RV64-NEXT:    addi a2, a2, %lo(.LCPI156_0)
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vlse64.v v11, (a2), zero
-; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI156_1)
-; LMULMAX1-RV64-NEXT:    ld a2, %lo(.LCPI156_1)(a2)
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; LMULMAX1-RV64-NEXT:    vmv.s.x v11, a2
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vmulhu.vv v11, v9, v11
-; LMULMAX1-RV64-NEXT:    vsub.vv v9, v9, v11
-; LMULMAX1-RV64-NEXT:    vmulhu.vv v9, v9, v10
-; LMULMAX1-RV64-NEXT:    vadd.vv v9, v9, v11
-; LMULMAX1-RV64-NEXT:    vid.v v10
+; LMULMAX1-RV64-NEXT:    vslide1up.vx v11, v9, a2
+; LMULMAX1-RV64-NEXT:    vle64.v v9, (a0)
+; LMULMAX1-RV64-NEXT:    vslide1up.vx v12, v10, a3
+; LMULMAX1-RV64-NEXT:    vmulhu.vv v10, v8, v12
+; LMULMAX1-RV64-NEXT:    vsub.vv v8, v8, v10
+; LMULMAX1-RV64-NEXT:    vmulhu.vv v8, v8, v11
+; LMULMAX1-RV64-NEXT:    vadd.vv v8, v8, v10
 ; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI156_2)
 ; LMULMAX1-RV64-NEXT:    addi a2, a2, %lo(.LCPI156_2)
-; LMULMAX1-RV64-NEXT:    vlse64.v v11, (a2), zero
+; LMULMAX1-RV64-NEXT:    vlse64.v v10, (a2), zero
 ; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI156_3)
 ; LMULMAX1-RV64-NEXT:    ld a2, %lo(.LCPI156_3)(a2)
-; LMULMAX1-RV64-NEXT:    vadd.vi v12, v10, 2
-; LMULMAX1-RV64-NEXT:    vsrl.vv v9, v9, v12
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; LMULMAX1-RV64-NEXT:    vmv.s.x v11, a2
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vmulhu.vv v8, v8, v11
-; LMULMAX1-RV64-NEXT:    vadd.vi v10, v10, 1
-; LMULMAX1-RV64-NEXT:    vsrl.vv v8, v8, v10
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vse64.v v9, (a1)
+; LMULMAX1-RV64-NEXT:    vid.v v11
+; LMULMAX1-RV64-NEXT:    vadd.vi v12, v11, 2
+; LMULMAX1-RV64-NEXT:    vsrl.vv v8, v8, v12
+; LMULMAX1-RV64-NEXT:    vslide1up.vx v12, v10, a2
+; LMULMAX1-RV64-NEXT:    vmulhu.vv v9, v9, v12
+; LMULMAX1-RV64-NEXT:    vadd.vi v10, v11, 1
+; LMULMAX1-RV64-NEXT:    vsrl.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT:    vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT:    vse64.v v8, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 
 define void @mulhs_v32i8(<32 x i8>* %x) {

 ; LMULMAX1-RV32-NEXT:    vdiv.vv v8, v8, v10
 ; LMULMAX1-RV32-NEXT:    vse64.v v8, (a0)
 ; LMULMAX1-RV32-NEXT:    vse64.v v9, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: mulhs_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vle64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI160_0)
-; LMULMAX1-RV64-NEXT:    addi a1, a1, %lo(.LCPI160_0)
-; LMULMAX1-RV64-NEXT:    vlse64.v v9, (a1), zero
-; LMULMAX1-RV64-NEXT:    lui a1, %hi(.LCPI160_1)
-; LMULMAX1-RV64-NEXT:    ld a1, %lo(.LCPI160_1)(a1)
-; LMULMAX1-RV64-NEXT:    addi a2, a0, 16
-; LMULMAX1-RV64-NEXT:    vle64.v v10, (a2)
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, tu, ma
-; LMULMAX1-RV64-NEXT:    vmv.s.x v9, a1
-; LMULMAX1-RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; LMULMAX1-RV64-NEXT:    vmulh.vv v11, v10, v9
+; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
+; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI160_0)
+; LMULMAX1-RV64-NEXT:    addi a2, a2, %lo(.LCPI160_0)
+; LMULMAX1-RV64-NEXT:    vlse64.v v8, (a2), zero
+; LMULMAX1-RV64-NEXT:    lui a2, %hi(.LCPI160_1)
+; LMULMAX1-RV64-NEXT:    ld a2, %lo(.LCPI160_1)(a2)
+; LMULMAX1-RV64-NEXT:    vle64.v v9, (a1)
+; LMULMAX1-RV64-NEXT:    vle64.v v10, (a0)
+; LMULMAX1-RV64-NEXT:    vslide1up.vx v11, v8, a2
+; LMULMAX1-RV64-NEXT:    vmulh.vv v8, v9, v11
 ; LMULMAX1-RV64-NEXT:    vid.v v12
 ; LMULMAX1-RV64-NEXT:    vrsub.vi v13, v12, 0
-; LMULMAX1-RV64-NEXT:    vmacc.vv v11, v13, v10
-; LMULMAX1-RV64-NEXT:    li a1, 63
-; LMULMAX1-RV64-NEXT:    vsrl.vx v10, v11, a1
-; LMULMAX1-RV64-NEXT:    vsra.vv v11, v11, v12
-; LMULMAX1-RV64-NEXT:    vadd.vv v10, v11, v10
-; LMULMAX1-RV64-NEXT:    vmulh.vv v9, v8, v9
-; LMULMAX1-RV64-NEXT:    vmacc.vv v9, v8, v13
-; LMULMAX1-RV64-NEXT:    vsrl.vx v8, v9, a1
+; LMULMAX1-RV64-NEXT:    vmacc.vv v8, v13, v9
+; LMULMAX1-RV64-NEXT:    li a2, 63
+; LMULMAX1-RV64-NEXT:    vsrl.vx v9, v8, a2
+; LMULMAX1-RV64-NEXT:    vsra.vv v8, v8, v12
+; LMULMAX1-RV64-NEXT:    vadd.vv v8, v8, v9
+; LMULMAX1-RV64-NEXT:    vmulh.vv v9, v10, v11
+; LMULMAX1-RV64-NEXT:    vmacc.vv v9, v10, v13
+; LMULMAX1-RV64-NEXT:    vsrl.vx v10, v9, a2
 ; LMULMAX1-RV64-NEXT:    vsra.vv v9, v9, v12
-; LMULMAX1-RV64-NEXT:    vadd.vv v8, v9, v8
-; LMULMAX1-RV64-NEXT:    vse64.v v8, (a0)
-; LMULMAX1-RV64-NEXT:    vse64.v v10, (a2)
+; LMULMAX1-RV64-NEXT:    vadd.vv v9, v9, v10
+; LMULMAX1-RV64-NEXT:    vse64.v v9, (a0)
+; LMULMAX1-RV64-NEXT:    vse64.v v8, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 
 define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

; ZVE32F-NEXT:    ret
   ret <1 x i1> %1
 }
 
 define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {
 ; CHECK-LABEL: buildvec_mask_nonconst_v2i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmv.v.x v8, a1
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
-; CHECK-NEXT:    vmv.s.x v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vand.vi v8, v8, 1
+; CHECK-NEXT:    vslide1up.vx v9, v8, a0
+; CHECK-NEXT:    vand.vi v8, v9, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
 ;
 ; ZVE32F-LABEL: buildvec_mask_nonconst_v2i1:
 ; ZVE32F:       # %bb.0:
 ; ZVE32F-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
 ; ZVE32F-NEXT:    vmv.v.x v8, a1
-; ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, tu, ma
-; ZVE32F-NEXT:    vmv.s.x v8, a0
-; ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; ZVE32F-NEXT:    vand.vi v8, v8, 1
+; ZVE32F-NEXT:    vslide1up.vx v9, v8, a0
+; ZVE32F-NEXT:    vand.vi v8, v9, 1
 ; ZVE32F-NEXT:    vmsne.vi v0, v8, 0
 ; ZVE32F-NEXT:    ret
   %1 = insertelement <2 x i1> poison, i1 %x, i32 0
   %2 = insertelement <2 x i1> %1,  i1 %y, i32 1
   ret <2 x i1> %2
 }
 
 ; FIXME: optsize isn't smaller than the code above

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

 ; RV64-NEXT:    ret
 ;
 ; RV32ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32:
 ; RV32ZVE32F:       # %bb.0:
 ; RV32ZVE32F-NEXT:    lw a1, 0(a0)
 ; RV32ZVE32F-NEXT:    addi a0, a0, 8
 ; RV32ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; RV32ZVE32F-NEXT:    vlse32.v v9, (a0), zero
-; RV32ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV32ZVE32F-NEXT:    vmv.s.x v9, a1
-; RV32ZVE32F-NEXT:    vsoxei32.v v9, (zero), v8, v0.t
+; RV32ZVE32F-NEXT:    vslide1up.vx v10, v9, a1
+; RV32ZVE32F-NEXT:    vsoxei32.v v10, (zero), v8, v0.t
 ; RV32ZVE32F-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mscatter_v2i64_truncstore_v2i32:
 ; RV64ZVE32F:       # %bb.0:
 ; RV64ZVE32F-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
-; RV64ZVE32F-NEXT:    vmv.v.x v8, a1
-; RV64ZVE32F-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; RV64ZVE32F-NEXT:    vmv.s.x v8, a0
+; RV64ZVE32F-NEXT:    vmv.v.x v9, a1
+; RV64ZVE32F-NEXT:    vslide1up.vx v8, v9, a0
 ; RV64ZVE32F-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
 ; RV64ZVE32F-NEXT:    vmv.x.s a0, v0
 ; RV64ZVE32F-NEXT:    andi a1, a0, 1
 ; RV64ZVE32F-NEXT:    bnez a1, .LBB24_3
 ; RV64ZVE32F-NEXT:  # %bb.1: # %else
 ; RV64ZVE32F-NEXT:    andi a0, a0, 2
 ; RV64ZVE32F-NEXT:    bnez a0, .LBB24_4
 ; RV64ZVE32F-NEXT:  .LBB24_2: # %else2

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32MV-NEXT:    or a1, a1, a2
 ; RV32MV-NEXT:    andi a1, a1, 2047
 ; RV32MV-NEXT:    sh a1, 12(sp)
 ; RV32MV-NEXT:    addi a1, sp, 8
 ; RV32MV-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; RV32MV-NEXT:    vle16.v v8, (a1)
 ; RV32MV-NEXT:    vmv.v.i v9, 10
 ; RV32MV-NEXT:    li a1, 9
-; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, ma
-; RV32MV-NEXT:    vmv.s.x v9, a1
-; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
-; RV32MV-NEXT:    lui a1, %hi(.LCPI4_0)
-; RV32MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
-; RV32MV-NEXT:    vle16.v v10, (a1)
-; RV32MV-NEXT:    vid.v v11
-; RV32MV-NEXT:    vsub.vv v8, v8, v11
+; RV32MV-NEXT:    lui a2, %hi(.LCPI4_0)
+; RV32MV-NEXT:    addi a2, a2, %lo(.LCPI4_0)
+; RV32MV-NEXT:    vle16.v v10, (a2)
+; RV32MV-NEXT:    vslide1up.vx v11, v9, a1
+; RV32MV-NEXT:    vid.v v9
+; RV32MV-NEXT:    vsub.vv v8, v8, v9
 ; RV32MV-NEXT:    vmul.vv v8, v8, v10
-; RV32MV-NEXT:    vadd.vv v10, v8, v8
-; RV32MV-NEXT:    vsll.vv v9, v10, v9
+; RV32MV-NEXT:    vadd.vv v9, v8, v8
+; RV32MV-NEXT:    vsll.vv v9, v9, v11
 ; RV32MV-NEXT:    vmv.v.i v10, 0
 ; RV32MV-NEXT:    li a1, 1
-; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, ma
-; RV32MV-NEXT:    vmv1r.v v11, v10
-; RV32MV-NEXT:    vmv.s.x v11, a1
+; RV32MV-NEXT:    vslide1up.vx v11, v10, a1
 ; RV32MV-NEXT:    li a1, 2047
-; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; RV32MV-NEXT:    vand.vx v8, v8, a1
 ; RV32MV-NEXT:    lui a2, %hi(.LCPI4_1)
 ; RV32MV-NEXT:    addi a2, a2, %lo(.LCPI4_1)
 ; RV32MV-NEXT:    vle16.v v12, (a2)
 ; RV32MV-NEXT:    vsrl.vv v8, v8, v11
 ; RV32MV-NEXT:    vor.vv v8, v8, v9
 ; RV32MV-NEXT:    vand.vx v8, v8, a1
 ; RV32MV-NEXT:    vmsltu.vv v0, v12, v8

 ; RV64MV-NEXT:    slli a1, a1, 42
 ; RV64MV-NEXT:    srli a1, a1, 53
 ; RV64MV-NEXT:    sh a1, 10(sp)
 ; RV64MV-NEXT:    addi a1, sp, 8
 ; RV64MV-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; RV64MV-NEXT:    vle16.v v8, (a1)
 ; RV64MV-NEXT:    vmv.v.i v9, 10
 ; RV64MV-NEXT:    li a1, 9
-; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, ma
-; RV64MV-NEXT:    vmv.s.x v9, a1
-; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
-; RV64MV-NEXT:    lui a1, %hi(.LCPI4_0)
-; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
-; RV64MV-NEXT:    vle16.v v10, (a1)
-; RV64MV-NEXT:    vid.v v11
-; RV64MV-NEXT:    vsub.vv v8, v8, v11
+; RV64MV-NEXT:    lui a2, %hi(.LCPI4_0)
+; RV64MV-NEXT:    addi a2, a2, %lo(.LCPI4_0)
+; RV64MV-NEXT:    vle16.v v10, (a2)
+; RV64MV-NEXT:    vslide1up.vx v11, v9, a1
+; RV64MV-NEXT:    vid.v v9
+; RV64MV-NEXT:    vsub.vv v8, v8, v9
 ; RV64MV-NEXT:    vmul.vv v8, v8, v10
-; RV64MV-NEXT:    vadd.vv v10, v8, v8
-; RV64MV-NEXT:    vsll.vv v9, v10, v9
+; RV64MV-NEXT:    vadd.vv v9, v8, v8
+; RV64MV-NEXT:    vsll.vv v9, v9, v11
 ; RV64MV-NEXT:    vmv.v.i v10, 0
 ; RV64MV-NEXT:    li a1, 1
-; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, ma
-; RV64MV-NEXT:    vmv1r.v v11, v10
-; RV64MV-NEXT:    vmv.s.x v11, a1
+; RV64MV-NEXT:    vslide1up.vx v11, v10, a1
 ; RV64MV-NEXT:    li a1, 2047
-; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
 ; RV64MV-NEXT:    vand.vx v8, v8, a1
 ; RV64MV-NEXT:    lui a2, %hi(.LCPI4_1)
 ; RV64MV-NEXT:    addi a2, a2, %lo(.LCPI4_1)
 ; RV64MV-NEXT:    vle16.v v12, (a2)
 ; RV64MV-NEXT:    vsrl.vv v8, v8, v11
 ; RV64MV-NEXT:    vor.vv v8, v8, v9
 ; RV64MV-NEXT:    vand.vx v8, v8, a1
 ; RV64MV-NEXT:    vmsltu.vv v0, v12, v8