[VP] Rename SDNode of vp.fptrunc from VP_FP_ROUND to VP_FP_TRUNCATE

[eopXD]

Summary

The current naming is asymmetric to naming of vp.trunc (VP_TRUNCATE).
It may also become easily mistaken when we have vp.round in the future.

[craig.topper]

The name was chosen to be consistent with ISD::FP_ROUND. There is no ISD::FP_TRUNCATE. The naming issue you mention already exists for ISD::FP_ROUND and ISD::FROUND. Consistency with non-VP opcodes is more important.

[eopXD]

I see. This revision is not needed then.

llvm/include/llvm/IR/VPIntrinsics.def

 
 // llvm.vp.uitofp(x,mask,vlen)
 HELPER_REGISTER_FP_CAST_VP(uitofp, VP_UINT_TO_FP, UIToFP, 1)
 
 // llvm.vp.sitofp(x,mask,vlen)
 HELPER_REGISTER_FP_CAST_VP(sitofp, VP_SINT_TO_FP, SIToFP, 1)
 
 // llvm.vp.fptrunc(x,mask,vlen)
-HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, 1)
+HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_TRUNCATE, FPTrunc, 1)
 
 // llvm.vp.fpext(x,mask,vlen)
 HELPER_REGISTER_FP_CAST_VP(fpext, VP_FP_EXTEND, FPExt, 0)
 
 #undef HELPER_REGISTER_FP_CAST_VP
 
 // Specialized helper macro for integer type conversions.
 // <operation>(%x, %mask, %evl).

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::FLOG2:
   case ISD::FNEARBYINT:
   case ISD::FNEG: case ISD::VP_FNEG:
   case ISD::FREEZE:
   case ISD::ARITH_FENCE:
   case ISD::FP_EXTEND:
   case ISD::VP_FP_EXTEND:
   case ISD::FP_ROUND:
-  case ISD::VP_FP_ROUND:
+  case ISD::VP_FP_TRUNCATE:
   case ISD::FP_TO_SINT:
   case ISD::VP_FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::VP_FP_TO_UINT:
   case ISD::FRINT:
   case ISD::FROUND:
   case ISD::FROUNDEVEN:
   case ISD::FSIN:
#endif
   case ISD::INSERT_SUBVECTOR:  Res = SplitVecOp_INSERT_SUBVECTOR(N, OpNo); break;
   case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
   case ISD::CONCAT_VECTORS:    Res = SplitVecOp_CONCAT_VECTORS(N); break;
   case ISD::VP_TRUNCATE:
   case ISD::TRUNCATE:
     Res = SplitVecOp_TruncateHelper(N);
     break;
   case ISD::STRICT_FP_ROUND:
-  case ISD::VP_FP_ROUND:
+  case ISD::VP_FP_TRUNCATE:
   case ISD::FP_ROUND:          Res = SplitVecOp_FP_ROUND(N); break;
   case ISD::FCOPYSIGN:         Res = SplitVecOp_FCOPYSIGN(N); break;
   case ISD::STORE:
     Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
     break;
   case ISD::VP_STORE:
     Res = SplitVecOp_VP_STORE(cast<VPStoreSDNode>(N), OpNo);
     break;
Lo = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other },
                      { N->getOperand(0), Lo, N->getOperand(2) });
     Hi = DAG.getNode(N->getOpcode(), DL, { OutVT, MVT::Other }, 
                      { N->getOperand(0), Hi, N->getOperand(2) });
     // Legalize the chain result - switch anything that used the old chain to
     // use the new one.
     SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 
                                    Lo.getValue(1), Hi.getValue(1));
     ReplaceValueWith(SDValue(N, 1), NewChain);
-  } else if (N->getOpcode() == ISD::VP_FP_ROUND) {
+  } else if (N->getOpcode() == ISD::VP_FP_TRUNCATE) {
     SDValue MaskLo, MaskHi, EVLLo, EVLHi;
     std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1));
     std::tie(EVLLo, EVLHi) =
         DAG.SplitEVL(N->getOperand(2), N->getValueType(0), DL);
-    Lo = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Lo, MaskLo, EVLLo);
-    Hi = DAG.getNode(ISD::VP_FP_ROUND, DL, OutVT, Hi, MaskHi, EVLHi);
+    Lo = DAG.getNode(ISD::VP_FP_TRUNCATE, DL, OutVT, Lo, MaskLo, EVLLo);
+    Hi = DAG.getNode(ISD::VP_FP_TRUNCATE, DL, OutVT, Hi, MaskHi, EVLHi);
   } else {
     Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
     Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
   }
 
   return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
 }
 
#include "llvm/IR/ConstrainedOps.def"
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
     break;
 
   case ISD::ANY_EXTEND:
   case ISD::FP_EXTEND:
   case ISD::VP_FP_EXTEND:
   case ISD::FP_ROUND:
-  case ISD::VP_FP_ROUND:
+  case ISD::VP_FP_TRUNCATE:
   case ISD::FP_TO_SINT:
   case ISD::VP_FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::VP_FP_TO_UINT:
   case ISD::SIGN_EXTEND:
   case ISD::VP_SIGN_EXTEND:
   case ISD::SINT_TO_FP:
   case ISD::VP_SINT_TO_FP:

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
                              int64_t ExtTrueVal) const;
   SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerVPFPExtendOrTruncateOp(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static const unsigned IntegerVPOps[] = {
         ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE};
 
     static const unsigned FloatingPointVPOps[] = {
         ISD::VP_FADD,        ISD::VP_FSUB,        ISD::VP_FMUL,
         ISD::VP_FDIV,        ISD::VP_FNEG,        ISD::VP_FABS,
         ISD::VP_FMA,         ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
         ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_MERGE,
         ISD::VP_SELECT,      ISD::VP_SINT_TO_FP,  ISD::VP_UINT_TO_FP,
-        ISD::VP_SETCC,       ISD::VP_FP_ROUND,    ISD::VP_FP_EXTEND};
+        ISD::VP_SETCC,       ISD::VP_FP_TRUNCATE, ISD::VP_FP_EXTEND};
 
     static const unsigned IntegerVecReduceOps[] = {
         ISD::VECREDUCE_ADD,  ISD::VECREDUCE_AND,  ISD::VECREDUCE_OR,
         ISD::VECREDUCE_XOR,  ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN,
         ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN};
 
     static const unsigned FloatingPointVecReduceOps[] = {
         ISD::VECREDUCE_FADD, ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_FMIN,
if (Op.getValueType() == MVT::f16 && Subtarget.is64Bit() &&
                          DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
     }
     return SDValue();
   }
   case ISD::FP_EXTEND:
   case ISD::FP_ROUND:
     if (!Op.getValueType().isVector())
       return Op;
-    return lowerVectorFPExtendOrRoundLike(Op, DAG);
+    return lowerVPFPExtendOrTruncateOp(Op, DAG);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP: {
     // RVV can only do fp<->int conversions to types half/double the size as
     // the source. We custom-lower any conversions that do two hops into
     // sequences.
     MVT VT = Op.getSimpleValueType();
if (Op.getOperand(0).getSimpleValueType().getVectorElementType() == MVT::i1)
       return lowerVPExtMaskOp(Op, DAG);
     return lowerVPOp(Op, DAG,
                      Op.getOpcode() == ISD::VP_SIGN_EXTEND
                          ? RISCVISD::VSEXT_VL
                          : RISCVISD::VZEXT_VL);
   case ISD::VP_TRUNCATE:
     return lowerVectorTruncLike(Op, DAG);
   case ISD::VP_FP_EXTEND:
-  case ISD::VP_FP_ROUND:
-    return lowerVectorFPExtendOrRoundLike(Op, DAG);
+  case ISD::VP_FP_TRUNCATE:
+    return lowerVPFPExtendOrTruncateOp(Op, DAG);
   case ISD::VP_FP_TO_SINT:
     return lowerVPFPIntConvOp(Op, DAG, RISCVISD::VFCVT_RTZ_X_F_VL);
   case ISD::VP_FP_TO_UINT:
     return lowerVPFPIntConvOp(Op, DAG, RISCVISD::VFCVT_RTZ_XU_F_VL);
   case ISD::VP_SINT_TO_FP:
     return lowerVPFPIntConvOp(Op, DAG, RISCVISD::SINT_TO_FP_VL);
   case ISD::VP_UINT_TO_FP:
     return lowerVPFPIntConvOp(Op, DAG, RISCVISD::UINT_TO_FP_VL);
SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
 
   if (SrcVT.isFixedLengthVector())
     Result = convertFromScalableVector(VT, Result, DAG, Subtarget);
 
   return Result;
 }
 
 SDValue
-RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
-                                                    SelectionDAG &DAG) const {
-  bool IsVP =
-      Op.getOpcode() == ISD::VP_FP_ROUND || Op.getOpcode() == ISD::VP_FP_EXTEND;
+RISCVTargetLowering::lowerVPFPExtendOrTruncateOp(SDValue Op,
+  bool IsVP = Op.getOpcode() == ISD::VP_FP_TRUNCATE ||
+              Op.getOpcode() == ISD::VP_FP_EXTEND;
   bool IsExtend =
       Op.getOpcode() == ISD::VP_FP_EXTEND || Op.getOpcode() == ISD::FP_EXTEND;
   // RVV can only do truncate fp to types half the size as the source. We
   // custom-lower f64->f16 rounds via RVV's round-to-odd float
   // conversion instruction.
   SDLoc DL(Op);
   MVT VT = Op.getSimpleValueType();