[RISCV]Preserve (and X, 0xffff) in targetShrinkDemandedConstant

[liaolucy]

Summary

shrinkdemandedconstant does some optimizations, but is not very friendly to riscv, targetShrinkDemandedConstant to limit the damage.

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10044–10048

I'm actually not sure if there are side effects.

I also implemented a version in RISCV DAGcombine, maybe it can be used as an alternative

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10044–10048

What does the DAGCombine do? When it get in an infinite loop with shrinkDemandedConstant?

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10044–10048

Current implementation:

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1d5cd3ecd8ea..a6a764c2032b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8630,6 +8630,25 @@ static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     if (SDValue V = combineDeMorganOfBoolean(N, DAG))
       return V;

+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+  // fold (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 
+  auto *C1 = dyn_cast<ConstantSDNode>(N1);
+  if (C1 && N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
+    if (auto *C2 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+      const APInt &ImmC1 = C1->getAPIntValue();
+      const APInt &ImmC2 = C2->getAPIntValue();
+      const APInt &ImmC = ImmC1|ImmC2;
+      unsigned MinSignedBits = ImmC.getMinSignedBits();
+      if (MinSignedBits <= 12) {
+      EVT VT = N->getValueType(0);
+      SDValue NewOR = DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
+      SDValue NewN1 = DAG.getConstant(ImmC1|ImmC2, SDLoc(N), VT);
+      return DAG.getNode(ISD::AND, SDLoc(N), VT, NewOR, NewN1);
+      }
+    } 
+  }
+
   // fold (or (select cond, 0, y), x) ->
   //      (select cond, x, (or x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::targetShrinkDemandedConstant(
 
   // If the shrunk mask fits in sign extended 12 bits, let the target
   // independent code apply it.
   if (ShrunkMask.isSignedIntN(12))
     return false;
 
   // And has a few special cases for zext.
   if (Opcode == ISD::AND) {
-    // Preserve (and X, 0xffff) when zext.h is supported.
-    if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
-      APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
-      if (IsLegalMask(NewMask))
-        return UseMask(NewMask);
-    }
+    // Preserve (and X, 0xffff), if zext.h exists use zext.h,
+    // otherwise use SLLI + SRLI.
 
     // Try to preserve (and X, 0xffffffff), the (zext_inreg X, i32) pattern.
     if (VT == MVT::i64) {
       APInt NewMask = APInt(64, 0xffffffff);
       if (IsLegalMask(NewMask))
         return UseMask(NewMask);
     }
   }

llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

 ; CHECK-NEXT:    sw a4, 0(a1)
 ; CHECK-NEXT:    ret
   %4 = and i32 %0, -8
   %5 = lshr i32 %0, 3
   store i32 %5, ptr %1, align 4
   %6 = add i32 %4, %2
   ret i32 %6
 }
+
+define i32 @and_or(i32 signext %x) {
+; CHECK-LABEL: and_or:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ori a0, a0, 255
+; CHECK-NEXT:    slli a0, a0, 48
+; CHECK-NEXT:    srli a0, a0, 48
+; CHECK-NEXT:    ret
+entry:
+  %and = and i32 %x, 65280
+  %or = or i32 %and, 255
+  ret i32 %or
+}