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Differential D133902

X86: Stop assigning register costs for longer encodings
ClosedPublic

Authored by MatzeB on Sep 14 2022, 3:32 PM.

Details

Reviewers
RKSimon
craig.topper
qcolombet
mtrofin
arsenm
reames
wmi
sjarus
lebedev.ri
Commits
rG189900eb149b: X86: Stop assigning register costs for longer encodings.
Summary

This stops reporting CostPerUse 1 for R8-R15 and XMM8-XMM31. This was
previously done because instruction encoding require a REX prefix when
using them resulting in longer instruction encodings. I found that this
regresses the quality of the register allocation as the costs impose an
ordering on eviction candidates. I also feel that there is a bit of an
impedance mismatch as the actual costs occure when encoding instructions
using those registers, but the order of VReg assignments is not
primarily ordered by number of Defs+Uses.

I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.

Results for measuring static and dynamic instruction counts:

-O3 + ThinLTO + Instr-PGO

Dynamic Counts (scaled by execution frequency) / Optimization Remarks:

Spills+FoldedSpills   -5.6%
Reloads+FoldedReloads -4.2%
Copies                -0.1%

Static / LLVM Statistics:

regalloc.NumSpills    mean -1.6%, geomean -2.8%
regalloc.NumReloads   mean -1.7%, geomean -3.1%
size..text            mean +0.4%, geomean +0.4%

-O3

Static / LLVM Statistics:

mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text

-Os

Static / LLVM Statistics:

regalloc.NumSpills   mean -3.0%
regalloc.NumReloads  mean -3.3%
size..text           mean +0.3%, geomean +0.3%

Detailed numbers in https://reviews.llvm.org/P8290

Diff Detail

Event Timeline

MatzeB created this revision.Sep 14 2022, 3:32 PM
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MatzeB added a comment.Sep 14 2022, 3:40 PM

I guess this somewhat of an RFC, if we would accept better regalloc at slightly bigger programs: I found that dropping CostPerUse produced a small but measurable improvement on X86 regalloc.

I would also love to hear if others can explain why the increased register costs for the larger encodings result in slightly smaller programs, even though I don't us prefering registers with more or less uses when ordering eviction and assignment choices (and as far as the AllocationOrder goes the register with longer encodings are still on the back anyway).

MatzeB edited the summary of this revision. (Show Details)Sep 14 2022, 3:42 PM
craig.topper added a comment.Sep 14 2022, 3:56 PM

Looks like the code change to X86RegisterInfo.td is not in this patch?

Harbormaster completed remote builds in B186744: Diff 460246.Sep 14 2022, 4:21 PM
asb added a subscriber: asb.Sep 15 2022, 9:47 AM

D86836 introduced support for setting multiple CostPerUse values (which we use on RISC-V to set a non-zero value for some registers only when the 'compressed' extension is enabled). Did you evaluate doing something similar to only set CostPerUse at Os or perhaps Oz?

MatzeB added a comment.Sep 15 2022, 10:43 AM
In D133902#3791069, @craig.topper wrote:

Looks like the code change to X86RegisterInfo.td is not in this patch?

huh. It's included now.

D86836 introduced support for setting multiple CostPerUse values (which we use on RISC-V to set a non-zero value for some registers only when the 'compressed' extension is enabled). Did you evaluate doing something similar to only set CostPerUse at Os or perhaps Oz?

Yes I saw that, didn't push on this angle (yet) as we should really use llvm::shouldOptimizeForSize then which requires a ProfileSummaryInfo reference that isn't around in that callback. So would need to refactor those interfaces in some way...

MatzeB updated this revision to Diff 460453.Sep 15 2022, 10:46 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 15 2022, 10:46 AM
Harbormaster completed remote builds in B186900: Diff 460453.Sep 15 2022, 11:23 AM
RKSimon added a comment.Sep 16 2022, 4:00 AM

Early x86-64 CPUs (often with weak frontend/decoders) might benefit from avoiding REX encodings (I know when I was doing exegesis testing for the atom/silvermont sched models avoiding REX registers gave much more consistent backend numbers), although I'm not certain how much work adding CPU Feature specific costs would be (or how much benefit they'd give for most people).

llvm/lib/Target/X86/X86RegisterInfo.td
128

Keep the comments?

221

This comment is still useful

mtrofin added a comment.Sep 16 2022, 12:10 PM

LGTM

In D133902#3791035, @MatzeB wrote:

I guess this somewhat of an RFC, if we would accept better regalloc at slightly bigger programs: I found that dropping CostPerUse produced a small but measurable improvement on X86 regalloc.

FWIW, tried it on a server app (was curious if the "slightly larger" bit meant more iCache pressure), doesn't seem to be an issue.

I would also love to hear if others can explain why the increased register costs for the larger encodings result in slightly smaller programs, even though I don't us prefering registers with more or less uses when ordering eviction and assignment choices (and as far as the AllocationOrder goes the register with longer encodings are still on the back anyway).

mtrofin accepted this revision.Sep 16 2022, 12:11 PM
This revision is now accepted and ready to land.Sep 16 2022, 12:11 PM
qcolombet added a comment.Sep 16 2022, 12:16 PM

Looks sensible to me.
I would just second @RKSimon's question about how this works with older x86 HW but if x86 folks are fine with the change, that's fine by me.

MatzeB marked 2 inline comments as done.Sep 30 2022, 1:42 PM

Early x86-64 CPUs (often with weak frontend/decoders) might benefit from avoiding REX encodings (I know when I was doing exegesis testing for the atom/silvermont sched models avoiding REX registers gave much more consistent backend numbers), although I'm not certain how much work adding CPU Feature specific costs would be (or how much benefit they'd give for most people).

My gut feeling would be that we are better off without the added complexity, as the size differences are somewhat happening by accident anyway. And in fact looking into my data the size differences seem to mostly stem from small functions and there is not really a trend for bigger functions.

llvm/lib/Target/X86/X86RegisterInfo.td
128

To me it seemed that this comment was meant to justify the CostPerUse = [1] which I am removing, but no problem to keep them anyway.

MatzeB updated this revision to Diff 464388.Sep 30 2022, 1:49 PM
MatzeB marked an inline comment as done.

rebase, update some tests missed the first time.

MatzeB edited the summary of this revision. (Show Details)Sep 30 2022, 1:50 PM
MatzeB edited the summary of this revision. (Show Details)
MatzeB edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B189770: Diff 464388.Sep 30 2022, 3:03 PM
This revision was landed with ongoing or failed builds.Sep 30 2022, 4:03 PM
Closed by commit rG189900eb149b: X86: Stop assigning register costs for longer encodings. (authored by MatzeB). · Explain Why
This revision was automatically updated to reflect the committed changes.
MatzeB added a commit: rG189900eb149b: X86: Stop assigning register costs for longer encodings..
MatzeB added a comment.Sep 30 2022, 5:27 PM

Fixes for expensive-tests enabled bots and attempt at fixing MLRegalloc tests in https://github.com/llvm/llvm-project/commit/f9317bf0bed0e0f248c18114afa24dcd56d727ae (aka https://reviews.llvm.org/rGf9317bf0bed0 )

mtrofin mentioned this in rG25d65b545530: [mlgo] Fix tests post D133902.Sep 30 2022, 5:28 PM
mtrofin added a comment.EditedSep 30 2022, 5:28 PM

was just sending the fix or the mlgo bit, thanks for looking into it!

mtrofin mentioned this in rG280ed30b6487: Revert "[mlgo] Fix tests post D133902".Sep 30 2022, 5:30 PM
MatzeB added a comment.Sep 30 2022, 5:33 PM

I'm not sure I have 100% fixed it, we'll see :)

Also thinking about things right now, I realized that my change probably lowers the amount of times ragreedy asks for eviction decisions. I hope that doesn't reduce the quality of ML regalloc, maybe you can keep on eye on that on your end.

(I'm happy to revert if it decreases quality, though we have to find a better way than somewhat "arbitrary" CostPerUse / high register numbers triggering things long-term...)

mtrofin added a comment.Sep 30 2022, 5:36 PM
In D133902#3828661, @MatzeB wrote:

I'm not sure I have 100% fixed it, we'll see :)

Also thinking about things right now, I realized that my change probably lowers the amount of times ragreedy asks for eviction decisions. I hope that doesn't reduce the quality of ML regalloc, maybe you can keep on eye on that on your end.

(I'm happy to revert if it decreases quality, though we have to find a better way than somewhat "arbitrary" CostPerUse / high register numbers triggering things long-term...)

I tried it with your change already, didn't see anything for the workload I looked at - anyway, we can always retrain it if needed.

MatzeB added a comment.Sep 30 2022, 5:44 PM

Seems we need your changed to dev-mode-logging.ll after all, will push them now.

MatzeB mentioned this in rG56c7cf41d451: Adapt dev-mode-logging.ll test to D133902.Sep 30 2022, 5:45 PM
MatzeB mentioned this in rGbd1ea6e110a3: UPdate reference-log-noml.txt as well to adapt for D133902.Sep 30 2022, 6:04 PM
skan added a subscriber: skan.Feb 1 2023, 4:03 AM

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Diff 464424

llvm/lib/Target/X86/X86RegisterInfo.td

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
// High registers. On x86-64, these cannot be used in any instruction // High registers. On x86-64, these cannot be used in any instruction
// with a REX prefix. // with a REX prefix.
def AH : X86Reg<"ah", 4>; def AH : X86Reg<"ah", 4>;
def DH : X86Reg<"dh", 6>; def DH : X86Reg<"dh", 6>;
def CH : X86Reg<"ch", 5>; def CH : X86Reg<"ch", 5>;
def BH : X86Reg<"bh", 7>; def BH : X86Reg<"bh", 7>;
// X86-64 only, requires REX. // X86-64 only, requires REX.
let CostPerUse = [1] in {
def SIL : X86Reg<"sil", 6>; def SIL : X86Reg<"sil", 6>;
def DIL : X86Reg<"dil", 7>; def DIL : X86Reg<"dil", 7>;
def BPL : X86Reg<"bpl", 5>; def BPL : X86Reg<"bpl", 5>;
def SPL : X86Reg<"spl", 4>; def SPL : X86Reg<"spl", 4>;
def R8B : X86Reg<"r8b", 8>; def R8B : X86Reg<"r8b", 8>;
def R9B : X86Reg<"r9b", 9>; def R9B : X86Reg<"r9b", 9>;
def R10B : X86Reg<"r10b", 10>; def R10B : X86Reg<"r10b", 10>;
def R11B : X86Reg<"r11b", 11>; def R11B : X86Reg<"r11b", 11>;
def R12B : X86Reg<"r12b", 12>; def R12B : X86Reg<"r12b", 12>;
def R13B : X86Reg<"r13b", 13>; def R13B : X86Reg<"r13b", 13>;
def R14B : X86Reg<"r14b", 14>; def R14B : X86Reg<"r14b", 14>;
def R15B : X86Reg<"r15b", 15>; def R15B : X86Reg<"r15b", 15>;
}
let isArtificial = 1 in { let isArtificial = 1 in {
// High byte of the low 16 bits of the super-register: // High byte of the low 16 bits of the super-register:
def SIH : X86Reg<"", -1>; def SIH : X86Reg<"", -1>;
def DIH : X86Reg<"", -1>; def DIH : X86Reg<"", -1>;
def BPH : X86Reg<"", -1>; def BPH : X86Reg<"", -1>;
def SPH : X86Reg<"", -1>; def SPH : X86Reg<"", -1>;
def R8BH : X86Reg<"", -1>; def R8BH : X86Reg<"", -1>;
Show All 34 Lines
let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
def SI : X86Reg<"si", 6, [SIL,SIH]>; def SI : X86Reg<"si", 6, [SIL,SIH]>;
def DI : X86Reg<"di", 7, [DIL,DIH]>; def DI : X86Reg<"di", 7, [DIL,DIH]>;
def BP : X86Reg<"bp", 5, [BPL,BPH]>; def BP : X86Reg<"bp", 5, [BPL,BPH]>;
def SP : X86Reg<"sp", 4, [SPL,SPH]>; def SP : X86Reg<"sp", 4, [SPL,SPH]>;
} }
def IP : X86Reg<"ip", 0>; def IP : X86Reg<"ip", 0>;
// X86-64 only, requires REX. // X86-64 only, requires REX.
RKSimonUnsubmitted
Done
ReplyInline Actions

Keep the comments?

RKSimon: Keep the comments?
MatzeBAuthorUnsubmitted
Done
ReplyInline Actions

To me it seemed that this comment was meant to justify the CostPerUse = [1] which I am removing, but no problem to keep them anyway.

MatzeB: To me it seemed that this comment was meant to justify the `CostPerUse = [1]` which I am…
let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = [1], let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in {
CoveredBySubRegs = 1 in {
def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>;
def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>;
def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>;
def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>;
def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>;
def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>;
def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>;
def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>;
} }
// 32-bit registers // 32-bit registers
let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
} }
// X86-64 only, requires REX // X86-64 only, requires REX
let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = [1], let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in {
CoveredBySubRegs = 1 in {
def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>;
def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>;
def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>;
def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>;
def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>;
def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>;
def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>;
def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>;
} }
// 64-bit registers, X86-64 only // 64-bit registers, X86-64 only
let SubRegIndices = [sub_32bit] in { let SubRegIndices = [sub_32bit] in {
def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
// These also require REX. // These also require REX.
let CostPerUse = [1] in {
def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
}} }
// MMX Registers. These are actually aliased to ST0 .. ST7 // MMX Registers. These are actually aliased to ST0 .. ST7
def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
Show All 15 Lines
def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
// X86-64 only // X86-64 only
RKSimonUnsubmitted
Done
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This comment is still useful

RKSimon: This comment is still useful
let CostPerUse = [1] in {
def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
Show All 10 Lines
def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>;
def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>;
def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>;
def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>;
def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>;
def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>;
def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>;
} // CostPerUse
// YMM0-15 registers, used by AVX instructions and // YMM0-15 registers, used by AVX instructions and
// YMM16-31 registers, used by AVX-512 instructions. // YMM16-31 registers, used by AVX-512 instructions.
let SubRegIndices = [sub_xmm] in { let SubRegIndices = [sub_xmm] in {
foreach Index = 0-31 in { foreach Index = 0-31 in {
def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>,
DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>;
} }
} }
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llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll

llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll

llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll

llvm/test/CodeGen/X86/AMX/amx-across-func.ll

llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll

llvm/test/CodeGen/X86/AMX/amx-intrinsic-chain.ll

llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll

llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

llvm/test/CodeGen/X86/AMX/amx-spill.ll

llvm/test/CodeGen/X86/MergeConsecutiveStores.ll

llvm/test/CodeGen/X86/StackColoring.ll

llvm/test/CodeGen/X86/add-and-not.ll

llvm/test/CodeGen/X86/addcarry.ll

llvm/test/CodeGen/X86/avg.ll

llvm/test/CodeGen/X86/avoid-sfb.ll

llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx-load-store.ll

llvm/test/CodeGen/X86/avx512-calling-conv.ll

llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/bfloat.ll

llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll

llvm/test/CodeGen/X86/bitreverse.ll

llvm/test/CodeGen/X86/break-false-dep.ll

llvm/test/CodeGen/X86/bswap.ll

llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll

llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll

llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll

llvm/test/CodeGen/X86/cgp-usubo.ll

llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll

llvm/test/CodeGen/X86/combine-pmuldq.ll

llvm/test/CodeGen/X86/combine-sdiv.ll

llvm/test/CodeGen/X86/commute-fcmp.ll

llvm/test/CodeGen/X86/compact-unwind.ll

llvm/test/CodeGen/X86/conditional-tailcall.ll

llvm/test/CodeGen/X86/copy-eflags.ll

llvm/test/CodeGen/X86/ctpop-combine.ll

llvm/test/CodeGen/X86/dag-update-nodetomatch.ll

llvm/test/CodeGen/X86/dagcombine-cse.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll

llvm/test/CodeGen/X86/divmod128.ll

llvm/test/CodeGen/X86/extract-bits.ll

llvm/test/CodeGen/X86/flt-rounds.ll

llvm/test/CodeGen/X86/fma-commute-loop.ll

llvm/test/CodeGen/X86/fmaddsub-combine.ll

llvm/test/CodeGen/X86/fmaxnum.ll

llvm/test/CodeGen/X86/fminnum.ll

llvm/test/CodeGen/X86/fp-stack-2results.ll

llvm/test/CodeGen/X86/fp128-libcalls-strict.ll

llvm/test/CodeGen/X86/fp128-select.ll

llvm/test/CodeGen/X86/fpclamptosat_vec.ll

llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll

llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll

llvm/test/CodeGen/X86/gather-addresses.ll

llvm/test/CodeGen/X86/h-registers-1.ll

llvm/test/CodeGen/X86/haddsub-2.ll

llvm/test/CodeGen/X86/haddsub-4.ll

llvm/test/CodeGen/X86/hoist-invariant-load.ll

llvm/test/CodeGen/X86/i128-mul.ll

llvm/test/CodeGen/X86/load-local-v3i1.ll

llvm/test/CodeGen/X86/lrshrink.ll

llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll

llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll

llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

llvm/test/CodeGen/X86/machine-cp.ll

llvm/test/CodeGen/X86/madd.ll

llvm/test/CodeGen/X86/masked-iv-unsafe.ll

llvm/test/CodeGen/X86/masked_compressstore.ll

llvm/test/CodeGen/X86/masked_expandload.ll

llvm/test/CodeGen/X86/masked_gather.ll

llvm/test/CodeGen/X86/masked_load.ll

llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll

llvm/test/CodeGen/X86/masked_store_trunc_usat.ll

llvm/test/CodeGen/X86/midpoint-int-vec-256.ll

llvm/test/CodeGen/X86/misched-matmul.ll

llvm/test/CodeGen/X86/mmx-arith.ll

llvm/test/CodeGen/X86/mul-constant-result.ll

llvm/test/CodeGen/X86/mul-i1024.ll

llvm/test/CodeGen/X86/mul-i256.ll

llvm/test/CodeGen/X86/mul-i512.ll

llvm/test/CodeGen/X86/muloti.ll

llvm/test/CodeGen/X86/musttail-varargs.ll

llvm/test/CodeGen/X86/nontemporal-loads.ll

llvm/test/CodeGen/X86/oddshuffles.ll

llvm/test/CodeGen/X86/or-address.ll

llvm/test/CodeGen/X86/paddus.ll

llvm/test/CodeGen/X86/pmul.ll

llvm/test/CodeGen/X86/pmulh.ll

llvm/test/CodeGen/X86/popcnt.ll

llvm/test/CodeGen/X86/pr18344.ll

llvm/test/CodeGen/X86/pr21792.ll

llvm/test/CodeGen/X86/pr23603.ll

llvm/test/CodeGen/X86/pr29112.ll

llvm/test/CodeGen/X86/pr32329.ll

llvm/test/CodeGen/X86/pr35316.ll

llvm/test/CodeGen/X86/pr38185.ll

llvm/test/CodeGen/X86/pr38217.ll

llvm/test/CodeGen/X86/pr43820.ll

llvm/test/CodeGen/X86/pr45563-2.ll

llvm/test/CodeGen/X86/pr45563.ll

llvm/test/CodeGen/X86/pr45995.ll

llvm/test/CodeGen/X86/pr46877.ll

llvm/test/CodeGen/X86/pr47299.ll

llvm/test/CodeGen/X86/pr47857.ll

llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll

llvm/test/CodeGen/X86/promote-cmp.ll

llvm/test/CodeGen/X86/psubus.ll

llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll

llvm/test/CodeGen/X86/reverse_branches.ll

llvm/test/CodeGen/X86/sad.ll

llvm/test/CodeGen/X86/sadd_sat_vec.ll

llvm/test/CodeGen/X86/sbb-false-dep.ll

llvm/test/CodeGen/X86/scalar_widen_div.ll

llvm/test/CodeGen/X86/scheduler-backtracking.ll

llvm/test/CodeGen/X86/sdiv_fix.ll

llvm/test/CodeGen/X86/sdiv_fix_sat.ll

llvm/test/CodeGen/X86/setcc-wide-types.ll

llvm/test/CodeGen/X86/shift-i128.ll

llvm/test/CodeGen/X86/shrink_vmul.ll

llvm/test/CodeGen/X86/smul-with-overflow.ll

llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll

llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll

llvm/test/CodeGen/X86/speculative-load-hardening.ll

llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

llvm/test/CodeGen/X86/sse-intel-ocl.ll

llvm/test/CodeGen/X86/sse-regcall.ll

llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/sshl_sat.ll

llvm/test/CodeGen/X86/ssub_sat_vec.ll

llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir

llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir

llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir

llvm/test/CodeGen/X86/statepoint-live-in-remat.ll

llvm/test/CodeGen/X86/statepoint-live-in.ll

llvm/test/CodeGen/X86/statepoint-ra-no-ls.ll

llvm/test/CodeGen/X86/statepoint-regs.ll

llvm/test/CodeGen/X86/statepoint-spill-slot-size-promotion.ll

llvm/test/CodeGen/X86/statepoint-stack-usage.ll

llvm/test/CodeGen/X86/statepoint-vreg-details.ll

llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll

llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll

llvm/test/CodeGen/X86/statepoint-vreg.ll

llvm/test/CodeGen/X86/statepoint-vreg.mir

llvm/test/CodeGen/X86/subcarry.ll

llvm/test/CodeGen/X86/swifterror.ll

llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll

llvm/test/CodeGen/X86/tail-opts.ll

llvm/test/CodeGen/X86/tailcallstack64.ll

llvm/test/CodeGen/X86/tailccstack64.ll

llvm/test/CodeGen/X86/twoaddr-lea.ll

llvm/test/CodeGen/X86/uadd_sat_vec.ll

llvm/test/CodeGen/X86/udiv_fix_sat.ll

llvm/test/CodeGen/X86/umul-with-overflow.ll

llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll

llvm/test/CodeGen/X86/usub_sat_vec.ll

llvm/test/CodeGen/X86/var-permute-128.ll

llvm/test/CodeGen/X86/var-permute-512.ll

llvm/test/CodeGen/X86/vec_int_to_fp.ll

llvm/test/CodeGen/X86/vec_saddo.ll

llvm/test/CodeGen/X86/vec_smulo.ll

llvm/test/CodeGen/X86/vec_ssubo.ll

llvm/test/CodeGen/X86/vec_uaddo.ll

llvm/test/CodeGen/X86/vec_umulo.ll

llvm/test/CodeGen/X86/vec_usubo.ll

llvm/test/CodeGen/X86/vector-bitreverse.ll

llvm/test/CodeGen/X86/vector-compare-results.ll

llvm/test/CodeGen/X86/vector-fshl-128.ll

llvm/test/CodeGen/X86/vector-fshl-256.ll

llvm/test/CodeGen/X86/vector-fshl-rot-256.ll

llvm/test/CodeGen/X86/vector-fshr-128.ll

llvm/test/CodeGen/X86/vector-fshr-256.ll

llvm/test/CodeGen/X86/vector-fshr-rot-256.ll

llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll

llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

llvm/test/CodeGen/X86/vector-interleave.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

llvm/test/CodeGen/X86/vector-reduce-add-sext.ll

llvm/test/CodeGen/X86/vector-reduce-fmax.ll

llvm/test/CodeGen/X86/vector-reduce-fmin.ll

llvm/test/CodeGen/X86/vector-reduce-mul.ll

llvm/test/CodeGen/X86/vector-reduce-umax.ll

llvm/test/CodeGen/X86/vector-reduce-umin.ll

llvm/test/CodeGen/X86/vector-rotate-256.ll

llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll

llvm/test/CodeGen/X86/vector-shuffle-v192.ll

llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll

llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll

llvm/test/CodeGen/X86/vector-trunc-math.ll

llvm/test/CodeGen/X86/vector-trunc-packus.ll

llvm/test/CodeGen/X86/vector-trunc-ssat.ll

llvm/test/CodeGen/X86/vector-trunc-usat.ll

llvm/test/CodeGen/X86/vector-zext.ll

llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll

llvm/test/CodeGen/X86/vselect-minmax.ll

llvm/test/CodeGen/X86/vselect-packss.ll

llvm/test/CodeGen/X86/x86-cmov-converter.ll

llvm/test/CodeGen/X86/x86-interleaved-access.ll

llvm/test/CodeGen/X86/zext-sext.ll

llvm/test/CodeGen/X86/znver3-gather.ll

llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

llvm/test/DebugInfo/X86/live-debug-variables.ll

llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll

llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll

llvm/test/Transforms/LoopStrengthReduce/X86/lsr-insns-2.ll

llvm/test/tools/llvm-locstats/locstats.ll