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Differential D133902

X86: Stop assigning register costs for longer encodings
ClosedPublic

Authored by MatzeB on Sep 14 2022, 3:32 PM.

Details

Reviewers
RKSimon
craig.topper
qcolombet
mtrofin
arsenm
reames
wmi
sjarus
lebedev.ri
Commits
rG189900eb149b: X86: Stop assigning register costs for longer encodings.
Summary

This stops reporting CostPerUse 1 for R8-R15 and XMM8-XMM31. This was
previously done because instruction encoding require a REX prefix when
using them resulting in longer instruction encodings. I found that this
regresses the quality of the register allocation as the costs impose an
ordering on eviction candidates. I also feel that there is a bit of an
impedance mismatch as the actual costs occure when encoding instructions
using those registers, but the order of VReg assignments is not
primarily ordered by number of Defs+Uses.

I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.

Results for measuring static and dynamic instruction counts:

-O3 + ThinLTO + Instr-PGO

Dynamic Counts (scaled by execution frequency) / Optimization Remarks:

Spills+FoldedSpills   -5.6%
Reloads+FoldedReloads -4.2%
Copies                -0.1%

Static / LLVM Statistics:

regalloc.NumSpills    mean -1.6%, geomean -2.8%
regalloc.NumReloads   mean -1.7%, geomean -3.1%
size..text            mean +0.4%, geomean +0.4%

-O3

Static / LLVM Statistics:

mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text

-Os

Static / LLVM Statistics:

regalloc.NumSpills   mean -3.0%
regalloc.NumReloads  mean -3.3%
size..text           mean +0.3%, geomean +0.3%

Detailed numbers in https://reviews.llvm.org/P8290

Diff Detail

Event Timeline

MatzeB created this revision.Sep 14 2022, 3:32 PM
Herald added a reviewer: sjarus. · View Herald TranscriptSep 14 2022, 3:32 PM
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Herald added subscribers: lebedev.ri, armkevincheng, eric-k256 and 8 others. · View Herald Transcript
MatzeB requested review of this revision.Sep 14 2022, 3:32 PM
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MatzeB added a comment.Sep 14 2022, 3:40 PM

I guess this somewhat of an RFC, if we would accept better regalloc at slightly bigger programs: I found that dropping CostPerUse produced a small but measurable improvement on X86 regalloc.

I would also love to hear if others can explain why the increased register costs for the larger encodings result in slightly smaller programs, even though I don't us prefering registers with more or less uses when ordering eviction and assignment choices (and as far as the AllocationOrder goes the register with longer encodings are still on the back anyway).

MatzeB edited the summary of this revision. (Show Details)Sep 14 2022, 3:42 PM
craig.topper added a comment.Sep 14 2022, 3:56 PM

Looks like the code change to X86RegisterInfo.td is not in this patch?

Harbormaster completed remote builds in B186744: Diff 460246.Sep 14 2022, 4:21 PM
asb added a subscriber: asb.Sep 15 2022, 9:47 AM

D86836 introduced support for setting multiple CostPerUse values (which we use on RISC-V to set a non-zero value for some registers only when the 'compressed' extension is enabled). Did you evaluate doing something similar to only set CostPerUse at Os or perhaps Oz?

MatzeB added a comment.Sep 15 2022, 10:43 AM
In D133902#3791069, @craig.topper wrote:

Looks like the code change to X86RegisterInfo.td is not in this patch?

huh. It's included now.

D86836 introduced support for setting multiple CostPerUse values (which we use on RISC-V to set a non-zero value for some registers only when the 'compressed' extension is enabled). Did you evaluate doing something similar to only set CostPerUse at Os or perhaps Oz?

Yes I saw that, didn't push on this angle (yet) as we should really use llvm::shouldOptimizeForSize then which requires a ProfileSummaryInfo reference that isn't around in that callback. So would need to refactor those interfaces in some way...

MatzeB updated this revision to Diff 460453.Sep 15 2022, 10:46 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptSep 15 2022, 10:46 AM
Harbormaster completed remote builds in B186900: Diff 460453.Sep 15 2022, 11:23 AM
RKSimon added a comment.Sep 16 2022, 4:00 AM

Early x86-64 CPUs (often with weak frontend/decoders) might benefit from avoiding REX encodings (I know when I was doing exegesis testing for the atom/silvermont sched models avoiding REX registers gave much more consistent backend numbers), although I'm not certain how much work adding CPU Feature specific costs would be (or how much benefit they'd give for most people).

llvm/lib/Target/X86/X86RegisterInfo.td
128 ↗(On Diff #460453)

Keep the comments?

221 ↗(On Diff #460453)

This comment is still useful

mtrofin added a comment.Sep 16 2022, 12:10 PM

LGTM

In D133902#3791035, @MatzeB wrote:

I guess this somewhat of an RFC, if we would accept better regalloc at slightly bigger programs: I found that dropping CostPerUse produced a small but measurable improvement on X86 regalloc.

FWIW, tried it on a server app (was curious if the "slightly larger" bit meant more iCache pressure), doesn't seem to be an issue.

I would also love to hear if others can explain why the increased register costs for the larger encodings result in slightly smaller programs, even though I don't us prefering registers with more or less uses when ordering eviction and assignment choices (and as far as the AllocationOrder goes the register with longer encodings are still on the back anyway).

mtrofin accepted this revision.Sep 16 2022, 12:11 PM
This revision is now accepted and ready to land.Sep 16 2022, 12:11 PM
qcolombet added a comment.Sep 16 2022, 12:16 PM

Looks sensible to me.
I would just second @RKSimon's question about how this works with older x86 HW but if x86 folks are fine with the change, that's fine by me.

MatzeB marked 2 inline comments as done.Sep 30 2022, 1:42 PM

Early x86-64 CPUs (often with weak frontend/decoders) might benefit from avoiding REX encodings (I know when I was doing exegesis testing for the atom/silvermont sched models avoiding REX registers gave much more consistent backend numbers), although I'm not certain how much work adding CPU Feature specific costs would be (or how much benefit they'd give for most people).

My gut feeling would be that we are better off without the added complexity, as the size differences are somewhat happening by accident anyway. And in fact looking into my data the size differences seem to mostly stem from small functions and there is not really a trend for bigger functions.

llvm/lib/Target/X86/X86RegisterInfo.td
128 ↗(On Diff #460453)

To me it seemed that this comment was meant to justify the CostPerUse = [1] which I am removing, but no problem to keep them anyway.

MatzeB updated this revision to Diff 464388.Sep 30 2022, 1:49 PM
MatzeB marked an inline comment as done.

rebase, update some tests missed the first time.

MatzeB edited the summary of this revision. (Show Details)Sep 30 2022, 1:50 PM
MatzeB edited the summary of this revision. (Show Details)
MatzeB edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B189770: Diff 464388.Sep 30 2022, 3:03 PM
This revision was landed with ongoing or failed builds.Sep 30 2022, 4:03 PM
Closed by commit rG189900eb149b: X86: Stop assigning register costs for longer encodings. (authored by MatzeB). · Explain Why
This revision was automatically updated to reflect the committed changes.
MatzeB added a commit: rG189900eb149b: X86: Stop assigning register costs for longer encodings..
MatzeB added a comment.Sep 30 2022, 5:27 PM

Fixes for expensive-tests enabled bots and attempt at fixing MLRegalloc tests in https://github.com/llvm/llvm-project/commit/f9317bf0bed0e0f248c18114afa24dcd56d727ae (aka https://reviews.llvm.org/rGf9317bf0bed0 )

mtrofin mentioned this in rG25d65b545530: [mlgo] Fix tests post D133902.Sep 30 2022, 5:28 PM
mtrofin added a comment.EditedSep 30 2022, 5:28 PM

was just sending the fix or the mlgo bit, thanks for looking into it!

mtrofin mentioned this in rG280ed30b6487: Revert "[mlgo] Fix tests post D133902".Sep 30 2022, 5:30 PM
MatzeB added a comment.Sep 30 2022, 5:33 PM

I'm not sure I have 100% fixed it, we'll see :)

Also thinking about things right now, I realized that my change probably lowers the amount of times ragreedy asks for eviction decisions. I hope that doesn't reduce the quality of ML regalloc, maybe you can keep on eye on that on your end.

(I'm happy to revert if it decreases quality, though we have to find a better way than somewhat "arbitrary" CostPerUse / high register numbers triggering things long-term...)

mtrofin added a comment.Sep 30 2022, 5:36 PM
In D133902#3828661, @MatzeB wrote:

I'm not sure I have 100% fixed it, we'll see :)

Also thinking about things right now, I realized that my change probably lowers the amount of times ragreedy asks for eviction decisions. I hope that doesn't reduce the quality of ML regalloc, maybe you can keep on eye on that on your end.

(I'm happy to revert if it decreases quality, though we have to find a better way than somewhat "arbitrary" CostPerUse / high register numbers triggering things long-term...)

I tried it with your change already, didn't see anything for the workload I looked at - anyway, we can always retrain it if needed.

MatzeB added a comment.Sep 30 2022, 5:44 PM

Seems we need your changed to dev-mode-logging.ll after all, will push them now.

MatzeB mentioned this in rG56c7cf41d451: Adapt dev-mode-logging.ll test to D133902.Sep 30 2022, 5:45 PM
MatzeB mentioned this in rGbd1ea6e110a3: UPdate reference-log-noml.txt as well to adapt for D133902.Sep 30 2022, 6:04 PM
skan added a subscriber: skan.Feb 1 2023, 4:03 AM

Large Diff

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Diff 460246

llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll

llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll

llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll

llvm/test/CodeGen/X86/AMX/amx-across-func.ll

llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll

llvm/test/CodeGen/X86/AMX/amx-intrinsic-chain.ll

llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll

llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll

llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

llvm/test/CodeGen/X86/AMX/amx-spill.ll

llvm/test/CodeGen/X86/MergeConsecutiveStores.ll

llvm/test/CodeGen/X86/StackColoring.ll

llvm/test/CodeGen/X86/add-and-not.ll

llvm/test/CodeGen/X86/addcarry.ll

llvm/test/CodeGen/X86/avg.ll

llvm/test/CodeGen/X86/avoid-sfb.ll

llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx-load-store.ll

llvm/test/CodeGen/X86/avx512-calling-conv.ll

llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/bfloat.ll

llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll

llvm/test/CodeGen/X86/bitreverse.ll

llvm/test/CodeGen/X86/break-false-dep.ll

llvm/test/CodeGen/X86/bswap.ll

llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll

llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll

llvm/test/CodeGen/X86/callbr-asm-phi-placement.ll

llvm/test/CodeGen/X86/cgp-usubo.ll

llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll

llvm/test/CodeGen/X86/combine-pmuldq.ll

llvm/test/CodeGen/X86/combine-sdiv.ll

llvm/test/CodeGen/X86/commute-fcmp.ll

llvm/test/CodeGen/X86/compact-unwind.ll

llvm/test/CodeGen/X86/conditional-tailcall.ll

llvm/test/CodeGen/X86/copy-eflags.ll

llvm/test/CodeGen/X86/ctpop-combine.ll

llvm/test/CodeGen/X86/dag-update-nodetomatch.ll

llvm/test/CodeGen/X86/dagcombine-cse.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll

llvm/test/CodeGen/X86/divmod128.ll

llvm/test/CodeGen/X86/extract-bits.ll

llvm/test/CodeGen/X86/flt-rounds.ll

llvm/test/CodeGen/X86/fma-commute-loop.ll

llvm/test/CodeGen/X86/fmaddsub-combine.ll

llvm/test/CodeGen/X86/fmaxnum.ll

llvm/test/CodeGen/X86/fminnum.ll

llvm/test/CodeGen/X86/fp-stack-2results.ll

llvm/test/CodeGen/X86/fp128-libcalls-strict.ll

llvm/test/CodeGen/X86/fp128-select.ll

llvm/test/CodeGen/X86/fpclamptosat_vec.ll

llvm/test/CodeGen/X86/fptosi-sat-vector-128.ll

llvm/test/CodeGen/X86/fptoui-sat-vector-128.ll

llvm/test/CodeGen/X86/gather-addresses.ll

llvm/test/CodeGen/X86/h-registers-1.ll

llvm/test/CodeGen/X86/haddsub-2.ll

llvm/test/CodeGen/X86/haddsub-4.ll

llvm/test/CodeGen/X86/hoist-invariant-load.ll

llvm/test/CodeGen/X86/i128-mul.ll

llvm/test/CodeGen/X86/load-local-v3i1.ll

llvm/test/CodeGen/X86/lrshrink.ll

llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll

llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll

llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

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llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll

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llvm/test/CodeGen/X86/statepoint-stack-usage.ll

llvm/test/CodeGen/X86/statepoint-vreg-details.ll

llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll

llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll

llvm/test/CodeGen/X86/statepoint-vreg.ll

llvm/test/CodeGen/X86/statepoint-vreg.mir

llvm/test/CodeGen/X86/subcarry.ll

llvm/test/CodeGen/X86/swifterror.ll

llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll

llvm/test/CodeGen/X86/tail-opts.ll

llvm/test/CodeGen/X86/tailcallstack64.ll

llvm/test/CodeGen/X86/tailccstack64.ll

llvm/test/CodeGen/X86/twoaddr-lea.ll

llvm/test/CodeGen/X86/uadd_sat_vec.ll

llvm/test/CodeGen/X86/udiv_fix_sat.ll

llvm/test/CodeGen/X86/umul-with-overflow.ll

llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll

llvm/test/CodeGen/X86/usub_sat_vec.ll

llvm/test/CodeGen/X86/var-permute-128.ll

llvm/test/CodeGen/X86/var-permute-512.ll

llvm/test/CodeGen/X86/vec_int_to_fp.ll

llvm/test/CodeGen/X86/vec_saddo.ll

llvm/test/CodeGen/X86/vec_smulo.ll

llvm/test/CodeGen/X86/vec_ssubo.ll

llvm/test/CodeGen/X86/vec_uaddo.ll

llvm/test/CodeGen/X86/vec_umulo.ll

llvm/test/CodeGen/X86/vec_usubo.ll

llvm/test/CodeGen/X86/vector-bitreverse.ll

llvm/test/CodeGen/X86/vector-compare-results.ll

llvm/test/CodeGen/X86/vector-fshl-128.ll

llvm/test/CodeGen/X86/vector-fshl-256.ll

llvm/test/CodeGen/X86/vector-fshl-rot-256.ll

llvm/test/CodeGen/X86/vector-fshr-128.ll

llvm/test/CodeGen/X86/vector-fshr-256.ll

llvm/test/CodeGen/X86/vector-fshr-rot-256.ll

llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll

llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

llvm/test/CodeGen/X86/vector-interleave.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll

llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll

llvm/test/CodeGen/X86/vector-mulfix-legalize.ll

llvm/test/CodeGen/X86/vector-reduce-add-sext.ll

llvm/test/CodeGen/X86/vector-reduce-fmax.ll

llvm/test/CodeGen/X86/vector-reduce-fmin.ll

llvm/test/CodeGen/X86/vector-reduce-mul.ll

llvm/test/CodeGen/X86/vector-reduce-umax.ll

llvm/test/CodeGen/X86/vector-reduce-umin.ll

llvm/test/CodeGen/X86/vector-rotate-256.ll

llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll

llvm/test/CodeGen/X86/vector-shuffle-v192.ll

llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll

llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll

llvm/test/CodeGen/X86/vector-trunc-math.ll

llvm/test/CodeGen/X86/vector-trunc-packus.ll

llvm/test/CodeGen/X86/vector-trunc-ssat.ll

llvm/test/CodeGen/X86/vector-trunc-usat.ll

llvm/test/CodeGen/X86/vector-zext.ll

llvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll

llvm/test/CodeGen/X86/vselect-minmax.ll

llvm/test/CodeGen/X86/vselect-packss.ll

llvm/test/CodeGen/X86/x86-cmov-converter.ll

llvm/test/CodeGen/X86/x86-interleaved-access.ll

llvm/test/CodeGen/X86/znver3-gather.ll