[LLVM][ARM] Remove options for armv2, 2A, 3 and 3M

[DavidSpickett]

Summary

Fixes #57486

These pre v4 architectures are not specifically supported
by codegen. As demonstrated in the linked issue.

GCC has not supported 3M since GCC 9 and presumably
2 and 2A earlier than that. So we are aligned in that sense.

(see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2abd6e34fcf3bd9f9ffafcaa47cdc3ed443f9add)

This removes the options and associated testing.

The Pre_v4 build attribute remains mainly because its absence
would be more confusing. It will not be used other than to
complete the list of build attributes as shown in the ABI.

https://github.com/ARM-software/abi-aa/blob/main/addenda32/addenda32.rst#3352the-target-related-attributes

[DavidSpickett]

https://github.com/llvm/llvm-project/issues/57486

[DavidSpickett]

The remaining reference in the repo is a #define in openmp/runtime/src/kmp_platform.h which seems harmless.

[peter.smith]

LGTM. GCC no longer supports Arm architecture prior to v4 so it is likely the alternative of adding support for v3 is not worth it. The only Arm machines running v2 are likely to be the Acorn Archimedes family, these have their own object file format so are unlikely to benefit from LLVM support.

Agree that the openmp reference looks harmless.

Will be worth waiting to see if Nick has any objections.

[nickdesaulniers]

For the Linux kernel, we're only building v5+ continuously.

It looks like the Linux kernel supports v4+ and v3m (for Acorn Risc-PC (Intel StrongARM(R) SA-110)). We've never been able to build that target, and it's not high ROI to do so.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/Makefile#n74

GCC no longer supports Arm architecture prior to v4 so it is likely the alternative of adding support for v3 is not worth it.

Oh, looks like the kernel already has a check for (6 <= GCC < 9.1), so there's no risk of breakage on our side. Thanks for the heads up though!
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2abd6e34fcf3bd9f9ffafcaa47cdc3ed443f9add

Consider amending the commit message to mention the specific version of GCC that support for v3- was removed from.

[DavidSpickett]

This is probably overkill but I posted an RFC just in case https://discourse.llvm.org/t/rfc-removal-of-armv2-2a-3-3m-target-options/65040. Like I said, no rush to land this.

[rengolin]

Agree. Even 10 years ago we made the concerted effort not to care about pre-v4, so I'd be a little surprised if people are actually using modern clang to target those platforms.

Projects that rely on it can work in the same way as gcc and pick an older version of the toolchains.

[DavidSpickett]

1:38 AM <arnd> might be good to take them out here as well

So I looked into this. Here are the Arm architectures that clang has that
gcc doesn't:
"armv5tej" Not in GCC, j = jazelle
"armv7k" Apple Watch S1
"armv7s" // iPhone 5
"xscale"

(minus some very new ones that are just because I used trunk clang)

These are the gcc architectures that clang doesn't have:
"armv6j"
"armv6s-m"
"armv6z"
"armv6zk"
"armv7"

So a random grab bag of v6 and 7 on both sides. Not worth disturbing that
now.

Arnd picked out jazelle. GCC doesn't list armv5tej but it does accept it
https://godbolt.org/z/cazcbfjGY. For armv6j clang doesn't list it but it
also does accept it https://godbolt.org/z/aEKfnojTY.

llvm's support for jazelle is a single instruction "bxj" which is a branch
exchange, but for jazelle (
https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/bxj
).
Which makes some sense. If you had that one instruction you could compile
99% of the code with public toolchains, then the rest with some tool from
Arm, I guess. GCC appears to have done the same.

So targets wise I think things are fine as is unless a v6 enthusiast tries
to use clang sometime.

For jazelle the bxj instruction appears to be present on non jazelle
processors, and can be used as a normal bx in ThumbEE. The code to
implement it and the armv5tej target is minimal and compact so I think we
keep it for now.

[rengolin]

I think we can safely say that we care less about jazelle than we care about armv1/2/3, so feel free to ignore that, too.

clang/docs/ReleaseNotes.rst

 - Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk.
 
 DWARF Support in Clang
 ----------------------
 
 Arm and AArch64 Support in Clang
 --------------------------------
 
+- `-march` values for targeting armv2, armv2A, armv3 and armv3M have been removed.
+  Their presence gave the impression that Clang can correctly generate code for
+  them, which it cannot.
+
 Floating Point Support in Clang
 -------------------------------
 
 Internal API Changes
 --------------------
 
 Build System Changes
 --------------------

llvm/docs/ReleaseNotes.rst

 ------------------------------
 
 Changes to the AMDGPU Backend
 -----------------------------
 
 Changes to the ARM Backend
 --------------------------
 
+* Support for targeting armv2, armv2A, armv3 and armv3M has been removed.
+  LLVM did not, and was not ever likely to generate correct code for those
+  architecture versions so their presence was misleading.
+
 Changes to the AVR Backend
 --------------------------
 
 * ...
 
 Changes to the DirectX Backend
 ------------------------------
 

llvm/include/llvm/Support/ARMTargetParser.def

 ARM_FPU("softvfp", FK_SOFTVFP, FPUVersion::NONE, NeonSupportLevel::None, FPURestriction::None)
 #undef ARM_FPU
 
 #ifndef ARM_ARCH
 #define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT)
 #endif
 ARM_ARCH("invalid", INVALID, "", "",
           ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv2", ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4,
-          FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv2a", ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4,
-          FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv3", ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4,
-          FK_NONE, ARM::AEK_NONE)
-ARM_ARCH("armv3m", ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4,
-          FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("armv4", ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4,
           FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("armv4t", ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T,
           FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("armv5t", ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T,
           FK_NONE, ARM::AEK_NONE)
 ARM_ARCH("armv5te", ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE,
           FK_NONE, ARM::AEK_DSP)

llvm/lib/Support/ARMTargetParser.cpp

ARM::ArchKind ARM::parseArch(StringRef Arch) {
   }
   return ArchKind::INVALID;
 }
 
 // Version number (ex. v7 = 7).
 unsigned ARM::parseArchVersion(StringRef Arch) {
   Arch = getCanonicalArchName(Arch);
   switch (parseArch(Arch)) {
-  case ArchKind::ARMV2:
-  case ArchKind::ARMV2A:
-    return 2;
-  case ArchKind::ARMV3:
-  case ArchKind::ARMV3M:
-    return 3;
   case ArchKind::ARMV4:
   case ArchKind::ARMV4T:
     return 4;
   case ArchKind::ARMV5T:
   case ArchKind::ARMV5TE:
   case ArchKind::IWMMXT:
   case ArchKind::IWMMXT2:
   case ArchKind::XSCALE:
ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
   case ArchKind::ARMV8_6A:
   case ArchKind::ARMV8_7A:
   case ArchKind::ARMV8_8A:
   case ArchKind::ARMV9A:
   case ArchKind::ARMV9_1A:
   case ArchKind::ARMV9_2A:
   case ArchKind::ARMV9_3A:
     return ProfileKind::A;
-  case ArchKind::ARMV2:
-  case ArchKind::ARMV2A:
-  case ArchKind::ARMV3:
-  case ArchKind::ARMV3M:
   case ArchKind::ARMV4:
   case ArchKind::ARMV4T:
   case ArchKind::ARMV5T:
   case ArchKind::ARMV5TE:
   case ArchKind::ARMV5TEJ:
   case ArchKind::ARMV6:
   case ArchKind::ARMV6K:
   case ArchKind::ARMV6T2:

llvm/lib/Target/ARM/ARM.td

 class ProcNoItin<string Name, list<SubtargetFeature> Features>
   : Processor<Name, NoItineraries, Features>;
 
 
 //===----------------------------------------------------------------------===//
 // ARM architectures
 //
 
-def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
-
-def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
-
-def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
-
-def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
-
 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 
 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 
 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 
 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 

llvm/lib/Target/ARM/ARMSubtarget.h

protected:
   enum ARMProcClassEnum {
     None,
 
     AClass,
     MClass,
     RClass
   };
   enum ARMArchEnum {
-    ARMv2,
-    ARMv2a,
-    ARMv3,
-    ARMv3m,
     ARMv4,
     ARMv4t,
     ARMv5,
     ARMv5t,
     ARMv5te,
     ARMv5tej,
     ARMv6,
     ARMv6k,

llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

void ARMTargetELFStreamer::emitArchDefaultAttributes() {
   S.setAttributeItem(CPU_name, ARM::getCPUAttr(Arch), false);
 
   if (EmittedArch == ARM::ArchKind::INVALID)
     S.setAttributeItem(CPU_arch, ARM::getArchAttr(Arch), false);
   else
     S.setAttributeItem(CPU_arch, ARM::getArchAttr(EmittedArch), false);
 
   switch (Arch) {
-  case ARM::ArchKind::ARMV2:
-  case ARM::ArchKind::ARMV2A:
-  case ARM::ArchKind::ARMV3:
-  case ARM::ArchKind::ARMV3M:
   case ARM::ArchKind::ARMV4:
     S.setAttributeItem(ARM_ISA_use, Allowed, false);
     break;
 
   case ARM::ArchKind::ARMV4T:
   case ARM::ArchKind::ARMV5T:
   case ARM::ArchKind::XSCALE:
   case ARM::ArchKind::ARMV5TE:

llvm/test/MC/ARM/directive-arch-armv2.s

-@ Test the .arch directive for armv2
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv2 architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN:   | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
-  .syntax unified
-  .arch armv2
-
-@ CHECK-ASM:  .arch armv2
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 2
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_arch
-@ CHECK-ATTR:     Description: Pre-v4
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: ARM_ISA_use
-@ CHECK-ATTR:     Description: Permitted
-@ CHECK-ATTR:   }
-@ CHECK-ATTR: }
-

llvm/test/MC/ARM/directive-arch-armv2a.s

-@ Test the .arch directive for armv2a
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv2a architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN:   | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
-  .syntax unified
-  .arch armv2a
-
-@ CHECK-ASM:  .arch armv2a
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 2A
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_arch
-@ CHECK-ATTR:     Description: Pre-v4
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: ARM_ISA_use
-@ CHECK-ATTR:     Description: Permitted
-@ CHECK-ATTR:   }
-@ CHECK-ATTR: }
-

llvm/test/MC/ARM/directive-arch-armv3.s

-@ Test the .arch directive for armv3
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv3 architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN:   | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
-  .syntax unified
-  .arch armv3
-
-@ CHECK-ASM:  .arch armv3
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 3
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_arch
-@ CHECK-ATTR:     Description: Pre-v4
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: ARM_ISA_use
-@ CHECK-ATTR:     Description: Permitted
-@ CHECK-ATTR:   }
-@ CHECK-ATTR: }
-

llvm/test/MC/ARM/directive-arch-armv3m.s

-@ Test the .arch directive for armv3m
-
-@ This test case will check the default .ARM.attributes value for the
-@ armv3m architecture.
-
-@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \
-@ RUN:   | FileCheck %s -check-prefix CHECK-ASM
-@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \
-@ RUN:   | llvm-readobj --arch-specific - | FileCheck %s -check-prefix CHECK-ATTR
-
-  .syntax unified
-  .arch armv3m
-
-@ CHECK-ASM:  .arch armv3m
-
-@ CHECK-ATTR: FileAttributes {
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_name
-@ CHECK-ATTR:     Value: 3M
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: CPU_arch
-@ CHECK-ATTR:     Description: Pre-v4
-@ CHECK-ATTR:   }
-@ CHECK-ATTR:   Attribute {
-@ CHECK-ATTR:     TagName: ARM_ISA_use
-@ CHECK-ATTR:     Description: Permitted
-@ CHECK-ATTR:   }
-@ CHECK-ATTR: }
-

llvm/unittests/Support/TargetParserTest.cpp

 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 #include <string>
 
 using namespace llvm;
 
 namespace {
 const char *ARMArch[] = {
-    "armv2",       "armv2a",         "armv3",       "armv3m",    "armv4",
-    "armv4t",      "armv5",          "armv5t",      "armv5e",    "armv5te",
-    "armv5tej",    "armv6",          "armv6j",      "armv6k",    "armv6hl",
-    "armv6t2",     "armv6kz",        "armv6z",      "armv6zk",   "armv6-m",
-    "armv6m",      "armv6sm",        "armv6s-m",    "armv7-a",   "armv7",
-    "armv7a",      "armv7ve",        "armv7hl",     "armv7l",    "armv7-r",
-    "armv7r",      "armv7-m",        "armv7m",      "armv7k",    "armv7s",
-    "armv7e-m",    "armv7em",        "armv8-a",     "armv8",     "armv8a",
-    "armv8l",      "armv8.1-a",      "armv8.1a",    "armv8.2-a", "armv8.2a",
-    "armv8.3-a",   "armv8.3a",       "armv8.4-a",   "armv8.4a",  "armv8.5-a",
-    "armv8.5a",    "armv8.6-a",      "armv8.6a",    "armv8.7-a", "armv8.7a",
-    "armv8.8-a",   "armv8.8a",       "armv8-r",     "armv8r",    "armv8-m.base",
-    "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",    "iwmmxt2",
-    "xscale",      "armv8.1-m.main", "armv9-a",     "armv9",     "armv9a",
-    "armv9.1-a",   "armv9.1a",       "armv9.2-a",   "armv9.2a",
+    "armv4",        "armv4t",      "armv5",          "armv5t",      "armv5e",
+    "armv5te",      "armv5tej",    "armv6",          "armv6j",      "armv6k",
+    "armv6hl",      "armv6t2",     "armv6kz",        "armv6z",      "armv6zk",
+    "armv6-m",      "armv6m",      "armv6sm",        "armv6s-m",    "armv7-a",
+    "armv7",        "armv7a",      "armv7ve",        "armv7hl",     "armv7l",
+    "armv7-r",      "armv7r",      "armv7-m",        "armv7m",      "armv7k",
+    "armv7s",       "armv7e-m",    "armv7em",        "armv8-a",     "armv8",
+    "armv8a",       "armv8l",      "armv8.1-a",      "armv8.1a",    "armv8.2-a",
+    "armv8.2a",     "armv8.3-a",   "armv8.3a",       "armv8.4-a",   "armv8.4a",
+    "armv8.5-a",    "armv8.5a",    "armv8.6-a",      "armv8.6a",    "armv8.7-a",
+    "armv8.7a",     "armv8.8-a",   "armv8.8a",       "armv8-r",     "armv8r",
+    "armv8-m.base", "armv8m.base", "armv8-m.main",   "armv8m.main", "iwmmxt",
+    "iwmmxt2",      "xscale",      "armv8.1-m.main", "armv9-a",     "armv9",
+    "armv9a",       "armv9.1-a",   "armv9.1a",       "armv9.2-a",   "armv9.2a",
 };
 
 template <ARM::ISAKind ISAKind>
 std::string FormatExtensionFlags(uint64_t Flags) {
   std::vector<StringRef> Features;
 
   if (ISAKind == ARM::ISAKind::AARCH64) {
     // AEK_NONE is not meant to be shown to the user so the target parser
bool testARMArch(StringRef Arch, StringRef DefaultCPU, StringRef SubArch,
   Result &= ARM::getDefaultCPU(Arch).equals(DefaultCPU);
   Result &= ARM::getSubArch(AK).equals(SubArch);
   Result &= (ARM::getArchAttr(AK) == ArchAttr);
   return Result;
 }
 
 TEST(TargetParserTest, testARMArch) {
   EXPECT_TRUE(
-      testARMArch("armv2", "generic", "v2", ARMBuildAttrs::CPUArch::Pre_v4));
-  EXPECT_TRUE(
-      testARMArch("armv2a", "generic", "v2a", ARMBuildAttrs::CPUArch::Pre_v4));
-  EXPECT_TRUE(
-      testARMArch("armv3", "generic", "v3", ARMBuildAttrs::CPUArch::Pre_v4));
-  EXPECT_TRUE(
-      testARMArch("armv3m", "generic", "v3m", ARMBuildAttrs::CPUArch::Pre_v4));
-  EXPECT_TRUE(
       testARMArch("armv4", "strongarm", "v4",
                           ARMBuildAttrs::CPUArch::v4));
   EXPECT_TRUE(
       testARMArch("armv4t", "arm7tdmi", "v4t",
                           ARMBuildAttrs::CPUArch::v4T));
   EXPECT_TRUE(
       testARMArch("armv5t", "arm10tdmi", "v5",
                           ARMBuildAttrs::CPUArch::v5T));
TEST(TargetParserTest, testARMExtension) {
   EXPECT_FALSE(testARMExtension("cortex-a75",
                                 ARM::ArchKind::INVALID, "fp16fml"));
   EXPECT_FALSE(testARMExtension("cortex-r52",
                                 ARM::ArchKind::INVALID, "ras"));
   EXPECT_FALSE(testARMExtension("iwmmxt", ARM::ArchKind::INVALID, "crc"));
   EXPECT_FALSE(testARMExtension("xscale", ARM::ArchKind::INVALID, "crc"));
   EXPECT_FALSE(testARMExtension("swift", ARM::ArchKind::INVALID, "crc"));
 
-  EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2, "thumb"));
-  EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV2A, "thumb"));
-  EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3, "thumb"));
-  EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV3M, "thumb"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4, "dsp"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV4T, "dsp"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5T, "simd"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5TE, "simd"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV5TEJ, "simd"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV6, "crypto"));
   EXPECT_FALSE(testARMExtension("generic", ARM::ArchKind::ARMV6K, "crypto"));
   EXPECT_FALSE(testARMExtension("generic",