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- User Since
- Nov 12 2020, 2:35 AM (85 w, 6 d)
Yesterday
Mon, Jul 4
Tue, Jun 28
Seems straight forward.
Sat, Jun 25
But for now you should wait for @MyDeveloperDay that he at least removes the changes needed, or state what you have to change, or even better accept it.
Fri, Jun 24
Thu, Jun 23
Wed, Jun 22
Tue, Jun 21
Mon, Jun 20
Fri, Jun 17
Nice work adding the capability to the dump script.
Thu, Jun 16
Wed, Jun 15
Could you please either directly link to the github issue or better use llvm.org/pr55810 than just #55810 ?
Tue, Jun 14
Mon, Jun 13
Wed, Jun 8
Jun 5 2022
Jun 3 2022
Jun 2 2022
Can there be a test case, not related to Verilog? Or do we need to wait until you pump up the support for that?
Jun 1 2022
May 31 2022
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May 7 2022
For me there needs no bug report, but could you comment on the misformatting without the patch?
May 6 2022
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May 1 2022
Apr 28 2022
I currently don't know exactly how isSimpleTypeSpecifier works, but what is with
auto x = Foo * []{return 5;}();
auto x = Foo * *[]{static y = 5; return &y;}();
Apr 27 2022
Apr 26 2022
Apr 24 2022
There seem to be failing tests. Did you run the FormatTests?
Apr 22 2022
could you please reupload your patch with the full diff context? And please add a regression test.
Apr 21 2022
No I think it is a step in the right direction. It will help in common cases, and I still don't know when I will have the time to work on that.
But you are very welcome to join the review, and of course adding patches. :)
Not yet: https://reviews.llvm.org/D120034
As this is still on my todo list: Have you considered
concept X = Bar<5 < 4, 5 > 8>; concept X = Bar<5 < 4, false>;
Or stuff like that?
Apr 12 2022
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Mar 31 2022
Mar 30 2022
I cannot view the diff between the last two revisions:
Mar 28 2022
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Mar 23 2022
Mar 22 2022
Just a side note, I often get this on your changes:
Unhandled Exception ("Exception")
Found unknown intradiff source line, expected a line beginning with "+", "-", or " " (space): \ No newline at end of file
.
Just a formality.