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Differential D132999

[RISCV][CostModel] Add cost model for integer abs
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Authored by Miss_Grape on Aug 31 2022, 12:34 AM.

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craig.topper
reames
Commits
rGf3408739da33: [RISCV][CostModel] Add cost model for integer abs

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Miss_Grape created this revision.Aug 31 2022, 12:34 AM
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Miss_Grape requested review of this revision.Aug 31 2022, 12:34 AM
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Miss_Grape updated this revision to Diff 456882.Aug 31 2022, 12:58 AM
Miss_Grape retitled this revision from [RISCV][CostModel] Add test coverage for integer abs to [RISCV][CostModel] Add cost model for integer abs.
Herald added a subscriber: hiraditya. · View Herald TranscriptAug 31 2022, 12:58 AM
Harbormaster completed remote builds in B184305: Diff 456882.Aug 31 2022, 1:41 AM
reames resigned from this revision.Aug 31 2022, 2:25 PM
Miss_Grape edited reviewers, added: craig.topper; removed: reames.Aug 31 2022, 5:52 PM
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Miss_Grape added a comment.Sep 8 2022, 12:57 AM

ping

Miss_Grape added a reviewer: reames.Sep 8 2022, 3:37 AM
craig.topper added inline comments.Sep 8 2022, 3:23 PM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
889

There an implicit fallthrough here. You need a break;

Miss_Grape updated this revision to Diff 459956.Sep 13 2022, 7:10 PM

address the comment

Miss_Grape marked an inline comment as done.Sep 13 2022, 7:10 PM
Harbormaster completed remote builds in B186514: Diff 459956.Sep 13 2022, 7:57 PM
craig.topper added inline comments.Sep 13 2022, 9:38 PM
llvm/test/Analysis/CostModel/RISCV/abs.ll
28

There's an extra . after nx here

Miss_Grape updated this revision to Diff 460623.Sep 15 2022, 8:35 PM
Miss_Grape marked an inline comment as done.
Harbormaster completed remote builds in B187042: Diff 460623.Sep 15 2022, 9:07 PM
Miss_Grape added a comment.Sep 20 2022, 8:06 PM

ping

Miss_Grape added a comment.Jan 3 2023, 5:51 PM

ping

craig.topper accepted this revision.Jan 3 2023, 5:52 PM

LGTM

This revision is now accepted and ready to land.Jan 3 2023, 5:52 PM
This revision was landed with ongoing or failed builds.Jan 8 2023, 7:47 PM
Closed by commit rGf3408739da33: [RISCV][CostModel] Add cost model for integer abs (authored by Miss_Grape). · Explain Why
This revision was automatically updated to reflect the committed changes.
Miss_Grape added a commit: rGf3408739da33: [RISCV][CostModel] Add cost model for integer abs.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
9 lines
test/
Analysis/
CostModel/
RISCV/
117 lines

Diff 487265

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show First 20 Lines • Show All 874 Lines • ▼ Show 20 LinesRISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
case Intrinsic::ssub_sat: case Intrinsic::ssub_sat:
case Intrinsic::uadd_sat: case Intrinsic::uadd_sat:
case Intrinsic::usub_sat: { case Intrinsic::usub_sat: {
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector()) if (ST->hasVInstructions() && LT.second.isVector())
return LT.first; return LT.first;
break; break;
} }
case Intrinsic::abs: {
auto LT = getTypeLegalizationCost(RetTy);
if (ST->hasVInstructions() && LT.second.isVector()) {
// vrsub.vi v10, v8, 0
// vmax.vv v8, v8, v10
return LT.first * 2;
}
craig.topperUnsubmitted
Done
ReplyInline Actions

There an implicit fallthrough here. You need a break;

craig.topper: There an implicit fallthrough here. You need a `break;`
break;
}
// TODO: add more intrinsic // TODO: add more intrinsic
case Intrinsic::experimental_stepvector: { case Intrinsic::experimental_stepvector: {
unsigned Cost = 1; // vid unsigned Cost = 1; // vid
auto LT = getTypeLegalizationCost(RetTy); auto LT = getTypeLegalizationCost(RetTy);
return Cost + (LT.first - 1); return Cost + (LT.first - 1);
} }
case Intrinsic::vp_rint: { case Intrinsic::vp_rint: {
// RISC-V target uses at least 5 instructions to lower rounding intrinsics. // RISC-V target uses at least 5 instructions to lower rounding intrinsics.
▲ Show 20 Lines • Show All 602 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/RISCV/abs.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 | FileCheck %s
; Check that we don't crash querying costs when vectors are not enabled.
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=riscv64
declare <2 x i64> @llvm.abs.v2i64(<2 x i64>, i1)
declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)
declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
declare <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64>, i1)
declare <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64>, i1)
declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)
declare <vscale x 2 x i32> @llvm.abs.nxv2i32(<vscale x 2 x i32>, i1)
declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)
declare <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32>, i1)
declare <vscale x 16 x i32> @llvm.abs.nxv16i32(<vscale x 16 x i32>, i1)
declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)
declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
declare <32 x i16> @llvm.abs.v32i16(<32 x i16>, i1)
declare <vscale x 2 x i16> @llvm.abs.nxv2i16(<vscale x 2 x i16>, i1)
declare <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16>, i1)
craig.topperUnsubmitted
Done
ReplyInline Actions

There's an extra . after nx here

craig.topper: There's an extra `.` after `nx` here
declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)
declare <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16>, i1)
declare <vscale x 32 x i16> @llvm.abs.nxv32i16(<vscale x 32 x i16>, i1)
declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
declare <4 x i8> @llvm.abs.v4i8(<4 x i8>, i1)
declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1)
declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1)
declare <64 x i8> @llvm.abs.v64i8(<64 x i8>, i1)
declare <vscale x 8 x i8> @llvm.abs.nxv8i8(<vscale x 8 x i8>, i1)
declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)
declare <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8>, i1)
declare <vscale x 64 x i8> @llvm.abs.nxv64i8(<vscale x 64 x i8>, i1)
define i32 @abs(i32 %arg) {
; CHECK-LABEL: 'abs'
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = call <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %7 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call <vscale x 2 x i32> @llvm.abs.nxv2i32(<vscale x 2 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %13 = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call <vscale x 16 x i32> @llvm.abs.nxv16i32(<vscale x 16 x i32> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %15 = call <2 x i16> @llvm.abs.v2i16(<2 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %16 = call <4 x i16> @llvm.abs.v4i16(<4 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %17 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %18 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %19 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %20 = call <vscale x 2 x i16> @llvm.abs.nxv2i16(<vscale x 2 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %21 = call <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %22 = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %23 = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %24 = call <vscale x 32 x i16> @llvm.abs.nxv32i16(<vscale x 32 x i16> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %25 = call <8 x i8> @llvm.abs.v8i8(<8 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %26 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %27 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %28 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %29 = call <vscale x 8 x i8> @llvm.abs.nxv8i8(<vscale x 8 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %30 = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %31 = call <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %32 = call <vscale x 64 x i8> @llvm.abs.nxv64i8(<vscale x 64 x i8> undef, i1 false)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
;
call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false)
call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> undef, i1 false)
call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> undef, i1 false)
call <vscale x 8 x i64> @llvm.abs.nxv8i64(<vscale x 8 x i64> undef, i1 false)
call <2 x i32> @llvm.abs.v2i32(<2 x i32> undef, i1 false)
call <4 x i32> @llvm.abs.v4i32(<4 x i32> undef, i1 false)
call <8 x i32> @llvm.abs.v8i32(<8 x i32> undef, i1 false)
call <16 x i32> @llvm.abs.v16i32(<16 x i32> undef, i1 false)
call <vscale x 2 x i32> @llvm.abs.nxv2i32(<vscale x 2 x i32> undef, i1 false)
call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> undef, i1 false)
call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> undef, i1 false)
call <vscale x 16 x i32> @llvm.abs.nxv16i32(<vscale x 16 x i32> undef, i1 false)
call <2 x i16> @llvm.abs.v2i16(<2 x i16> undef, i1 false)
call <4 x i16> @llvm.abs.v4i16(<4 x i16> undef, i1 false)
call <8 x i16> @llvm.abs.v8i16(<8 x i16> undef, i1 false)
call <16 x i16> @llvm.abs.v16i16(<16 x i16> undef, i1 false)
call <32 x i16> @llvm.abs.v32i16(<32 x i16> undef, i1 false)
call <vscale x 2 x i16> @llvm.abs.nxv2i16(<vscale x 2 x i16> undef, i1 false)
call <vscale x 4 x i16> @llvm.abs.nxv4i16(<vscale x 4 x i16> undef, i1 false)
call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> undef, i1 false)
call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> undef, i1 false)
call <vscale x 32 x i16> @llvm.abs.nxv32i16(<vscale x 32 x i16> undef, i1 false)
call <8 x i8> @llvm.abs.v8i8(<8 x i8> undef, i1 false)
call <16 x i8> @llvm.abs.v16i8(<16 x i8> undef, i1 false)
call <32 x i8> @llvm.abs.v32i8(<32 x i8> undef, i1 false)
call <64 x i8> @llvm.abs.v64i8(<64 x i8> undef, i1 false)
call <vscale x 8 x i8> @llvm.abs.nxv8i8(<vscale x 8 x i8> undef, i1 false)
call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> undef, i1 false)
call <vscale x 32 x i8> @llvm.abs.nxv32i8(<vscale x 32 x i8> undef, i1 false)
call <vscale x 64 x i8> @llvm.abs.nxv64i8(<vscale x 64 x i8> undef, i1 false)
ret i32 undef
}
No newline at end of file