[RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.

[craig.topper]

Summary

This builds on D132771 to invert (setlt 0, X) to (setlt X, 1) and
vice versa.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9210

I think we can generalize this for any constant operand where adding one doesn't overflow? If so, mind doing that in a follow up?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9210

Its more complicated because the constant on the LHS can't be folded into the instruction. 0 is special because it will select x0. But I'll try to see if there is anything that makes sense.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9210

Good point on the constant LHS bit. Hadn't considered that.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static SDValue tryDemorganOfBooleanCondition(SDValue Cond, SelectionDAG &DAG) {
   if (!SetCCOpVT.isScalarInteger())
     return SDValue();
 
   ISD::CondCode CCVal = cast<CondCodeSDNode>(Setcc.getOperand(2))->get();
   if (ISD::isIntEqualitySetCC(CCVal)) {
     CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
     Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(0),
                          Setcc.getOperand(1), CCVal);
+  } else if (CCVal == ISD::SETLT && isNullConstant(Setcc.getOperand(0))) {
+    // Invert (setlt 0, X) by converting to (setlt X, 1).
+    Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(1),
+                         DAG.getConstant(1, SDLoc(Setcc), VT), CCVal);
+  } else if (CCVal == ISD::SETLT && isOneConstant(Setcc.getOperand(1))) {
+    // (setlt X, 1) by converting to (setlt 0, X).
+    Setcc = DAG.getSetCC(SDLoc(Setcc), VT,
+                         DAG.getConstant(0, SDLoc(Setcc), VT),
+                         Setcc.getOperand(0), CCVal);
   } else
     return SDValue();
 
   unsigned Opc = IsAnd ? ISD::OR : ISD::AND;
   return DAG.getNode(Opc, SDLoc(Cond), VT, Setcc, Xor.getOperand(0));
 }
 
 // Perform common combines for BR_CC and SELECT_CC condtions.

llvm/test/CodeGen/RISCV/setcc-logic.ll

 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
 ; RV32I-LABEL: and_sge_gt0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    sgtz a1, a2
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB37_2
+; RV32I-NEXT:    slti a1, a2, 1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB37_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB37_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sge_gt0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    sgtz a1, a2
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB37_2
+; RV64I-NEXT:    slti a1, a2, 1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB37_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB37_2:
 ; RV64I-NEXT:    tail bar@plt
   %4 = icmp sge i32 %0, %1
   %5 = icmp sgt i32 %2, 0
   %6 = and i1 %4, %5
   br i1 %6, label %8, label %7
 
 7:                                                ; preds = %4
   tail call void @bar()
   br label %8
 
 8:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {
 ; RV32I-LABEL: and_sle_lt1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    not a0, a0
-; RV32I-NEXT:    slti a1, a2, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB38_2
+; RV32I-NEXT:    sgtz a1, a2
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB38_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB38_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sle_lt1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    not a0, a0
-; RV64I-NEXT:    slti a1, a2, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB38_2
+; RV64I-NEXT:    sgtz a1, a2
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB38_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB38_2:
 ; RV64I-NEXT:    tail bar@plt
   %4 = icmp sle i32 %0, %1
   %5 = icmp slt i32 %2, 1
   %6 = and i1 %4, %5
   br i1 %6, label %8, label %7
 
 7:                                                ; preds = %4
   tail call void @bar()
   br label %8
 
 8:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) {
 ; RV32I-LABEL: or_uge_gt0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    sgtz a1, a2
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB39_2
+; RV32I-NEXT:    slti a1, a2, 1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB39_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB39_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_uge_gt0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
-; RV64I-NEXT:    xori a0, a0, 1
-; RV64I-NEXT:    sgtz a1, a2
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB39_2
+; RV64I-NEXT:    slti a1, a2, 1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB39_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB39_2:
 ; RV64I-NEXT:    tail bar@plt
   %4 = icmp uge i32 %0, %1
   %5 = icmp sgt i32 %2, 0
   %6 = or i1 %4, %5
   br i1 %6, label %8, label %7
 
 7:                                                ; preds = %4
   tail call void @bar()
   br label %8
 
 8:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) {
 ; RV32I-LABEL: or_ule_lt1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
-; RV32I-NEXT:    slti a1, a2, 1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB40_2
+; RV32I-NEXT:    sgtz a1, a2
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB40_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB40_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_ule_lt1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
-; RV64I-NEXT:    xori a0, a0, 1
-; RV64I-NEXT:    slti a1, a2, 1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB40_2
+; RV64I-NEXT:    sgtz a1, a2
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB40_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB40_2:
 ; RV64I-NEXT:    tail bar@plt
   %4 = icmp ule i32 %0, %1
   %5 = icmp slt i32 %2, 1
   %6 = or i1 %4, %5
   br i1 %6, label %8, label %7
 
 7:                                                ; preds = %4
   tail call void @bar()
   br label %8
 
 8:                                                ; preds = %8, %4
   ret void
 }