This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.
ClosedPublic

Authored by craig.topper on Aug 27 2022, 2:31 PM.

Details

Summary

This builds on D132771 to invert (setlt 0, X) to (setlt X, 1) and
vice versa.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 27 2022, 2:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 27 2022, 2:31 PM
craig.topper requested review of this revision.Aug 27 2022, 2:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 27 2022, 2:31 PM
reames accepted this revision.Aug 29 2022, 11:35 AM

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
9210

I think we can generalize this for any constant operand where adding one doesn't overflow? If so, mind doing that in a follow up?

This revision is now accepted and ready to land.Aug 29 2022, 11:35 AM
craig.topper added inline comments.Aug 29 2022, 11:47 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
9210

Its more complicated because the constant on the LHS can't be folded into the instruction. 0 is special because it will select x0. But I'll try to see if there is anything that makes sense.

reames added inline comments.Aug 29 2022, 11:58 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
9210

Good point on the constant LHS bit. Hadn't considered that.

This revision was landed with ongoing or failed builds.Aug 29 2022, 12:28 PM
This revision was automatically updated to reflect the committed changes.