[RISCV] Apply DeMorgan to (beqz (and/or (seteq), (xor Z, 1))) to remove the xor.

[craig.topper]

Summary

We can rewrite to (bnez (or/and (setne), Z) is Z is 0/1.

Alternatively, we could canonicalize to (xor (or/and (setne), Z), 1)
even if there is no branch. The xor would not always get removed,
but it might enable other DeMorgan combines. I decided to be
conservative for this first patch and require the xor to be removed.

I have a couple other invertible setccs I will add in a follow up
patch.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9142

I think you meant xor Z, 1?

9164

This bit of logic seems like it's getting repeated a bunch, can we factor out a utility? Something like matchLogicalNot?

llvm/test/CodeGen/RISCV/setcc-logic.ll

306

As a follow up, is it worth exploiting the fact that we can skip the snez on the xor and just use the xor result as a non-boolean?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9142

I did indeed.

9164

Just the constant value checking? I don't think matchLogicalNot is a good name for that. I'm not sure what a good name is. isOneOrAllOnes with a bool for AllowAllOnes?

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9164

I was thinking to fold the masked value check in as well. The think we're trying for is to match the logical not of a boolean Z right?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9164

Yes. My thought was that the name only makes sense if the Xor opcode check is also in it.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
   if (ShAmt == 32)
     return SExt;
 
   return DAG.getNode(
       ISD::SHL, DL, MVT::i64, SExt,
       DAG.getConstant(32 - ShAmt, DL, MVT::i64));
 }
 
+// Invert (and/or (set cc X, Y), (xor Z, 1)) to (or/and (set !cc X, Y)), Z) if
+// the result is used as the conditon of a br_cc or select_cc we can invert,
+// inverting the setcc is free, and Z is 0/1. Caller will invert the
+// br_cc/select_cc.
+static SDValue tryDemorganOfBooleanCondition(SDValue Cond, SelectionDAG &DAG) {
+  bool IsAnd = Cond.getOpcode() == ISD::AND;
+  if (!IsAnd && Cond.getOpcode() != ISD::OR)
+    return SDValue();
+
+  if (!Cond.hasOneUse())
+    return SDValue();
+
+  SDValue Setcc = Cond.getOperand(0);
+  SDValue Xor = Cond.getOperand(1);
+  // Canonicalize setcc to LHS.
+  if (Setcc.getOpcode() != ISD::SETCC)
+    std::swap(Setcc, Xor);
+  // LHS should be a setcc and RHS should be an xor.
+  if (Setcc.getOpcode() != ISD::SETCC || !Setcc.hasOneUse() ||
+      Xor.getOpcode() != ISD::XOR || !Xor.hasOneUse())
+    return SDValue();
+
+  // If the condition is an And, SimplifyDemandedBits may have changed
+  // (xor Z, 1) to (not Z).
+  SDValue Xor1 = Xor.getOperand(1);
+  if (!isOneConstant(Xor1) && !(IsAnd && isAllOnesConstant(Xor1)))
+    return SDValue();
+
+  EVT VT = Cond.getValueType();
+  SDValue Xor0 = Xor.getOperand(0);
+
+  // The LHS of the xor needs to be 0/1.
+  APInt Mask = APInt::getBitsSetFrom(VT.getSizeInBits(), 1);
+  if (!DAG.MaskedValueIsZero(Xor0, Mask))
+    return SDValue();
+
+  // We can only invert integer setccs.
+  EVT SetCCOpVT = Setcc.getOperand(0).getValueType();
+  if (!SetCCOpVT.isScalarInteger())
+    return SDValue();
+
+  ISD::CondCode CCVal = cast<CondCodeSDNode>(Setcc.getOperand(2))->get();
+  if (ISD::isIntEqualitySetCC(CCVal)) {
+    CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
+    Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(0),
+                         Setcc.getOperand(1), CCVal);
+  } else
+    return SDValue();
+
+  unsigned Opc = IsAnd ? ISD::OR : ISD::AND;
+  return DAG.getNode(Opc, SDLoc(Cond), VT, Setcc, Xor.getOperand(0));
+}
+
 // Perform common combines for BR_CC and SELECT_CC condtions.
 static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
                        SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
   ISD::CondCode CCVal = cast<CondCodeSDNode>(CC)->get();
   if (!ISD::isIntEqualitySetCC(CCVal))
     return false;
 
   // Fold ((setlt X, Y), 0, ne) -> (X, Y, lt)
static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
   APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
   if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) {
     CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
     CC = DAG.getCondCode(CCVal);
     RHS = DAG.getConstant(0, DL, LHS.getValueType());
     return true;
   }
 
+  if (isNullConstant(RHS)) {
+    if (SDValue NewCond = tryDemorganOfBooleanCondition(LHS, DAG)) {
+      CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
+      CC = DAG.getCondCode(CCVal);
+      LHS = NewCond;
+      return true;
+    }
+  }
+
   return false;
 }
 
 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
 
   // Helper to call SimplifyDemandedBits on an operand of N where only some low

llvm/test/CodeGen/RISCV/setcc-logic.ll

 }
 
 declare void @bar(...)
 
 define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_sge_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB13_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB13_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB13_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sge_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB13_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB13_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB13_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sge i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_sle_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB14_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB14_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB14_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sle_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB14_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB14_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB14_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sle i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_uge_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB15_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB15_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB15_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_uge_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB15_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB15_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB15_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp uge i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ule_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB16_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB16_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB16_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ule_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB16_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB16_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB16_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ule i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_sge_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB17_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB17_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB17_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sge_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB17_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB17_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB17_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sge i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_sle_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB18_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB18_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB18_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_sle_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB18_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB18_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB18_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sle i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_uge_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB19_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB19_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB19_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_uge_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB19_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB19_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB19_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp uge i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ule_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB20_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    or a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB20_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB20_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ule_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
-; RV64I-NEXT:    not a0, a0
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB20_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    or a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB20_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB20_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ule i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_sge_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB21_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB21_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB21_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_sge_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB21_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB21_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB21_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sge i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_sle_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB22_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB22_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB22_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_sle_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB22_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB22_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB22_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sle i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_uge_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB23_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB23_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB23_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_uge_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB23_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB23_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB23_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp uge i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_ule_eq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    seqz a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB24_2
+; RV32I-NEXT:    snez a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB24_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB24_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_ule_eq:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    seqz a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB24_2
+; RV64I-NEXT:    snez a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB24_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ule i32 %0, %1
   %6 = icmp eq i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_sge_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB25_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB25_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_sge_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a0, a1
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB25_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB25_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB25_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sge i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_sle_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slt a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB26_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB26_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_sle_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slt a0, a1, a0
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB26_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB26_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB26_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp sle i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_uge_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a0, a1
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB27_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB27_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB27_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_uge_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a0, a1
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB27_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB27_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB27_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp uge i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: or_ule_ne:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sltu a0, a1, a0
-; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    xor a1, a2, a3
-; RV32I-NEXT:    snez a1, a1
-; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB28_2
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    bnez a0, .LBB28_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: or_ule_ne:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sltu a0, a1, a0
-; RV64I-NEXT:    xori a0, a0, 1
 ; RV64I-NEXT:    xor a1, a2, a3
-; RV64I-NEXT:    snez a1, a1
-; RV64I-NEXT:    or a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB28_2
+; RV64I-NEXT:    seqz a1, a1
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    bnez a0, .LBB28_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB28_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ule i32 %0, %1
   %6 = icmp ne i32 %2, %3
   %7 = or i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_eq_sge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    slt a1, a2, a3
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB29_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB29_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB29_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_eq_sge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    slt a1, a2, a3
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB29_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB29_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB29_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp eq  i32 %0, %1
   %6 = icmp sge i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_eq_sle:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    slt a1, a3, a2
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB30_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB30_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB30_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_eq_sle:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    slt a1, a3, a2
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB30_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB30_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB30_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp eq  i32 %0, %1
   %6 = icmp sle i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_eq_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    sltu a1, a2, a3
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB31_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB31_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB31_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_eq_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    sltu a1, a2, a3
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB31_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB31_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB31_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp eq  i32 %0, %1
   %6 = icmp uge i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_eq_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    sltu a1, a3, a2
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB32_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB32_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB32_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_eq_ule:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    sltu a1, a3, a2
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB32_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB32_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB32_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp eq  i32 %0, %1
   %6 = icmp ule i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ne_sge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    slt a1, a2, a3
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB33_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB33_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB33_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ne_sge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    slt a1, a2, a3
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB33_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB33_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB33_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ne  i32 %0, %1
   %6 = icmp sge i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ne_sle:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    slt a1, a3, a2
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB34_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB34_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB34_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ne_sle:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    slt a1, a3, a2
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB34_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB34_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB34_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ne  i32 %0, %1
   %6 = icmp sle i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ne_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    sltu a1, a2, a3
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB35_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB35_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB35_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ne_uge:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    sltu a1, a2, a3
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB35_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB35_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB35_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ne  i32 %0, %1
   %6 = icmp uge i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }
 
 define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
 ; RV32I-LABEL: and_ne_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
-; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    seqz a0, a0
 ; RV32I-NEXT:    sltu a1, a3, a2
-; RV32I-NEXT:    xori a1, a1, 1
-; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    beqz a0, .LBB36_2
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    bnez a0, .LBB36_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB36_2:
 ; RV32I-NEXT:    tail bar@plt
 ;
 ; RV64I-LABEL: and_ne_ule:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    xor a0, a0, a1
-; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    sltu a1, a3, a2
-; RV64I-NEXT:    xori a1, a1, 1
-; RV64I-NEXT:    and a0, a0, a1
-; RV64I-NEXT:    beqz a0, .LBB36_2
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    bnez a0, .LBB36_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB36_2:
 ; RV64I-NEXT:    tail bar@plt
   %5 = icmp ne  i32 %0, %1
   %6 = icmp ule i32 %2, %3
   %7 = and i1 %5, %6
   br i1 %7, label %9, label %8
 
 8:                                                ; preds = %4
   tail call void @bar()
   br label %9
 
 9:                                                ; preds = %8, %4
   ret void
 }