[RISCV] Refactor performSUBCombine to prepare for D132000.

[craig.topper]

Summary

This refactors the code into a separate function with early returns.
D132000 adds an additional operation to the if/else that selects
NewLHS, but can otherwise share the rest of the code.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (SDValue V = transformAddShlImm(N, DAG, Subtarget))
     return V;
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
   // fold (add (select lhs, rhs, cc, 0, y), x) ->
   //      (select lhs, rhs, cc, x, (add x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
-static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
+// Try to turn a sub boolean RHS and constant LHS into an addi.
+static SDValue combineSubOfBoolean(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  // Require a constant LHS.
+  auto *N0C = dyn_cast<ConstantSDNode>(N0);
+  if (!N0C)
+    return SDValue();
 
-  // Prefer to make this 'add 0/1' rather than 'sub 0/1'
-  // sub constant, 0/1 -> add constant - 1, 1/0
+  // All our optimizations involve subtracting 1 from the immediate and forming
+  // an ADDI. Make sure the new immediate is valid for an ADDI.
+  APInt ImmValMinus1 = N0C->getAPIntValue() - 1;
+  if (!ImmValMinus1.isSignedIntN(12))
+    return SDValue();
+
+  SDValue NewLHS;
+  if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     // (sub constant, (setcc x, y, eq/neq)) ->
     // (add (setcc x, y, neq/eq), constant - 1)
-  auto *N0C = dyn_cast<ConstantSDNode>(N0);
-  if (N0C && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
     EVT SetCCOpVT = N1.getOperand(0).getValueType();
-    if (SetCCOpVT.isInteger() && isIntEqualitySetCC(CCVal)) {
-      EVT VT = N->getValueType(0);
-      APInt ImmValMinus1 = N0C->getAPIntValue() - 1;
-      // If this doesn't form ADDI, the transform won't save any instructions
-      // and may increase the number of constants we need.
-      if (ImmValMinus1.isSignedIntN(12)) {
-        CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
-        SDValue NewN0 = DAG.getSetCC(SDLoc(N1), VT, N1.getOperand(0),
-                                     N1.getOperand(1), CCVal);
-        SDValue NewN1 = DAG.getConstant(ImmValMinus1, SDLoc(N), VT);
-        return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
-      }
-    }
-  }
+    if (!isIntEqualitySetCC(CCVal) || !SetCCOpVT.isInteger())
+      return SDValue();
+    NewLHS =
+        DAG.getSetCC(SDLoc(N1), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
+  } else
+    return SDValue();
+
+  SDValue NewRHS = DAG.getConstant(ImmValMinus1, DL, VT);
+  return DAG.getNode(ISD::ADD, DL, VT, NewLHS, NewRHS);
 
+static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
+  if (SDValue V = combineSubOfBoolean(N, DAG))
+    return V;
+
   // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
   //      (select lhs, rhs, cc, x, (sub x, y))
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and