[RISCV][NFC] Use nested namespace definations.

[jacquesguan]

Summary

Since we use C++17 now, we could use nested namespace definations to simplify code.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

 //===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
 
 #include "llvm/MC/MCFixup.h"
 
 #undef RISCV
 
-namespace llvm {
-namespace RISCV {
+namespace llvm::RISCV {
 enum Fixups {
   // 20-bit fixup corresponding to %hi(foo) for instructions like lui
   fixup_riscv_hi20 = FirstTargetFixupKind,
   // 12-bit fixup corresponding to %lo(foo) for instructions like addi
   fixup_riscv_lo12_i,
   // 12-bit fixup corresponding to %lo(foo) for the S-type store instructions
   fixup_riscv_lo12_s,
   // 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc
enum Fixups {
   // 6-bit fixup corresponding to R_RISCV_SUB6 for local label assignment in
   // DWARF CFA.
   fixup_riscv_sub_6b,
 
   // Used as a sentinel, must be the last
   fixup_riscv_invalid,
   NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
 };
-} // end namespace RISCV
-} // end namespace llvm
+} // end namespace llvm::RISCV
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

static unsigned extractRotateInfo(int64_t Val) {
   unsigned LowerLeadingOnes = countLeadingOnes(Lo_32(Val));
   if (UpperTrailingOnes < 32 &&
       (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
     return 32 - UpperTrailingOnes;
 
   return 0;
 }
 
-namespace llvm {
-namespace RISCVMatInt {
+namespace llvm::RISCVMatInt {
 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   RISCVMatInt::InstSeq Res;
   generateInstSeqImpl(Val, ActiveFeatures, Res);
 
   // If there are trailing zeros, try generating a sign extended constant with
   // no trailing zeros and use a final SLLI to restore them.
   if ((Val & 1) == 0 && Res.size() > 2) {
     unsigned TrailingZeros = countTrailingZeros((uint64_t)Val);
OpndKind Inst::getOpndKind() const {
   case RISCV::SLLI_UW:
   case RISCV::RORI:
   case RISCV::BSETI:
   case RISCV::BCLRI:
     return RISCVMatInt::RegImm;
   }
 }
 
-} // namespace RISCVMatInt
-} // namespace llvm
+} // namespace llvm::RISCVMatInt

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 #include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-isel"
 
-namespace llvm {
-namespace RISCV {
+namespace llvm::RISCV {
 #define GET_RISCVVSSEGTable_IMPL
 #define GET_RISCVVLSEGTable_IMPL
 #define GET_RISCVVLXSEGTable_IMPL
 #define GET_RISCVVSXSEGTable_IMPL
 #define GET_RISCVVLETable_IMPL
 #define GET_RISCVVSETable_IMPL
 #define GET_RISCVVLXTable_IMPL
 #define GET_RISCVVSXTable_IMPL
 #define GET_RISCVMaskedPseudosTable_IMPL
 #include "RISCVGenSearchableTables.inc"
-} // namespace RISCV
-} // namespace llvm
+} // namespace llvm::RISCV
 
 void RISCVDAGToDAGISel::PreprocessISelDAG() {
   SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
 
   bool MadeChange = false;
   while (Position != CurDAG->allnodes_begin()) {
     SDNode *N = &*--Position;
     if (N->use_empty())

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

report_fatal_error(
         Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
   BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
   if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg))
     report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
                              StringRef(RegName) + "\"."));
   return Reg;
 }
 
-namespace llvm {
-namespace RISCVVIntrinsicsTable {
+namespace llvm::RISCVVIntrinsicsTable {
 
 #define GET_RISCVVIntrinsicsTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 
-} // namespace RISCVVIntrinsicsTable
-
-} // namespace llvm
+} // namespace llvm::RISCVVIntrinsicsTable

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 #define GET_INSTRINFO_CTOR_DTOR
 #define GET_INSTRINFO_NAMED_OPS
 #include "RISCVGenInstrInfo.inc"
 
 static cl::opt<bool> PreferWholeRegisterMove(
     "riscv-prefer-whole-register-move", cl::init(false), cl::Hidden,
     cl::desc("Prefer whole register move for vector registers."));
 
-namespace llvm {
-namespace RISCVVPseudosTable {
+namespace llvm::RISCVVPseudosTable {
 
 using namespace RISCV;
 
 #define GET_RISCVVPseudosTable_IMPL
 #include "RISCVGenSearchableTables.inc"
 
-} // namespace RISCVVPseudosTable
-} // namespace llvm
+} // namespace llvm::RISCVVPseudosTable
 
 RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI)
     : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
       STI(STI) {}
 
 MCInst RISCVInstrInfo::getNop() const {
   if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
     return MCInstBuilder(RISCV::C_NOP);