[RISCV] Fold (sub constant, (setcc x, y, eq/neq)) -> (add constant - 1, (setcc x, y, neq/eq))

[liaolucy]

Summary

(setcc x, y, eq/neq) are seqz, snez that set rd = 0/1.

addi is used to process immediate, which can save instructions for load immediate.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8287

Do we need to check that this is the only user of the setcc?

8291

Use ISD::isIntEqualitySetCC(CCVal)

8299

Put these in canonical order with constant on the RHS.

[liaolucy]

Use ISD::isIntEqualitySetCC(CCVal) and put constant on the RHS.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8287

At present, I think only setcc, ensure that rd is only 0/1, I have not found other SDNode have this function.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8287

That wasn’t my question. What if the setcc is used by another instruction other than this sub. Then the original setcc won’t be removed and there will be two setccs with opposite conditions.

[liaolucy]

Address craig.topper's comments and thanks. Add sub is the only user of the setcc.

[liaolucy]

update

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8288

You can use N1.hasOneUse() which should be cheaper. isOnlyUser is more useful if N had multiple operands that could each be N1. We know one operand of N is a constant so N1 can only be used by one operand.

8294

This line has undefined behavior if N0 happens to be 0x8000000000000000.

It's also incorrect if N is type i65 or larger. Probably best to use APInt which will fix both issues.

[liaolucy]

Use N1.hasOneUse(), APInt and dyn_cast

[craig.topper]

LGTM with that change.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

8296

Use DAG.getSetCC then you don't need to call getCondCode.

[liaolucy]

rebase

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineBinOpToReduce(N, DAG))
     return V;
   // fold (add (select lhs, rhs, cc, 0, y), x) ->
   //      (select lhs, rhs, cc, x, (add x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
-  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
-  //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+
+  // Prefer to make this 'add 0/1' rather than 'sub 0/1'
+  // sub constant(!0), 0/1 -> add constant - 1, 1/0
+  // NODE: constant == 0, No redundant instructions are generated.
+  // (sub constant, (setcc x, y, eq/neq)) ->
+  // (add (setcc x, y, neq/eq), constant - 1)
+  auto *Nnz0 = dyn_cast<ConstantSDNode>(N0);
+  if (Nnz0 && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
+    const auto *CC = cast<CondCodeSDNode>(N1->getOperand(2));
+    ISD::CondCode CCVal = CC->get();
+    if (!Nnz0->isZero() && isIntEqualitySetCC(CCVal)) {
+      EVT VT = N->getValueType(0);
+      const APInt &ImmVal = Nnz0->getAPIntValue();
+      SDValue CCInverse =
+          DAG.getCondCode(ISD::getSetCCInverse(CCVal, N0.getValueType()));
+      SDValue NewN0 = DAG.getNode(ISD::SETCC, SDLoc(N), VT, N1->getOperand(0),
+                                  N1->getOperand(1), CCInverse);
+      SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);
+      return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
+    }
+  }
+
+  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
+  //      (select lhs, rhs, cc, x, (sub x, y))
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);
   // Pre-promote (i32 (and (srl X, Y), 1)) on RV64 with Zbs without zero
   // extending X. This is safe since we only need the LSB after the shift and

llvm/test/CodeGen/RISCV/setcc-logic.ll

 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    and a0, a1, a0
 ; RV64I-NEXT:    ret
   %a = icmp ne i32 %x, 44
   %b = icmp ne i32 %x, 92
   %r = and i1 %a, %b
   ret i1 %r
 }
+
+define i32 @bar(i32 %n) {
+; RV32I-LABEL: bar:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    addi a0, a0, -9
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    addi a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: bar:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    addi a0, a0, -9
+; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    ret
+entry:
+  %cmp = icmp eq i32 %n, 9
+  %a = select i1 %cmp, i32 1, i32 2
+  ret i32 %a
+}