This is an archive of the discontinued LLVM Phabricator instance.

[RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V
ClosedPublic

Authored by smd on Aug 6 2022, 2:46 PM.

Details

Summary

[6/12] patch series to port HWASAN for riscv64

Depends On D131574

Diff Detail

Event Timeline

smd created this revision.Aug 6 2022, 2:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 6 2022, 2:46 PM
smd added a project: Restricted Project.Aug 6 2022, 3:06 PM
smd published this revision for review.Aug 7 2022, 3:29 AM
craig.topper added inline comments.
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
264

Why do we need to create STI when there's already an STI as a member of this class?

smd updated this revision to Diff 450706.Aug 7 2022, 11:09 PM

Addressing comments

smd added inline comments.Aug 7 2022, 11:10 PM
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
264

Fixed, thanks

Please split RISCVAsmParser/Printer and HWAddressSanitizer into separate patches

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
17

If we change RISCVAsmPrinter, I assume we need to update RISCVAsmParser.cpp and add corresponding tests

llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
919 ↗(On Diff #450706)

we need a few new tests for instumentation

smd retitled this revision from [RISC-V][HWASAN] Add support for HWASAN code instrumentation for RISC-V to [RISC-V][HWASAN] Add support for lowering HWASAN intrinsic for RISC-V.Aug 10 2022, 8:03 AM
smd edited the summary of this revision. (Show Details)
smd updated this revision to Diff 451471.Aug 10 2022, 8:03 AM

Addressing comments

smd added a comment.Aug 10 2022, 8:10 AM

Please split RISCVAsmParser/Printer and HWAddressSanitizer into separate patches

Fixed, thanks.

RISCVAsmPrinter needs a test for changes in this patch.

smd added a comment.Aug 15 2022, 5:24 AM

RISCVAsmPrinter needs a test for changes in this patch.

The requested tests have been added as part of D131344.
Thanks.

vitalybuka accepted this revision.Aug 15 2022, 10:47 AM

RISCVAsmPrinter needs a test for changes in this patch.

The requested tests have been added as part of D131344.
Thanks.

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll ?
the test essentially validates LowerHWASAN_CHECK_MEMACCESS, and does not relies on the rest of D131344
So the test needs to be moved from D131344 into this patch.

With moved test LGTM in general.
But I have no experience with RISCV, so I didn't look into details of emitted code.

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
120

This "if" looks to random here?
File structure is very different from AArch64 version, so not sure if this is the best place for the code.

This revision is now accepted and ready to land.Aug 15 2022, 10:47 AM
smd added a comment.Aug 16 2022, 11:41 AM

@vitalybuka

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll ?
the test essentially validates LowerHWASAN_CHECK_MEMACCESS, and does not relies on the rest of D131344
So the test needs to be moved from D131344 into this patch.

I believe the same applies to D131575 and basic.ll, where changes to instrumentMemAccessInline are tested?
If so, would you mind me moving hwasan-check-memaccess.ll to this patch and the rest of .ll tests to D131575?
Thanks

@vitalybuka

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll ?
the test essentially validates LowerHWASAN_CHECK_MEMACCESS, and does not relies on the rest of D131344
So the test needs to be moved from D131344 into this patch.

I believe the same applies to D131575 and basic.ll, where changes to instrumentMemAccessInline are tested?
If so, would you mind me moving hwasan-check-memaccess.ll to this patch and the rest of .ll tests to D131575?
Thanks

@vitalybuka

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll ?
the test essentially validates LowerHWASAN_CHECK_MEMACCESS, and does not relies on the rest of D131344
So the test needs to be moved from D131344 into this patch.

I believe the same applies to D131575 and basic.ll, where changes to instrumentMemAccessInline are tested?
If so, would you mind me moving hwasan-check-memaccess.ll to this patch and the rest of .ll tests to D131575?
Thanks

Sure. The logic is simple:

  1. Split functional changes into smaller patches: AsmPrint, Instrumentation, RT ...
  2. Each patch contains tests corresponding to changed functionality

So
test/CodeGen/RISCV/ goes into D131343 (CodeGen patch)
test/Instrumentation/HWAddressSanitizer/RISCV/ into D131575 (Instrumentation patch)

D131344 should keep only compiler-rt/test/hwasan/TestCases/ as they look irrelevant to CodeGen and Instrumentation

smd updated this revision to Diff 453089.Aug 16 2022, 12:01 PM

Addressing comments

vitalybuka accepted this revision.Aug 16 2022, 12:02 PM
jrtc27 added inline comments.Aug 22 2022, 11:01 AM
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
120

lowerRISCVMachineInstrToMCInst seems like the right place for it. That's where PATCHABLE_FUNCTION_ENTER gets handled. Given that this node is a copy of AArch64's and every architecture would presumably use the same thing I do wonder if it should be under TargetOpcode, too...

451

This is what STO_RISCV_VARIANT_CC is for

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
1

Use update_llc_test_checks.py. Also test PIC too if you have PIC-specific code.

3

Redundant, you have -mtriple in the command line

smd updated this revision to Diff 454956.Aug 23 2022, 2:05 PM

Addressing comments

smd added inline comments.Aug 23 2022, 2:13 PM
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
451

If you don't mind, I'd like address that in a separate patch, as I have to go through the discussion on this matter. Thanks

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
1

Fixed, thanks

3

Fixed, thanks

This revision was landed with ongoing or failed builds.Aug 28 2022, 11:23 AM
This revision was automatically updated to reflect the committed changes.

This was committed without addressing all the feedback you were provided

And if you’re committing a significant chunk of code to a backend I don’t think you should be doing so without getting approval from someone who regularly works on the backend

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
24

Surely you need UTC_ARGS
: —disable/—enable around this so it persists across reruns of update_llc_test_checks.py?

59

I do not understand what this comment is saying nor what the following lines are for

smd added a comment.Aug 28 2022, 1:18 PM

@jrtc27 sorry for the mess

This was committed without addressing all the feedback you were provided

What's the best way to fix it: would you like me to revert the commit or address the issues in next patches?

And if you’re committing a significant chunk of code to a backend I don’t think you should be doing so without getting approval from someone who regularly works on the backend

Would you mind me adding you as a reviewer for further patches?

llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
59

tbh, me neither, but this comment was added by update_llc_test_checks.py

Surely you need UTC_ARGS

Let me try this and see if it changes anything

smd edited the summary of this revision. (Show Details)Aug 30 2022, 11:31 PM
smd added a comment.Aug 30 2022, 11:34 PM

@jrtc27 I've created several reviews(D13299{3,4,5}) to address the issues that you mentioned. Could you please take a look? Thanks