[RISC-V][HWASAN] Add intrinsics required for HWASAN support for RISC-V

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Summary

[2/9] patch series to port HWASAN for riscv64

Depends On D131339

[craig.topper]

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

149 ↗

(On Diff #450574)

I think this line probably exceeds 80 characters

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Addressing comments

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llvm/lib/Target/RISCV/RISCVRegisterInfo.td

149 ↗

(On Diff #450574)

Fixed, thanks

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1669–1670

This formatting is not used anywhere in the RISCV backend

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

149 ↗

(On Diff #450574)

Why is this set of registers what it is? This is not a helpful name. It looks like this is in fact the set of GPRs minus RA and all temporary registers other than t0. The AArch64 equivalent has:

// Register set that excludes registers that are reserved for procedure calls.
// This is used for pseudo-instructions that are actually implemented using a
// procedure call.

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Addressing comments

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llvm/lib/Target/RISCV/RISCVRegisterInfo.td

149 ↗

(On Diff #450574)

Thanks for catching this, you're right, there's no need to introduce a new register class like this and GPRJALR should be used instead.

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Addressing comments

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1669–1670

Should be fixed now, thanks.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1669–1670

It is not

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Addressing comments

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llvm/lib/Target/RISCV/RISCVInstrInfo.td

1669–1670

Could you please check this kind of formatting?
If you still find it wrong could you please suggest the proper one, thanks

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 // We lower `trap` to `unimp`, as this causes a hard exception on nearly all
 // systems.
 def : Pat<(trap), (UNIMP)>;
 
 // We lower `debugtrap` to `ebreak`, as this will get the attention of the
 // debugger if possible.
 def : Pat<(debugtrap), (EBREAK)>;
 
+let Predicates = [IsRV64], Uses = [X5],
+    Defs = [X1, X6, X7, X28, X29, X30, X31] in
+def HWASAN_CHECK_MEMACCESS_SHORTGRANULES 
+  : Pseudo<(outs), (ins GPRJALR:$ptr, i32imm:$accessinfo),
+           [(int_hwasan_check_memaccess_shortgranules X5, GPRJALR:$ptr,
+                                                      (i32 timm:$accessinfo))]>;
+
 /// Simple optimization
 def : Pat<(add GPR:$rs1, (AddiPair:$rs2)),
           (ADDI (ADDI GPR:$rs1, (AddiPairImmLarge AddiPair:$rs2)),
                 (AddiPairImmSmall GPR:$rs2))>;
 
 let Predicates = [IsRV64] in {
 // Select W instructions if only the lower 32-bits of the result are used.
 def : Pat<(binop_allwusers<add> GPR:$rs1, (AddiPair:$rs2)),