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[RISCV] Do tail call when parameters are passed by stack
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Authored by StephenFan on Aug 5 2022, 8:14 AM.

Details

Summary

If parameters are passed by stack and their stack offsets are consistent
with stack offsets of caller's passed by stack parameters, tail call
optimization is feasible.

Fix https://github.com/llvm/llvm-project/issues/56908

Diff Detail

Event Timeline

StephenFan created this revision.Aug 5 2022, 8:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2022, 8:14 AM
StephenFan requested review of this revision.Aug 5 2022, 8:14 AM
StephenFan updated this revision to Diff 450295.Aug 5 2022, 8:16 AM

Delete comments.

StephenFan updated this revision to Diff 450299.Aug 5 2022, 8:18 AM

clang-format

I haven't noticed any specific issue so far but these things are fiddly, the patch needs more eye balls.
See if you can think of additional test coverage scenarios that might be relevant. Does this handle, say, when part of a value is passed on a register and part on the stack?

(OT: I just noticed that Phabricator is not syntax highlighting RISCVISelLowering.cpp. Is it because it's too big?)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
11278

Is this for sure the only problematic flag? Having more test coverage of weird scenarios would help.

llvm/test/CodeGen/RISCV/tail-calls.ll
116

Nit: keep the comment but update it to explain that tail call optimization is possible if the stack layout is compatible