[RISCV] Optimize (br_cc (and X, 0x80000000), 0, seteq, dest) on RV64

[craig.topper]

Summary

The 0x80000000 would normally require constant materialization, but
we can replace it with a sext.w to copy bit 31 to bit 63 and use a
sign compare with 0 to test the bit.

We can do something similar for setne and for select_cc which will
eventually becomes a branch. The setne case for select_cc becomes
an srliw instead through other means and I'm not sure it's worth
changing.

I chose sext.w because it's one instruction, srliw would need a
srl+and to be emitted. And a sext.w might be foldable into an earlier
instruction.

We don't want to do this for setcc that won't become a branch because
we don't have a sgez instruction. For those an srliw and an xori is
going to be better. That's probably best done from an isel pattern so
we don't expand and+setcc to srl+and+xor in the DAG.

[reames]

Can't we do something more general here using shifts?

For one bit masks, can't we shift the desired bit to one end and then test? For a left shift, this would be moving the desired bit to test into bit 64 (sign bit) and using the signed comparison as in this patch. For a right shift, this would be moving the desired bit into bit 0, and testing against zero. We do have a snez I believe.

[craig.topper]

In D130099#3665426, @reames wrote:

Can't we do something more general here using shifts?

For one bit masks, can't we shift the desired bit to one end and then test? For a left shift, this would be moving the desired bit to test into bit 64 (sign bit) and using the signed comparison as in this patch. For a right shift, this would be moving the desired bit into bit 0, and testing against zero. We do have a snez I believe.

Right shift doesn’t work without clearing the bits that are above the tested bit. But left shift would work.

[reames]

In D130099#3665984, @craig.topper wrote:

In D130099#3665426, @reames wrote:

Can't we do something more general here using shifts?

For one bit masks, can't we shift the desired bit to one end and then test? For a left shift, this would be moving the desired bit to test into bit 64 (sign bit) and using the signed comparison as in this patch. For a right shift, this would be moving the desired bit into bit 0, and testing against zero. We do have a snez I believe.

Right shift doesn’t work without clearing the bits that are above the tested bit. But left shift would work.

You're right, you'd need an AND 0x1 after the right shift to isolate the bit. Might still be worth doing over materializing the large mask constant - that's at least an LUI + SHL + AND, so SRLI + AND both with immediate operands seems to be slightly better.

But yes, the ability to do the left shift and signed compare is strictly better, so we should do that one. :)

For multiple bit masks, maybe the right shift variant is worth exploring providing the shifted bit mask fits in the immediate encoding. So any mask with set bits separated by less than 12 bits. I don't see a multi-bit mask variant of the left shift one off the top of my head.

[craig.topper]

I'm going to abandon this in favor of a more general single bit AND patch using SLLI implemented in a different place with different tests.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) {
       SDLoc DL(N);
       CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
       SDValue TargetCC = DAG.getCondCode(CCVal);
       RHS = DAG.getConstant(0, DL, LHS.getValueType());
       return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0),
                          {LHS, RHS, TargetCC, TrueV, FalseV});
     }
 
+    // Optimize
+    // (select_cc (and X, 0x80000000), 0, seteq, trueV, falseV) ->
+    // (select_cc (sext_inreg X, i32), 0, setge, trueV, falseV)
+    // And
+    // (select_cc (and X, 0x80000000), 0, setne, trueV, falseV) ->
+    // (select_cc (sext_inreg X, i32), 0, setlt, trueV, falseV)
+    if (Subtarget.is64Bit() && LHS.getValueType() == MVT::i64 &&
+        isNullConstant(RHS) && LHS.getOpcode() == ISD::AND && LHS.hasOneUse() &&
+        isa<ConstantSDNode>(LHS.getOperand(1)) &&
+        LHS.getConstantOperandVal(1) == UINT64_C(0x80000000)) {
+      SDLoc DL(N);
+      CCVal = CCVal == ISD::SETEQ ? ISD::SETGE : ISD::SETLT;
+      SDValue TargetCC = DAG.getCondCode(CCVal);
+      LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64,
+                        LHS.getOperand(0), DAG.getValueType(MVT::i32));
+      return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0),
+                         {LHS, RHS, TargetCC, TrueV, FalseV});
+    }
     break;
   }
   case RISCVISD::BR_CC: {
     SDValue LHS = N->getOperand(1);
     SDValue RHS = N->getOperand(2);
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N->getOperand(3))->get();
     if (!ISD::isIntEqualitySetCC(CCVal))
       break;
if (isOneConstant(RHS) && DAG.MaskedValueIsZero(LHS, Mask)) {
       SDLoc DL(N);
       CCVal = ISD::getSetCCInverse(CCVal, LHS.getValueType());
       SDValue TargetCC = DAG.getCondCode(CCVal);
       RHS = DAG.getConstant(0, DL, LHS.getValueType());
       return DAG.getNode(RISCVISD::BR_CC, DL, N->getValueType(0),
                          N->getOperand(0), LHS, RHS, TargetCC,
                          N->getOperand(4));
     }
+
+    // Optimize
+    // (br_cc (and X, 0x80000000), 0, seteq, dest) ->
+    // (br_cc (sext_inreg X, i32), 0, setge, dest)
+    // And
+    // (br_cc (and X, 0x80000000), 0, setne, dest) ->
+    // (br_cc (sext_inreg X, i32), 0, setlt, dest)
+    if (Subtarget.is64Bit() && LHS.getValueType() == MVT::i64 &&
+        isNullConstant(RHS) && LHS.getOpcode() == ISD::AND && LHS.hasOneUse() &&
+        isa<ConstantSDNode>(LHS.getOperand(1)) &&
+        LHS.getConstantOperandVal(1) == UINT64_C(0x80000000)) {
+      SDLoc DL(N);
+      CCVal = CCVal == ISD::SETEQ ? ISD::SETGE : ISD::SETLT;
+      SDValue TargetCC = DAG.getCondCode(CCVal);
+      LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i64,
+                        LHS.getOperand(0), DAG.getValueType(MVT::i32));
+      return DAG.getNode(RISCVISD::BR_CC, DL, N->getValueType(0),
+                         N->getOperand(0), LHS, RHS, TargetCC,
+                         N->getOperand(4));
+    }
     break;
   }
   case ISD::BITREVERSE:
     return performBITREVERSECombine(N, DAG, Subtarget);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
     return performFP_TO_INTCombine(N, DCI, Subtarget);
   case ISD::FP_TO_SINT_SAT:

llvm/test/CodeGen/RISCV/i64-icmp.ll

 ; RV64I-NEXT:    addi a0, a0, 2
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    ret
   %1 = and i64 %a, 4294967295
   %2 = icmp ne i64 %1, 4294967294
   %3 = zext i1 %2 to i64
   ret i64 %3
 }
+
+define i64 @icmp_bit31_eq_zero_select(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: icmp_bit31_eq_zero_select:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a3, a0
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    bgez a3, .LBB66_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:  .LBB66_2:
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 2147483648
+  %2 = icmp eq i64 %1, 0
+  %3 = select i1 %2, i64 %b, i64 %c
+  ret i64 %3
+}
+
+define i64 @icmp_bit31_ne_zero_select(i64 %a, i64 %b, i64 %c) nounwind {
+; RV64I-LABEL: icmp_bit31_ne_zero_select:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srliw a3, a0, 31
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    bnez a3, .LBB67_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:  .LBB67_2:
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 2147483648
+  %2 = icmp ne i64 %1, 0
+  %3 = select i1 %2, i64 %b, i64 %c
+  ret i64 %3
+}
+
+declare void @bar()
+
+define void @icmp_bit31_eq_zero_branch(i64 %0) {
+; RV64I-LABEL: icmp_bit31_eq_zero_branch:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    bltz a0, .LBB68_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    tail bar@plt
+; RV64I-NEXT:  .LBB68_2:
+; RV64I-NEXT:    ret
+  %2 = and i64 %0, 2147483648
+  %3 = icmp eq i64 %2, 0
+  br i1 %3, label %4, label %5
+
+4:
+  tail call void @bar()
+  br label %5
+
+5:
+  ret void
+}
+
+define void @icmp_bit31_ne_zero_branch(i64 %0) {
+; RV64I-LABEL: icmp_bit31_ne_zero_branch:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    bgez a0, .LBB69_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    tail bar@plt
+; RV64I-NEXT:  .LBB69_2:
+; RV64I-NEXT:    ret
+  %2 = and i64 %0, 2147483648
+  %3 = icmp ne i64 %2, 0
+  br i1 %3, label %4, label %5
+
+4:
+  tail call void @bar()
+  br label %5
+
+5:
+  ret void
+}