Computing scalable offset needs up to two scrach registers. We add
scavenge spill slots according to the result of RISCV::isRVVSpill
and RVVStackSize. Since ADDI is not included in RISCV::isRVVSpill,
PEI doesn't add scavenge spill slots for scrach registers when using
ADDI to get scalable stack offsets.
The ADDI instruction has a destination register which can be used as
a scrach register. So one scavenge spil slot is sufficient for
computing scalable stack offsets.