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[RISCV] Add ADDI instr to compute FrameIndex address for RVV
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Authored by StephenFan on Jun 20 2022, 5:30 AM.

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Summary

RVV doesn't have an immediate field for memory addressing. Currently,
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.

This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as ADDI GPR, targetframeindex, 0.

There are 2 advantages to such change:

  1. Stack objects address computing can be optimized by machine function passes.
  2. Since the ADDI instruction's destination register can be used as a temp register, we can save an emergency spill slot.

Diff Detail

Event Timeline

StephenFan created this revision.Jun 20 2022, 5:30 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2022, 5:30 AM
StephenFan requested review of this revision.Jun 20 2022, 5:30 AM
StephenFan retitled this revision from [RISCV] Add ADDI instr for computing FrameIndex address to [RISCV] Add ADDI instr to compute FrameIndex address for RVV.Jun 20 2022, 5:34 AM
StephenFan edited the summary of this revision. (Show Details)Jun 20 2022, 5:36 AM

Remove blank line

kito-cheng added inline comments.Jun 20 2022, 5:42 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1886

This blank line seems added by accident?

This revision is now accepted and ready to land.Jun 20 2022, 8:21 AM
craig.topper added inline comments.Jun 26 2022, 11:15 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1885–1886

I did some refactoring in SelectAddrRegImm to remove the dependency on SelectBaseAddr. You can remove it in this patch.

This revision was landed with ongoing or failed builds.Jul 4 2022, 7:14 AM
This revision was automatically updated to reflect the committed changes.