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[RISCV] Add RISCVISD opcode for PseudoLLA.
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Authored by craig.topper on Jun 13 2022, 9:41 PM.

Details

Summary

Rather than emitting a MachineSDNode from lowering. Let isel match it.

This is consistent with the RISCVISD::HI and ADD_LO nodes that were
also added. Having them both the same will make D127679 consistent.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 13 2022, 9:41 PM
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craig.topper requested review of this revision.Jun 13 2022, 9:41 PM
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reames accepted this revision.Jun 15 2022, 1:36 PM

LGTM - mostly I'm deferring to you on the direction. I have no objection here, and the code looks reasonable. I just don't have sufficient context to have any confidence this is or isn't the right approach.

This revision is now accepted and ready to land.Jun 15 2022, 1:36 PM
This revision was landed with ongoing or failed builds.Jun 16 2022, 3:15 PM
This revision was automatically updated to reflect the committed changes.
asb added a comment.Jun 20 2022, 3:17 AM

(Catching up from being away on holiday). This committed patch and the related changes all seem like a good direction to me. Thanks Craig.