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Differential D125364

[RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.
ClosedPublic

Authored by jacquesguan on May 11 2022, 2:28 AM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.
Summary

This patch tries to solve the incoordination between the direct and intermediate cast caused by D123975.
This patch replaces ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op in the lowering of FP scalable vector direct cast to unify with the intermediate cast.
And it also changes the FP widenning pattern with the VL op.

Diff Detail

Event Timeline

jacquesguan created this revision.May 11 2022, 2:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 11 2022, 2:28 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
jacquesguan requested review of this revision.May 11 2022, 2:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 11 2022, 2:28 AM
Herald added subscribers: llvm-commits, alextsao1999, • pcwang-thead and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B163857: Diff 428594.May 11 2022, 3:02 AM
jacquesguan added a comment.May 18 2022, 1:13 AM

ping.

frasercrmck added inline comments.May 20 2022, 6:23 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
822 ↗(On Diff #428594)

Using V0 in VL patterns is uncommon. We do it twice but I'm not entirely sure why or if that's an oversight. Shouldn't we be using VLOpFrag and GPR:$vl?

jacquesguan updated this revision to Diff 431615.May 24 2022, 1:48 AM

Use VLOpFrag instead of X0.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
822 ↗(On Diff #428594)

Done, thanks.

Harbormaster completed remote builds in B166008: Diff 431615.May 24 2022, 2:33 AM
craig.topper added inline comments.May 24 2022, 12:36 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1524 ↗(On Diff #431615)

Don't move things to this file that use none _vl ISD opcodes. This file should be pure VL patterns.

craig.topper added inline comments.May 24 2022, 12:40 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827 ↗(On Diff #431615)

This is taking the VL from the fpextend_vl node, but the root node of the pattern has no VL operand. Shouldn't we still be using vti.AVL?

jacquesguan updated this revision to Diff 431866.May 24 2022, 8:03 PM

move patterns back to RISCVInstrInfoVSDPatterns.td

jacquesguan added inline comments.May 24 2022, 8:07 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827 ↗(On Diff #431615)

That would cause error dead named input: $vl.

1524 ↗(On Diff #431615)

Done, I move those patterns back to RISCVInstrInfoVSDPatterns.td.

Harbormaster completed remote builds in B166186: Diff 431866.May 24 2022, 8:46 PM
craig.topper added inline comments.May 24 2022, 9:46 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827 ↗(On Diff #431615)

Yes it would, but's because we don't want that vl. I think you need to use (XLenVT srcvalue) instead of VLOpFrag.

frasercrmck added inline comments.May 24 2022, 9:49 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827 ↗(On Diff #431615)

Sorry about that, I think I mislead things. I got confused somewhat by these patterns previously being in the VL patterns file.

jacquesguan updated this revision to Diff 431889.May 24 2022, 11:41 PM

address comment.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827 ↗(On Diff #431615)

Thanks, done.

Harbormaster completed remote builds in B166203: Diff 431889.May 25 2022, 12:25 AM
craig.topper accepted this revision.May 25 2022, 9:18 AM

LGTM

This revision is now accepted and ready to land.May 25 2022, 9:18 AM
This revision was landed with ongoing or failed builds.May 25 2022, 7:18 PM
Closed by commit rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines
111 lines

Diff 432165

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,263 Lines • ▼ Show 20 LinesRISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
bool IsDirectExtend = IsExtend && (VT.getVectorElementType() != MVT::f64 || bool IsDirectExtend = IsExtend && (VT.getVectorElementType() != MVT::f64 ||
SrcVT.getVectorElementType() != MVT::f16); SrcVT.getVectorElementType() != MVT::f16);
bool IsDirectTrunc = !IsExtend && (VT.getVectorElementType() != MVT::f16 || bool IsDirectTrunc = !IsExtend && (VT.getVectorElementType() != MVT::f16 ||
SrcVT.getVectorElementType() != MVT::f64); SrcVT.getVectorElementType() != MVT::f64);
bool IsDirectConv = IsDirectExtend || IsDirectTrunc; bool IsDirectConv = IsDirectExtend || IsDirectTrunc;
// For FP_ROUND/FP_EXTEND of scalable vectors, leave it to the pattern.
if (!VT.isFixedLengthVector() && !IsVP && IsDirectConv)
return Op;
// Prepare any fixed-length vector operands. // Prepare any fixed-length vector operands.
MVT ContainerVT = VT; MVT ContainerVT = VT;
SDValue Mask, VL; SDValue Mask, VL;
if (IsVP) { if (IsVP) {
Mask = Op.getOperand(1); Mask = Op.getOperand(1);
VL = Op.getOperand(2); VL = Op.getOperand(2);
} }
if (VT.isFixedLengthVector()) { if (VT.isFixedLengthVector()) {
▲ Show 20 Lines • Show All 7,720 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 404 Lines • ▼ Show 20 Lines def : Pat<
)>; )>;
} }
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))), def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))), (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))), def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))), (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))), def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))), (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))), (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
} }
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>; defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>; defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
} }
multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> { multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1))), def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)), (wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))), def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)), (wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> { multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))), def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)), (fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))), def : Pat<(fma (riscv_fpextend_vl_oneuse
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag),
(fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag))),
(fneg wti.RegClass:$rd)), (fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))), def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)), (fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> { multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1))), def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag)),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)), (fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))), def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag)),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)), (fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> { multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))), def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
wti.RegClass:$rd), wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))), def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag)),
(fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag))),
wti.RegClass:$rd), wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))), def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
wti.RegClass:$rd), wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>; vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatMultiplyAddSDNode_VV_VX<SDNode op, string instruction_name> { multiclass VPatMultiplyAddSDNode_VV_VX<SDNode op, string instruction_name> {
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defm : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">; defm : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">;
defm : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">; defm : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">; defm : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
defm : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">; defm : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">; defm : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">;
defm : VPatWConvertI2FPSDNode_V<uint_to_fp, "PseudoVFWCVT_F_XU_V">; defm : VPatWConvertI2FPSDNode_V<uint_to_fp, "PseudoVFWCVT_F_XU_V">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
def : Pat<(fwti.Vector (fpextend (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
defm : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">; defm : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
defm : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">; defm : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
defm : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">; defm : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">;
defm : VPatNConvertI2FPSDNode_V<uint_to_fp, "PseudoVFNCVT_F_XU_W">; defm : VPatNConvertI2FPSDNode_V<uint_to_fp, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti; defvar fvti = fvtiToFWti.Vti;
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