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Differential D125364

[RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.
ClosedPublic

Authored by jacquesguan on May 11 2022, 2:28 AM.

Details

Reviewers
craig.topper
asb
luismarques
frasercrmck
benshi001
Commits
rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.
Summary

This patch tries to solve the incoordination between the direct and intermediate cast caused by D123975.
This patch replaces ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op in the lowering of FP scalable vector direct cast to unify with the intermediate cast.
And it also changes the FP widenning pattern with the VL op.

Diff Detail

Event Timeline

jacquesguan created this revision.May 11 2022, 2:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 11 2022, 2:28 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
jacquesguan requested review of this revision.May 11 2022, 2:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 11 2022, 2:28 AM
Herald added subscribers: llvm-commits, alextsao1999, • pcwang-thead and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B163857: Diff 428594.May 11 2022, 3:02 AM
jacquesguan added a comment.May 18 2022, 1:13 AM

ping.

frasercrmck added inline comments.May 20 2022, 6:23 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
822

Using V0 in VL patterns is uncommon. We do it twice but I'm not entirely sure why or if that's an oversight. Shouldn't we be using VLOpFrag and GPR:$vl?

jacquesguan updated this revision to Diff 431615.May 24 2022, 1:48 AM

Use VLOpFrag instead of X0.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
822

Done, thanks.

Harbormaster completed remote builds in B166008: Diff 431615.May 24 2022, 2:33 AM
craig.topper added inline comments.May 24 2022, 12:36 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
1524

Don't move things to this file that use none _vl ISD opcodes. This file should be pure VL patterns.

craig.topper added inline comments.May 24 2022, 12:40 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827

This is taking the VL from the fpextend_vl node, but the root node of the pattern has no VL operand. Shouldn't we still be using vti.AVL?

jacquesguan updated this revision to Diff 431866.May 24 2022, 8:03 PM

move patterns back to RISCVInstrInfoVSDPatterns.td

jacquesguan added inline comments.May 24 2022, 8:07 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827

That would cause error dead named input: $vl.

1524

Done, I move those patterns back to RISCVInstrInfoVSDPatterns.td.

Harbormaster completed remote builds in B166186: Diff 431866.May 24 2022, 8:46 PM
craig.topper added inline comments.May 24 2022, 9:46 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827

Yes it would, but's because we don't want that vl. I think you need to use (XLenVT srcvalue) instead of VLOpFrag.

frasercrmck added inline comments.May 24 2022, 9:49 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827

Sorry about that, I think I mislead things. I got confused somewhat by these patterns previously being in the VL patterns file.

jacquesguan updated this revision to Diff 431889.May 24 2022, 11:41 PM

address comment.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
827

Thanks, done.

Harbormaster completed remote builds in B166203: Diff 431889.May 25 2022, 12:25 AM
craig.topper accepted this revision.May 25 2022, 9:18 AM

LGTM

This revision is now accepted and ready to land.May 25 2022, 9:18 AM
This revision was landed with ongoing or failed builds.May 25 2022, 7:18 PM
Closed by commit rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op. (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rGb271488e8b13: [RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines
148 lines
187 lines

Diff 431615

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,263 Lines • ▼ Show 20 LinesRISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
bool IsDirectExtend = IsExtend && (VT.getVectorElementType() != MVT::f64 || bool IsDirectExtend = IsExtend && (VT.getVectorElementType() != MVT::f64 ||
SrcVT.getVectorElementType() != MVT::f16); SrcVT.getVectorElementType() != MVT::f16);
bool IsDirectTrunc = !IsExtend && (VT.getVectorElementType() != MVT::f16 || bool IsDirectTrunc = !IsExtend && (VT.getVectorElementType() != MVT::f16 ||
SrcVT.getVectorElementType() != MVT::f64); SrcVT.getVectorElementType() != MVT::f64);
bool IsDirectConv = IsDirectExtend || IsDirectTrunc; bool IsDirectConv = IsDirectExtend || IsDirectTrunc;
// For FP_ROUND/FP_EXTEND of scalable vectors, leave it to the pattern.
if (!VT.isFixedLengthVector() && !IsVP && IsDirectConv)
return Op;
// Prepare any fixed-length vector operands. // Prepare any fixed-length vector operands.
MVT ContainerVT = VT; MVT ContainerVT = VT;
SDValue Mask, VL; SDValue Mask, VL;
if (IsVP) { if (IsVP) {
Mask = Op.getOperand(1); Mask = Op.getOperand(1);
VL = Op.getOperand(2); VL = Op.getOperand(2);
} }
if (VT.isFixedLengthVector()) { if (VT.isFixedLengthVector()) {
▲ Show 20 Lines • Show All 7,720 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 400 Lines • ▼ Show 20 Lines def : Pat<
(wti.Vector (extop2 (vti.Vector vti.RegClass:$rs2))))), (wti.Vector (extop2 (vti.Vector vti.RegClass:$rs2))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
wti.RegClass:$rd, GPR:$rs1, vti.RegClass:$rs2, wti.RegClass:$rd, GPR:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC
)>; )>;
} }
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
}
multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
(wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2))),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))),
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs1)))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)))),
(fneg (wti.Vector (fpext_oneuse (vti.Vector vti.RegClass:$rs2)))),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (fpext_oneuse (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1))))),
(fpext_oneuse (vti.Vector vti.RegClass:$rs2)),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatMultiplyAddSDNode_VV_VX<SDNode op, string instruction_name> { multiclass VPatMultiplyAddSDNode_VV_VX<SDNode op, string instruction_name> {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
defvar suffix = vti.LMul.MX; defvar suffix = vti.LMul.MX;
// NOTE: We choose VMADD because it has the most commuting freedom. So it // NOTE: We choose VMADD because it has the most commuting freedom. So it
// works best with how TwoAddressInstructionPass tries commuting. // works best with how TwoAddressInstructionPass tries commuting.
def : Pat<(vti.Vector (op vti.RegClass:$rs2, def : Pat<(vti.Vector (op vti.RegClass:$rs2,
(mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))), (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
(!cast<Instruction>(instruction_name#"_VV_"# suffix) (!cast<Instruction>(instruction_name#"_VV_"# suffix)
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructionsAnyF] in {
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">; defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">; defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">;
defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">; defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">;
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">;
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">; defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">;
defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">; defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">;
defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">; defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">;
// 14.5. Vector Widening Floating-Point Multiply Instructions // 14.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF<fmul, "PseudoVFWMUL">; defm : VPatWidenBinaryFPSDNode_VV_VF<fmul, "PseudoVFWMUL">;
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
fvti.RegClass:$rd, fvti.RegClass:$rs2)), fvti.RegClass:$rd, fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
} }
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">;
defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">;
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)), def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX)
vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>;
// 14.12. Vector Floating-Point Sign-Injection Instructions // 14.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
defm : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">; defm : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">;
defm : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">; defm : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">; defm : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
defm : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">; defm : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
defm : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">; defm : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">;
defm : VPatWConvertI2FPSDNode_V<uint_to_fp, "PseudoVFWCVT_F_XU_V">; defm : VPatWConvertI2FPSDNode_V<uint_to_fp, "PseudoVFWCVT_F_XU_V">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
def : Pat<(fwti.Vector (fpextend (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
defm : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">; defm : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
defm : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">; defm : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
defm : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">; defm : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">;
defm : VPatNConvertI2FPSDNode_V<uint_to_fp, "PseudoVFNCVT_F_XU_W">; defm : VPatNConvertI2FPSDNode_V<uint_to_fp, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in { foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti; defvar fvti = fvtiToFWti.Vti;
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 807 Lines • ▼ Show 20 Linesmulticlass VPatWidenBinaryFPVL_WV_WF<SDNode op, PatFrags extop, string instruction_name> {
} }
} }
multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>;
defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>;
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag)),
frasercrmckUnsubmitted
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Using V0 in VL patterns is uncommon. We do it twice but I'm not entirely sure why or if that's an oversight. Shouldn't we be using VLOpFrag and GPR:$vl?

frasercrmck: Using `V0` in VL patterns is uncommon. We do it twice but I'm not entirely sure why or if…
jacquesguanAuthorUnsubmitted
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Done, thanks.

jacquesguan: Done, thanks.
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
craig.topperUnsubmitted
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This is taking the VL from the fpextend_vl node, but the root node of the pattern has no VL operand. Shouldn't we still be using vti.AVL?

craig.topper: This is taking the VL from the fpextend_vl node, but the root node of the pattern has no VL…
jacquesguanAuthorUnsubmitted
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That would cause error dead named input: $vl.

jacquesguan: That would cause error `dead named input: $vl`.
craig.topperUnsubmitted
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Yes it would, but's because we don't want that vl. I think you need to use (XLenVT srcvalue) instead of VLOpFrag.

craig.topper: Yes it would, but's because we don't want that vl. I think you need to use `(XLenVT srcvalue)`…
frasercrmckUnsubmitted
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Sorry about that, I think I mislead things. I got confused somewhat by these patterns previously being in the VL patterns file.

frasercrmck: Sorry about that, I think I mislead things. I got confused somewhat by these patterns…
jacquesguanAuthorUnsubmitted
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Thanks, done.

jacquesguan: Thanks, done.
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
}
multiclass VPatWidenFPMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag)),
(wti.Vector wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPNegMulAccSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag),
(fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag))),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag)),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag)),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatWidenFPNegMulSacSDNode_VV_VF<string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag)),
(fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag))),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fma (fneg (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), VLOpFrag))),
(riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
wti.RegClass:$rd),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
def : Pat< def : Pat<
(vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (wti.Vector wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
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let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructionsAnyF] in {
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">;
defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">;
defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">;
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions // 14.3. Vector Widening Floating-Point Add/Subtract Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">;
craig.topperUnsubmitted
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Don't move things to this file that use none _vl ISD opcodes. This file should be pure VL patterns.

craig.topper: Don't move things to this file that use none _vl ISD opcodes. This file should be pure VL…
jacquesguanAuthorUnsubmitted
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Done, I move those patterns back to RISCVInstrInfoVSDPatterns.td.

jacquesguan: Done, I move those patterns back to RISCVInstrInfoVSDPatterns.td.
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">; defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">;
defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">; defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">;
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">;
defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">;
defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">;
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} }
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm : VPatWidenFPMulAccVL_VV_VF<"PseudoVFWMACC">; defm : VPatWidenFPMulAccVL_VV_VF<"PseudoVFWMACC">;
defm : VPatWidenFPNegMulAccVL_VV_VF<"PseudoVFWNMACC">; defm : VPatWidenFPNegMulAccVL_VV_VF<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacVL_VV_VF<"PseudoVFWMSAC">; defm : VPatWidenFPMulSacVL_VV_VF<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacVL_VV_VF<"PseudoVFWNMSAC">; defm : VPatWidenFPNegMulSacVL_VV_VF<"PseudoVFWNMSAC">;
defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">;
defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">;
defm : VPatWidenFPNegMulSacSDNode_VV_VF<"PseudoVFWNMSAC">;
// 14.11. Vector Floating-Point MIN/MAX Instructions // 14.11. Vector Floating-Point MIN/MAX Instructions
defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">;
defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">;
// 14.13. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
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