This is an archive of the discontinued LLVM Phabricator instance.

Differential D124186

[RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
ClosedPublic

Authored by khchen on Apr 21 2022, 9:57 AM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
kito-cheng
arcbbb
monkchiang
eopXD
Commits
rGffe03ff75c26: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup.
Summary

vslideup works by leaving elements 0<i<OFFSET undisturbed.
so it need the destination operand as input for correctness
regardless of policy. Add a operand to indicate policy.

We also add policy operand for unmaksed vslidedown to keep the interface consistent with vslideup
because vslidedown have only undisturbed at 0<i<vstart but user have no way to control of vstart.

Diff Detail

Event Timeline

khchen created this revision.Apr 21 2022, 9:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 21 2022, 9:57 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 26 others. · View Herald Transcript
khchen requested review of this revision.Apr 21 2022, 9:57 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptApr 21 2022, 9:57 AM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
khchen added a parent revision: D124179: [RISCV][NFC] Remove unused text in the test..Apr 21 2022, 9:58 AM
Harbormaster completed remote builds in B160683: Diff 424239.Apr 21 2022, 9:58 AM
craig.topper added a comment.Apr 21 2022, 10:15 AM

The intrinsic interface doesn't care about 0<i<vstart for slidedown. We don't give user control of vstart. Nearly every instruction is undisturbed for 0<i<vstart.

But having said that it probably makes sense to keep the vslideup/down interface the same.

khchen edited the summary of this revision. (Show Details)EditedApr 21 2022, 10:00 PM
In D124186#3465136, @craig.topper wrote:

The intrinsic interface doesn't care about 0<i<vstart for slidedown. We don't give user control of vstart. Nearly every instruction is undisturbed for 0<i<vstart.

But having said that it probably makes sense to keep the vslideup/down interface the same.

Yes I know, but I didn't clarify that in comment, thanks for your advice.

khchen updated this revision to Diff 424517.Apr 22 2022, 10:08 AM
khchen edited the summary of this revision. (Show Details)

update clang tests.

Harbormaster completed remote builds in B160886: Diff 424517.Apr 22 2022, 10:09 AM
rogfer01 accepted this revision.Apr 25 2022, 3:23 AM

LGTM. Thanks @khchen !

This revision is now accepted and ready to land.Apr 25 2022, 3:23 AM
This revision was landed with ongoing or failed builds.Apr 25 2022, 9:20 AM
Closed by commit rGffe03ff75c26: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup. (authored by khchen). · Explain Why
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rGffe03ff75c26: [RISCV] Fix incorrect policy implement for unmasked vslidedown and vslideup..

Revision Contents

PathSize
clang/
include/
clang/
Basic/
3 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
106 lines
106 lines
rvv-intrinsics/
118 lines
118 lines
llvm/
include/
llvm/
IR/
20 lines
lib/
Target/
RISCV/
29 lines
8 lines
test/
CodeGen/
RISCV/
rvv/
4 lines
4 lines
8 lines
80 lines
24 lines
6 lines
8 lines
48 lines
14 lines
32 lines
12 lines
22 lines
58 lines
25 lines
17 lines
2 lines
51 lines
18 lines
14 lines
6 lines
12 lines
4 lines
34 lines
2 lines
36 lines
60 lines
60 lines
28 lines
104 lines
88 lines
13 lines
4 lines
2 lines
17 lines
222 lines
420 lines
420 lines
420 lines
420 lines

Diff 424934

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 437 Lines • ▼ Show 20 Linesclass RVVMaskNullaryBuiltin : RVVOutBuiltin<"m", "m", "c"> {
let HasUnMaskedOverloaded = false; let HasUnMaskedOverloaded = false;
} }
class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> { class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
let Name = NAME # "_m"; let Name = NAME # "_m";
let HasMaskedOffOperand = false; let HasMaskedOffOperand = false;
} }
let HasMaskedOffOperand = false in { let UnMaskedPolicy = HasPolicyOperand,
HasMaskedOffOperand = false in {
multiclass RVVSlideBuiltinSet { multiclass RVVSlideBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd", defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvvz"]]>; [["vx","v", "vvvz"]]>;
defm "" : RVVOutBuiltinSet<NAME, "csil", defm "" : RVVOutBuiltinSet<NAME, "csil",
[["vx","Uv", "UvUvUvz"]]>; [["vx","Uv", "UvUvUvz"]]>;
} }
} }
▲ Show 20 Lines • Show All 1,756 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset, vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset, vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset, vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset, vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src, vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src, vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src, vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src, vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src, vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src, vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src, vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src, vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src, vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src, vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src, vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src, vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src, vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src, vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src, vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src, vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src, vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src, vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src, vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src, vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src, vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src, vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src, vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src, vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src, vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src, vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src, vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src, vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src, vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src, vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src, vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src, vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src, vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src, vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src, vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src, vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src, vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src, vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src, vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src, vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src, vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown(dst, src, offset, vl); return vslidedown(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
▲ Show 20 Lines • Show All 573 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset, vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset, vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset, vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset, vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset, vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset, vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset, vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src, vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src, vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset, vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset, vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset, vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset, vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src, vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset, vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset, vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset, vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset, vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset, vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset, vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset, vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset, vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src, vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src, vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src, vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset, vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset, vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset, vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset, vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src, vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src, vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src, vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src, vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src, vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src, vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src, vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src, vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src, vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src, vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src, vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src, vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src, vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src, vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src, vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src, vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src, vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src, vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src, vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src, vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src, vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src, vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src, vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup(dst, src, offset, vl); return vslideup(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
▲ Show 20 Lines • Show All 558 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, vint8mf8_t test_vslidedown_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8mf8(dst, src, offset, vl); return vslidedown_vx_i8mf8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, vint8mf4_t test_vslidedown_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8mf4(dst, src, offset, vl); return vslidedown_vx_i8mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, vint8mf2_t test_vslidedown_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i8mf2(dst, src, offset, vl); return vslidedown_vx_i8mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset, vint8m1_t test_vslidedown_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8m1(dst, src, offset, vl); return vslidedown_vx_i8m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset, vint8m2_t test_vslidedown_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8m2(dst, src, offset, vl); return vslidedown_vx_i8m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset, vint8m4_t test_vslidedown_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8m4(dst, src, offset, vl); return vslidedown_vx_i8m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset, vint8m8_t test_vslidedown_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_i8m8(dst, src, offset, vl); return vslidedown_vx_i8m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src, vint16mf4_t test_vslidedown_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16mf4(dst, src, offset, vl); return vslidedown_vx_i16mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src, vint16mf2_t test_vslidedown_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16mf2(dst, src, offset, vl); return vslidedown_vx_i16mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src, vint16m1_t test_vslidedown_vx_i16m1(vint16m1_t dst, vint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16m1(dst, src, offset, vl); return vslidedown_vx_i16m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src, vint16m2_t test_vslidedown_vx_i16m2(vint16m2_t dst, vint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16m2(dst, src, offset, vl); return vslidedown_vx_i16m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src, vint16m4_t test_vslidedown_vx_i16m4(vint16m4_t dst, vint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16m4(dst, src, offset, vl); return vslidedown_vx_i16m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src, vint16m8_t test_vslidedown_vx_i16m8(vint16m8_t dst, vint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i16m8(dst, src, offset, vl); return vslidedown_vx_i16m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src, vint32mf2_t test_vslidedown_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i32mf2(dst, src, offset, vl); return vslidedown_vx_i32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src, vint32m1_t test_vslidedown_vx_i32m1(vint32m1_t dst, vint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i32m1(dst, src, offset, vl); return vslidedown_vx_i32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src, vint32m2_t test_vslidedown_vx_i32m2(vint32m2_t dst, vint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i32m2(dst, src, offset, vl); return vslidedown_vx_i32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src, vint32m4_t test_vslidedown_vx_i32m4(vint32m4_t dst, vint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i32m4(dst, src, offset, vl); return vslidedown_vx_i32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src, vint32m8_t test_vslidedown_vx_i32m8(vint32m8_t dst, vint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i32m8(dst, src, offset, vl); return vslidedown_vx_i32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src, vint64m1_t test_vslidedown_vx_i64m1(vint64m1_t dst, vint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i64m1(dst, src, offset, vl); return vslidedown_vx_i64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src, vint64m2_t test_vslidedown_vx_i64m2(vint64m2_t dst, vint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i64m2(dst, src, offset, vl); return vslidedown_vx_i64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src, vint64m4_t test_vslidedown_vx_i64m4(vint64m4_t dst, vint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i64m4(dst, src, offset, vl); return vslidedown_vx_i64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src, vint64m8_t test_vslidedown_vx_i64m8(vint64m8_t dst, vint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_i64m8(dst, src, offset, vl); return vslidedown_vx_i64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src, vuint8mf8_t test_vslidedown_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8mf8(dst, src, offset, vl); return vslidedown_vx_u8mf8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src, vuint8mf4_t test_vslidedown_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8mf4(dst, src, offset, vl); return vslidedown_vx_u8mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src, vuint8mf2_t test_vslidedown_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8mf2(dst, src, offset, vl); return vslidedown_vx_u8mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, vuint8m1_t test_vslidedown_vx_u8m1(vuint8m1_t dst, vuint8m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8m1(dst, src, offset, vl); return vslidedown_vx_u8m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, vuint8m2_t test_vslidedown_vx_u8m2(vuint8m2_t dst, vuint8m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8m2(dst, src, offset, vl); return vslidedown_vx_u8m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, vuint8m4_t test_vslidedown_vx_u8m4(vuint8m4_t dst, vuint8m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8m4(dst, src, offset, vl); return vslidedown_vx_u8m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslidedown.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, vuint8m8_t test_vslidedown_vx_u8m8(vuint8m8_t dst, vuint8m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u8m8(dst, src, offset, vl); return vslidedown_vx_u8m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src, vuint16mf4_t test_vslidedown_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16mf4(dst, src, offset, vl); return vslidedown_vx_u16mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src, vuint16mf2_t test_vslidedown_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16mf2(dst, src, offset, vl); return vslidedown_vx_u16mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src, vuint16m1_t test_vslidedown_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16m1(dst, src, offset, vl); return vslidedown_vx_u16m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src, vuint16m2_t test_vslidedown_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16m2(dst, src, offset, vl); return vslidedown_vx_u16m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src, vuint16m4_t test_vslidedown_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16m4(dst, src, offset, vl); return vslidedown_vx_u16m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslidedown.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src, vuint16m8_t test_vslidedown_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u16m8(dst, src, offset, vl); return vslidedown_vx_u16m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src, vuint32mf2_t test_vslidedown_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u32mf2(dst, src, offset, vl); return vslidedown_vx_u32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src, vuint32m1_t test_vslidedown_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u32m1(dst, src, offset, vl); return vslidedown_vx_u32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src, vuint32m2_t test_vslidedown_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u32m2(dst, src, offset, vl); return vslidedown_vx_u32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src, vuint32m4_t test_vslidedown_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u32m4(dst, src, offset, vl); return vslidedown_vx_u32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslidedown.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src, vuint32m8_t test_vslidedown_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u32m8(dst, src, offset, vl); return vslidedown_vx_u32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src, vuint64m1_t test_vslidedown_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u64m1(dst, src, offset, vl); return vslidedown_vx_u64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src, vuint64m2_t test_vslidedown_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u64m2(dst, src, offset, vl); return vslidedown_vx_u64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src, vuint64m4_t test_vslidedown_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u64m4(dst, src, offset, vl); return vslidedown_vx_u64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslidedown.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src, vuint64m8_t test_vslidedown_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_u64m8(dst, src, offset, vl); return vslidedown_vx_u64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src, vfloat32mf2_t test_vslidedown_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f32mf2(dst, src, offset, vl); return vslidedown_vx_f32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src, vfloat32m1_t test_vslidedown_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f32m1(dst, src, offset, vl); return vslidedown_vx_f32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src, vfloat32m2_t test_vslidedown_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f32m2(dst, src, offset, vl); return vslidedown_vx_f32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src, vfloat32m4_t test_vslidedown_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f32m4(dst, src, offset, vl); return vslidedown_vx_f32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslidedown.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src, vfloat32m8_t test_vslidedown_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f32m8(dst, src, offset, vl); return vslidedown_vx_f32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src, vfloat64m1_t test_vslidedown_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f64m1(dst, src, offset, vl); return vslidedown_vx_f64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src, vfloat64m2_t test_vslidedown_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f64m2(dst, src, offset, vl); return vslidedown_vx_f64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src, vfloat64m4_t test_vslidedown_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f64m4(dst, src, offset, vl); return vslidedown_vx_f64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslidedown.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslidedown_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslidedown_vx_f64m8(dst, src, offset, vl); return vslidedown_vx_f64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_i8mf8_m(
▲ Show 20 Lines • Show All 568 Lines • ▼ Show 20 Lines
vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslidedown_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslidedown_vx_f64m8_m(mask, dst, src, offset, vl); return vslidedown_vx_f64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslidedown_vx_f16mf4 (vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslidedown_vx_f16mf4 (vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16mf4(dest, src, offset, vl); return vslidedown_vx_f16mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslidedown_vx_f16mf2 (vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslidedown_vx_f16mf2 (vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16mf2(dest, src, offset, vl); return vslidedown_vx_f16mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m1( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslidedown_vx_f16m1 (vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslidedown_vx_f16m1 (vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m1(dest, src, offset, vl); return vslidedown_vx_f16m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m2( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslidedown_vx_f16m2 (vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslidedown_vx_f16m2 (vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m2(dest, src, offset, vl); return vslidedown_vx_f16m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m4( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslidedown_vx_f16m4 (vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslidedown_vx_f16m4 (vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m4(dest, src, offset, vl); return vslidedown_vx_f16m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16m8( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslidedown.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslidedown_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslidedown_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslidedown_vx_f16m8(dest, src, offset, vl); return vslidedown_vx_f16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslidedown_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \ // RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset, vint8mf8_t test_vslideup_vx_i8mf8(vint8mf8_t dst, vint8mf8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8mf8(dst, src, offset, vl); return vslideup_vx_i8mf8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset, vint8mf4_t test_vslideup_vx_i8mf4(vint8mf4_t dst, vint8mf4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8mf4(dst, src, offset, vl); return vslideup_vx_i8mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset, vint8mf2_t test_vslideup_vx_i8mf2(vint8mf2_t dst, vint8mf2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8mf2(dst, src, offset, vl); return vslideup_vx_i8mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset, vint8m1_t test_vslideup_vx_i8m1(vint8m1_t dst, vint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8m1(dst, src, offset, vl); return vslideup_vx_i8m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset, vint8m2_t test_vslideup_vx_i8m2(vint8m2_t dst, vint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8m2(dst, src, offset, vl); return vslideup_vx_i8m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset, vint8m4_t test_vslideup_vx_i8m4(vint8m4_t dst, vint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8m4(dst, src, offset, vl); return vslideup_vx_i8m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset, vint8m8_t test_vslideup_vx_i8m8(vint8m8_t dst, vint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i8m8(dst, src, offset, vl); return vslideup_vx_i8m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src, vint16mf4_t test_vslideup_vx_i16mf4(vint16mf4_t dst, vint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i16mf4(dst, src, offset, vl); return vslideup_vx_i16mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src, vint16mf2_t test_vslideup_vx_i16mf2(vint16mf2_t dst, vint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i16mf2(dst, src, offset, vl); return vslideup_vx_i16mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset, vint16m1_t test_vslideup_vx_i16m1(vint16m1_t dst, vint16m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16m1(dst, src, offset, vl); return vslideup_vx_i16m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset, vint16m2_t test_vslideup_vx_i16m2(vint16m2_t dst, vint16m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16m2(dst, src, offset, vl); return vslideup_vx_i16m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset, vint16m4_t test_vslideup_vx_i16m4(vint16m4_t dst, vint16m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16m4(dst, src, offset, vl); return vslideup_vx_i16m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset, vint16m8_t test_vslideup_vx_i16m8(vint16m8_t dst, vint16m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i16m8(dst, src, offset, vl); return vslideup_vx_i16m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src, vint32mf2_t test_vslideup_vx_i32mf2(vint32mf2_t dst, vint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_i32mf2(dst, src, offset, vl); return vslideup_vx_i32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset, vint32m1_t test_vslideup_vx_i32m1(vint32m1_t dst, vint32m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i32m1(dst, src, offset, vl); return vslideup_vx_i32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset, vint32m2_t test_vslideup_vx_i32m2(vint32m2_t dst, vint32m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i32m2(dst, src, offset, vl); return vslideup_vx_i32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset, vint32m4_t test_vslideup_vx_i32m4(vint32m4_t dst, vint32m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i32m4(dst, src, offset, vl); return vslideup_vx_i32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset, vint32m8_t test_vslideup_vx_i32m8(vint32m8_t dst, vint32m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i32m8(dst, src, offset, vl); return vslideup_vx_i32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset, vint64m1_t test_vslideup_vx_i64m1(vint64m1_t dst, vint64m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i64m1(dst, src, offset, vl); return vslideup_vx_i64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset, vint64m2_t test_vslideup_vx_i64m2(vint64m2_t dst, vint64m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i64m2(dst, src, offset, vl); return vslideup_vx_i64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset, vint64m4_t test_vslideup_vx_i64m4(vint64m4_t dst, vint64m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i64m4(dst, src, offset, vl); return vslideup_vx_i64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_i64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset, vint64m8_t test_vslideup_vx_i64m8(vint64m8_t dst, vint64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_i64m8(dst, src, offset, vl); return vslideup_vx_i64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8.i64(<vscale x 1 x i8> [[DST:%.*]], <vscale x 1 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
// //
vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src, vuint8mf8_t test_vslideup_vx_u8mf8(vuint8mf8_t dst, vuint8mf8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u8mf8(dst, src, offset, vl); return vslideup_vx_u8mf8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8.i64(<vscale x 2 x i8> [[DST:%.*]], <vscale x 2 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]]
// //
vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src, vuint8mf4_t test_vslideup_vx_u8mf4(vuint8mf4_t dst, vuint8mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u8mf4(dst, src, offset, vl); return vslideup_vx_u8mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8.i64(<vscale x 4 x i8> [[DST:%.*]], <vscale x 4 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]]
// //
vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src, vuint8mf2_t test_vslideup_vx_u8mf2(vuint8mf2_t dst, vuint8mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u8mf2(dst, src, offset, vl); return vslideup_vx_u8mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8.i64(<vscale x 8 x i8> [[DST:%.*]], <vscale x 8 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]]
// //
vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset, vuint8m1_t test_vslideup_vx_u8m1(vuint8m1_t dst, vuint8m1_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8m1(dst, src, offset, vl); return vslideup_vx_u8m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8.i64(<vscale x 16 x i8> [[DST:%.*]], <vscale x 16 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]]
// //
vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset, vuint8m2_t test_vslideup_vx_u8m2(vuint8m2_t dst, vuint8m2_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8m2(dst, src, offset, vl); return vslideup_vx_u8m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8.i64(<vscale x 32 x i8> [[DST:%.*]], <vscale x 32 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]]
// //
vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset, vuint8m4_t test_vslideup_vx_u8m4(vuint8m4_t dst, vuint8m4_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8m4(dst, src, offset, vl); return vslideup_vx_u8m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u8m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u8m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vslideup.nxv64i8.i64(<vscale x 64 x i8> [[DST:%.*]], <vscale x 64 x i8> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]]
// //
vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset, vuint8m8_t test_vslideup_vx_u8m8(vuint8m8_t dst, vuint8m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_u8m8(dst, src, offset, vl); return vslideup_vx_u8m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16.i64(<vscale x 1 x i16> [[DST:%.*]], <vscale x 1 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
// //
vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src, vuint16mf4_t test_vslideup_vx_u16mf4(vuint16mf4_t dst, vuint16mf4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16mf4(dst, src, offset, vl); return vslideup_vx_u16mf4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16.i64(<vscale x 2 x i16> [[DST:%.*]], <vscale x 2 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
// //
vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src, vuint16mf2_t test_vslideup_vx_u16mf2(vuint16mf2_t dst, vuint16mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16mf2(dst, src, offset, vl); return vslideup_vx_u16mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
// //
vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src, vuint16m1_t test_vslideup_vx_u16m1(vuint16m1_t dst, vuint16m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16m1(dst, src, offset, vl); return vslideup_vx_u16m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16.i64(<vscale x 8 x i16> [[DST:%.*]], <vscale x 8 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
// //
vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src, vuint16m2_t test_vslideup_vx_u16m2(vuint16m2_t dst, vuint16m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16m2(dst, src, offset, vl); return vslideup_vx_u16m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16.i64(<vscale x 16 x i16> [[DST:%.*]], <vscale x 16 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
// //
vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src, vuint16m4_t test_vslideup_vx_u16m4(vuint16m4_t dst, vuint16m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16m4(dst, src, offset, vl); return vslideup_vx_u16m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vslideup.nxv32i16.i64(<vscale x 32 x i16> [[DST:%.*]], <vscale x 32 x i16> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
// //
vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src, vuint16m8_t test_vslideup_vx_u16m8(vuint16m8_t dst, vuint16m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u16m8(dst, src, offset, vl); return vslideup_vx_u16m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32.i64(<vscale x 1 x i32> [[DST:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
// //
vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src, vuint32mf2_t test_vslideup_vx_u32mf2(vuint32mf2_t dst, vuint32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u32mf2(dst, src, offset, vl); return vslideup_vx_u32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
// //
vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src, vuint32m1_t test_vslideup_vx_u32m1(vuint32m1_t dst, vuint32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u32m1(dst, src, offset, vl); return vslideup_vx_u32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32.i64(<vscale x 4 x i32> [[DST:%.*]], <vscale x 4 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
// //
vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src, vuint32m2_t test_vslideup_vx_u32m2(vuint32m2_t dst, vuint32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u32m2(dst, src, offset, vl); return vslideup_vx_u32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32.i64(<vscale x 8 x i32> [[DST:%.*]], <vscale x 8 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
// //
vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src, vuint32m4_t test_vslideup_vx_u32m4(vuint32m4_t dst, vuint32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u32m4(dst, src, offset, vl); return vslideup_vx_u32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vslideup.nxv16i32.i64(<vscale x 16 x i32> [[DST:%.*]], <vscale x 16 x i32> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
// //
vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src, vuint32m8_t test_vslideup_vx_u32m8(vuint32m8_t dst, vuint32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u32m8(dst, src, offset, vl); return vslideup_vx_u32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
// //
vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src, vuint64m1_t test_vslideup_vx_u64m1(vuint64m1_t dst, vuint64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u64m1(dst, src, offset, vl); return vslideup_vx_u64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64.i64(<vscale x 2 x i64> [[DST:%.*]], <vscale x 2 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
// //
vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src, vuint64m2_t test_vslideup_vx_u64m2(vuint64m2_t dst, vuint64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u64m2(dst, src, offset, vl); return vslideup_vx_u64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64.i64(<vscale x 4 x i64> [[DST:%.*]], <vscale x 4 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
// //
vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src, vuint64m4_t test_vslideup_vx_u64m4(vuint64m4_t dst, vuint64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u64m4(dst, src, offset, vl); return vslideup_vx_u64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_u64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_u64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vslideup.nxv8i64.i64(<vscale x 8 x i64> [[DST:%.*]], <vscale x 8 x i64> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
// //
vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src, vuint64m8_t test_vslideup_vx_u64m8(vuint64m8_t dst, vuint64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_u64m8(dst, src, offset, vl); return vslideup_vx_u64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32.i64(<vscale x 1 x float> [[DST:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src, vfloat32mf2_t test_vslideup_vx_f32mf2(vfloat32mf2_t dst, vfloat32mf2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f32mf2(dst, src, offset, vl); return vslideup_vx_f32mf2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32.i64(<vscale x 2 x float> [[DST:%.*]], <vscale x 2 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src, vfloat32m1_t test_vslideup_vx_f32m1(vfloat32m1_t dst, vfloat32m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f32m1(dst, src, offset, vl); return vslideup_vx_f32m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32.i64(<vscale x 4 x float> [[DST:%.*]], <vscale x 4 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src, vfloat32m2_t test_vslideup_vx_f32m2(vfloat32m2_t dst, vfloat32m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f32m2(dst, src, offset, vl); return vslideup_vx_f32m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32.i64(<vscale x 8 x float> [[DST:%.*]], <vscale x 8 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src, vfloat32m4_t test_vslideup_vx_f32m4(vfloat32m4_t dst, vfloat32m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f32m4(dst, src, offset, vl); return vslideup_vx_f32m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f32m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f32m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vslideup.nxv16f32.i64(<vscale x 16 x float> [[DST:%.*]], <vscale x 16 x float> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src, vfloat32m8_t test_vslideup_vx_f32m8(vfloat32m8_t dst, vfloat32m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f32m8(dst, src, offset, vl); return vslideup_vx_f32m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src, vfloat64m1_t test_vslideup_vx_f64m1(vfloat64m1_t dst, vfloat64m1_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f64m1(dst, src, offset, vl); return vslideup_vx_f64m1(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64.i64(<vscale x 2 x double> [[DST:%.*]], <vscale x 2 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src, vfloat64m2_t test_vslideup_vx_f64m2(vfloat64m2_t dst, vfloat64m2_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f64m2(dst, src, offset, vl); return vslideup_vx_f64m2(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64.i64(<vscale x 4 x double> [[DST:%.*]], <vscale x 4 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src, vfloat64m4_t test_vslideup_vx_f64m4(vfloat64m4_t dst, vfloat64m4_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f64m4(dst, src, offset, vl); return vslideup_vx_f64m4(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f64m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f64m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vslideup.nxv8f64.i64(<vscale x 8 x double> [[DST:%.*]], <vscale x 8 x double> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src, vfloat64m8_t test_vslideup_vx_f64m8(vfloat64m8_t dst, vfloat64m8_t src,
size_t offset, size_t vl) { size_t offset, size_t vl) {
return vslideup_vx_f64m8(dst, src, offset, vl); return vslideup_vx_f64m8(dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m( // CHECK-RV64-LABEL: @test_vslideup_vx_i8mf8_m(
▲ Show 20 Lines • Show All 553 Lines • ▼ Show 20 Lines
vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst, vfloat64m8_t test_vslideup_vx_f64m8_m(vbool8_t mask, vfloat64m8_t dst,
vfloat64m8_t src, size_t offset, vfloat64m8_t src, size_t offset,
size_t vl) { size_t vl) {
return vslideup_vx_f64m8_m(mask, dst, src, offset, vl); return vslideup_vx_f64m8_m(mask, dst, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16.i64(<vscale x 1 x half> [[DEST:%.*]], <vscale x 1 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vslideup_vx_f16mf4 (vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) { vfloat16mf4_t test_vslideup_vx_f16mf4 (vfloat16mf4_t dest, vfloat16mf4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf4(dest, src, offset, vl); return vslideup_vx_f16mf4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16.i64(<vscale x 2 x half> [[DEST:%.*]], <vscale x 2 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vslideup_vx_f16mf2 (vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) { vfloat16mf2_t test_vslideup_vx_f16mf2 (vfloat16mf2_t dest, vfloat16mf2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16mf2(dest, src, offset, vl); return vslideup_vx_f16mf2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m1( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m1(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16.i64(<vscale x 4 x half> [[DEST:%.*]], <vscale x 4 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vslideup_vx_f16m1 (vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) { vfloat16m1_t test_vslideup_vx_f16m1 (vfloat16m1_t dest, vfloat16m1_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m1(dest, src, offset, vl); return vslideup_vx_f16m1(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m2( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m2(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16.i64(<vscale x 8 x half> [[DEST:%.*]], <vscale x 8 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vslideup_vx_f16m2 (vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) { vfloat16m2_t test_vslideup_vx_f16m2 (vfloat16m2_t dest, vfloat16m2_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m2(dest, src, offset, vl); return vslideup_vx_f16m2(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m4( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m4(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16.i64(<vscale x 16 x half> [[DEST:%.*]], <vscale x 16 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vslideup_vx_f16m4 (vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) { vfloat16m4_t test_vslideup_vx_f16m4 (vfloat16m4_t dest, vfloat16m4_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m4(dest, src, offset, vl); return vslideup_vx_f16m4(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16m8( // CHECK-RV64-LABEL: @test_vslideup_vx_f16m8(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vslideup.nxv32f16.i64(<vscale x 32 x half> [[DEST:%.*]], <vscale x 32 x half> [[SRC:%.*]], i64 [[OFFSET:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vslideup_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) { vfloat16m8_t test_vslideup_vx_f16m8 (vfloat16m8_t dest, vfloat16m8_t src, size_t offset, size_t vl) {
return vslideup_vx_f16m8(dest, src, offset, vl); return vslideup_vx_f16m8(dest, src, offset, vl);
} }
// CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m( // CHECK-RV64-LABEL: @test_vslideup_vx_f16mf4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 666 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
class RISCVSaturatingBinaryABShiftMasked class RISCVSaturatingBinaryABShiftMasked
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
LLVMMatchType<3>], LLVMMatchType<3>],
[ImmArg<ArgIndex<5>>, IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic { [ImmArg<ArgIndex<5>>, IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
let VLOperand = 4; let VLOperand = 4;
} }
// Input: (vector_in, vector_in, vector_in/scalar_in, vl) // Input: (vector_in, vector_in, scalar_in, vl, policy)
class RISCVTernaryAAAXUnMasked class RVVSlideUnMasked
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMMatchType<1>], LLVMMatchType<1>, LLVMMatchType<1>],
[IntrNoMem]>, RISCVVIntrinsic { [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl, policy) // Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVTernaryAAAXMasked class RVVSlideMasked
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty, [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>, LLVMMatchType<1>], LLVMMatchType<1>, LLVMMatchType<1>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic { [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 4; let VLOperand = 4;
} }
// UnMasked Vector Multiply-Add operations, its first operand can not be undef. // UnMasked Vector Multiply-Add operations, its first operand can not be undef.
▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
multiclass RISCVSaturatingBinaryAAShift { multiclass RISCVSaturatingBinaryAAShift {
def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftUnMasked; def "int_riscv_" # NAME : RISCVSaturatingBinaryAAShiftUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAShiftMasked; def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryAAShiftMasked;
} }
multiclass RISCVSaturatingBinaryABShift { multiclass RISCVSaturatingBinaryABShift {
def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMasked; def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABShiftMasked; def "int_riscv_" # NAME # "_mask" : RISCVSaturatingBinaryABShiftMasked;
} }
multiclass RISCVTernaryAAAX { multiclass RVVSlide {
def "int_riscv_" # NAME : RISCVTernaryAAAXUnMasked; def "int_riscv_" # NAME : RVVSlideUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAAXMasked; def "int_riscv_" # NAME # "_mask" : RVVSlideMasked;
} }
multiclass RISCVTernaryAAXA { multiclass RISCVTernaryAAXA {
def "int_riscv_" # NAME : RISCVTernaryAAXAUnMasked; def "int_riscv_" # NAME : RISCVTernaryAAXAUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMasked; def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMasked;
} }
multiclass RISCVCompare { multiclass RISCVCompare {
def "int_riscv_" # NAME : RISCVCompareUnMasked; def "int_riscv_" # NAME : RISCVCompareUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVCompareMasked; def "int_riscv_" # NAME # "_mask" : RISCVCompareMasked;
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
defm vfsgnj : RISCVBinaryAAX; defm vfsgnj : RISCVBinaryAAX;
defm vfsgnjn : RISCVBinaryAAX; defm vfsgnjn : RISCVBinaryAAX;
defm vfsgnjx : RISCVBinaryAAX; defm vfsgnjx : RISCVBinaryAAX;
defm vfclass : RISCVClassify; defm vfclass : RISCVClassify;
defm vfmerge : RISCVBinaryWithV0; defm vfmerge : RISCVBinaryWithV0;
defm vslideup : RISCVTernaryAAAX; defm vslideup : RVVSlide;
defm vslidedown : RISCVTernaryAAAX; defm vslidedown : RVVSlide;
defm vslide1up : RISCVBinaryAAX; defm vslide1up : RISCVBinaryAAX;
defm vslide1down : RISCVBinaryAAX; defm vslide1down : RISCVBinaryAAX;
defm vfslide1up : RISCVBinaryAAX; defm vfslide1up : RISCVBinaryAAX;
defm vfslide1down : RISCVBinaryAAX; defm vfslide1down : RISCVBinaryAAX;
defm vrgather_vv : RISCVRGatherVV; defm vrgather_vv : RISCVRGatherVV;
defm vrgather_vx : RISCVRGatherVX; defm vrgather_vx : RISCVRGatherVX;
▲ Show 20 Lines • Show All 241 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 2,503 Lines • ▼ Show 20 Lines
multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "", multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "",
list<LMULInfo> mxlist = MxList> { list<LMULInfo> mxlist = MxList> {
foreach m = mxlist in { foreach m = mxlist in {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
} }
multiclass VPseudoTernaryV_VX<string Constraint = ""> { multiclass VPseudoVSLDV_VX<string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm _VX : VPseudoTernaryNoMaskNoPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>; defm _VX : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
} }
multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> { multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m, defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
Show All 22 Lines
multiclass VPseudoTernaryW_VF { multiclass VPseudoTernaryW_VF {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach f = FPListW in foreach f = FPListW in
foreach m = f.MxList in foreach m = f.MxList in
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass, defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
m.vrclass, m, constraint>; m.vrclass, m, constraint>;
} }
multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in foreach m = MxList in
defm _VI : VPseudoTernaryNoMaskNoPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>; defm _VI : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
} }
multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> { multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
defm "" : VPseudoTernaryV_VV_AAXA<Constraint>, defm "" : VPseudoTernaryV_VV_AAXA<Constraint>,
Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>; Sched<[WriteVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddV, ReadVMask]>;
defm "" : VPseudoTernaryV_VX_AAXA<Constraint>, defm "" : VPseudoTernaryV_VX_AAXA<Constraint>,
Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>; Sched<[WriteVIMulAddX, ReadVIMulAddV, ReadVIMulAddV, ReadVIMulAddX, ReadVMask]>;
} }
multiclass VPseudoVMAC_VV_VF_AAXA<string Constraint = ""> { multiclass VPseudoVMAC_VV_VF_AAXA<string Constraint = ""> {
defm "" : VPseudoTernaryV_VV_AAXA<Constraint, MxListF>, defm "" : VPseudoTernaryV_VV_AAXA<Constraint, MxListF>,
Sched<[WriteVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVMask]>; Sched<[WriteVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVFMulAddV, ReadVMask]>;
defm "" : VPseudoTernaryV_VF_AAXA<Constraint>, defm "" : VPseudoTernaryV_VF_AAXA<Constraint>,
Sched<[WriteVFMulAddF, ReadVFMulAddV, ReadVFMulAddV, ReadVFMulAddF, ReadVMask]>; Sched<[WriteVFMulAddF, ReadVFMulAddV, ReadVFMulAddV, ReadVFMulAddF, ReadVMask]>;
} }
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
defm "" : VPseudoTernaryV_VX<Constraint>, defm "" : VPseudoVSLDV_VX<Constraint>,
Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideV, ReadVISlideX, ReadVMask]>; Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideV, ReadVISlideX, ReadVMask]>;
defm "" : VPseudoTernaryV_VI<ImmType, Constraint>, defm "" : VPseudoVSLDV_VI<ImmType, Constraint>,
Sched<[WriteVISlideI, ReadVISlideV, ReadVISlideV, ReadVMask]>; Sched<[WriteVISlideI, ReadVISlideV, ReadVISlideV, ReadVMask]>;
} }
multiclass VPseudoVWMAC_VV_VX { multiclass VPseudoVWMAC_VV_VX {
defm "" : VPseudoTernaryW_VV, defm "" : VPseudoTernaryW_VV,
Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>; Sched<[WriteVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddV, ReadVMask]>;
defm "" : VPseudoTernaryW_VX, defm "" : VPseudoTernaryW_VX,
Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>; Sched<[WriteVIWMulAddX, ReadVIWMulAddV, ReadVIWMulAddV, ReadVIWMulAddX, ReadVMask]>;
▲ Show 20 Lines • Show All 1,381 Lines • ▼ Show 20 Lines defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VX<string intrinsic, string instruction, multiclass VPatTernaryV_VX<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryNoMaskNoPolicy<intrinsic, instruction, "VX", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, GPR>; vti.RegClass, GPR>;
} }
multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryWithPolicy<intrinsic, instruction, defm : VPatTernaryWithPolicy<intrinsic, instruction,
"V"#vti.ScalarSuffix, "V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>; vti.ScalarRegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type> { list<VTypeInfo> vtilist, Operand Imm_type> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernaryNoMaskNoPolicy<intrinsic, instruction, "VI", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, Imm_type>; vti.RegClass, Imm_type>;
} }
multiclass VPatTernaryW_VV<string intrinsic, string instruction, multiclass VPatTernaryW_VV<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach vtiToWti = vtilist in { foreach vtiToWti = vtilist in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
Show All 21 Linesmulticlass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,
: VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>, : VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>,
VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>; VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>;
multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type = simm5> list<VTypeInfo> vtilist, Operand Imm_type = simm5>
: VPatTernaryV_VX<intrinsic, instruction, vtilist>, : VPatTernaryV_VX<intrinsic, instruction, vtilist>,
VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>; VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;
multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction, multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist> list<VTypeInfo> vtilist>
: VPatBinaryM_VV<intrinsic, instruction, vtilist>, : VPatBinaryM_VV<intrinsic, instruction, vtilist>,
VPatBinaryM_VX<intrinsic, instruction, vtilist>, VPatBinaryM_VX<intrinsic, instruction, vtilist>,
VPatBinaryM_VI<intrinsic, instruction, vtilist>; VPatBinaryM_VI<intrinsic, instruction, vtilist>;
multiclass VPatTernaryW_VV_VX<string intrinsic, string instruction, multiclass VPatTernaryW_VV_VX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> list<VTypeInfoToWide> vtilist>
▲ Show 20 Lines • Show All 1,474 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,901 Lines • ▼ Show 20 Lines
foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in {
def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
uimm5:$rs2, (vti.Mask true_mask), uimm5:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX)
vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask), GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX)
vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
uimm5:$rs2, (vti.Mask true_mask), uimm5:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX)
vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask), GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX)
vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} // Predicates = [HasVInstructions] } // Predicates = [HasVInstructions]

llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: $x5 = MUL killed $x5, killed $x1 ; CHECK-NEXT: $x5 = MUL killed $x5, killed $x1
; CHECK-NEXT: $x1 = LUI 1 ; CHECK-NEXT: $x1 = LUI 1
; CHECK-NEXT: $x1 = ADDIW killed $x1, -1888 ; CHECK-NEXT: $x1 = ADDIW killed $x1, -1888
; CHECK-NEXT: $x1 = ADD $x2, killed $x1 ; CHECK-NEXT: $x1 = ADD $x2, killed $x1
; CHECK-NEXT: $x1 = ADD killed $x1, killed $x5 ; CHECK-NEXT: $x1 = ADD killed $x1, killed $x5
; CHECK-NEXT: $x5 = LD $x2, 0 :: (load (s64) from %stack.16) ; CHECK-NEXT: $x5 = LD $x2, 0 :: (load (s64) from %stack.16)
; CHECK-NEXT: renamable $v0 = PseudoVRELOAD_M1 killed $x1 :: (load unknown-size from %stack.1, align 8) ; CHECK-NEXT: renamable $v0 = PseudoVRELOAD_M1 killed $x1 :: (load unknown-size from %stack.1, align 8)
; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.15) ; CHECK-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.15)
; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2 ; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31 ; CHECK-NEXT: liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x10 = COPY killed renamable $x13 ; CHECK-NEXT: renamable $x10 = COPY killed renamable $x13
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.0:
renamable $x11 = ANDI renamable $x15, 255 renamable $x11 = ANDI renamable $x15, 255
renamable $x13 = SLLI renamable $x11, 3 renamable $x13 = SLLI renamable $x11, 3
renamable $x13 = ADD renamable $x26, killed renamable $x13 renamable $x13 = ADD renamable $x26, killed renamable $x13
renamable $x13 = LD killed renamable $x13, 0 :: (load (s64)) renamable $x13 = LD killed renamable $x13, 0 :: (load (s64))
renamable $x16 = SUB killed renamable $x13, renamable $x13 renamable $x16 = SUB killed renamable $x13, renamable $x13
dead renamable $x13 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype dead renamable $x13 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
renamable $x13 = nsw ADDI renamable $x16, -2 renamable $x13 = nsw ADDI renamable $x16, -2
renamable $v0 = PseudoVRELOAD_M1 %stack.1 :: (load unknown-size from %stack.1, align 8) renamable $v0 = PseudoVRELOAD_M1 %stack.1 :: (load unknown-size from %stack.1, align 8)
renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, implicit $vl, implicit $vtype renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3, implicit $vl, implicit $vtype renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3, implicit $vl, implicit $vtype
BLT killed renamable $x16, renamable $x27, %bb.2 BLT killed renamable $x16, renamable $x27, %bb.2
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31 liveins: $x1, $x5, $x6, $x7, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
renamable $x10 = COPY killed renamable $x13 renamable $x10 = COPY killed renamable $x13
PseudoBR %bb.2 PseudoBR %bb.2
bb.2: bb.2:
PseudoRET PseudoRET
... ...

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) { define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
; CHECK-LABEL: extract_nxv6f16_nxv12f16_6: ; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v14, v10, a0 ; CHECK-NEXT: vslidedown.vx v14, v10, a0
; CHECK-NEXT: vslidedown.vx v12, v9, a0 ; CHECK-NEXT: vslidedown.vx v12, v9, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v13, v14, 0 ; CHECK-NEXT: vslideup.vi v13, v14, 0
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v12, v10, a0 ; CHECK-NEXT: vslideup.vx v12, v10, a0
; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6) %res = call <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
ret <vscale x 6 x half> %res ret <vscale x 6 x half> %res
} }
declare <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64) declare <vscale x 6 x half> @llvm.experimental.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

Show First 20 Lines • Show All 1,445 Lines • ▼ Show 20 Lines
; LMULMAX8-NEXT: vse32.v v8, (sp) ; LMULMAX8-NEXT: vse32.v v8, (sp)
; LMULMAX8-NEXT: li a0, 8 ; LMULMAX8-NEXT: li a0, 8
; LMULMAX8-NEXT: sd a0, 128(sp) ; LMULMAX8-NEXT: sd a0, 128(sp)
; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; LMULMAX8-NEXT: vmv.v.i v16, 0 ; LMULMAX8-NEXT: vmv.v.i v16, 0
; LMULMAX8-NEXT: vmerge.vim v16, v16, 1, v0 ; LMULMAX8-NEXT: vmerge.vim v16, v16, 1, v0
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX8-NEXT: vmv.v.i v17, 0 ; LMULMAX8-NEXT: vmv.v.i v17, 0
; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX8-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX8-NEXT: vslideup.vi v17, v16, 0 ; LMULMAX8-NEXT: vslideup.vi v17, v16, 0
; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX8-NEXT: vmsne.vi v16, v17, 0 ; LMULMAX8-NEXT: vmsne.vi v16, v17, 0
; LMULMAX8-NEXT: addi a0, sp, 136 ; LMULMAX8-NEXT: addi a0, sp, 136
; LMULMAX8-NEXT: li a5, 5 ; LMULMAX8-NEXT: li a5, 5
; LMULMAX8-NEXT: li a6, 6 ; LMULMAX8-NEXT: li a6, 6
; LMULMAX8-NEXT: li a7, 7 ; LMULMAX8-NEXT: li a7, 7
; LMULMAX8-NEXT: vsm.v v16, (a0) ; LMULMAX8-NEXT: vsm.v v16, (a0)
Show All 21 Lines
; LMULMAX4-NEXT: vse32.v v8, (sp) ; LMULMAX4-NEXT: vse32.v v8, (sp)
; LMULMAX4-NEXT: addi a0, sp, 64 ; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; LMULMAX4-NEXT: vmv.v.i v12, 0 ; LMULMAX4-NEXT: vmv.v.i v12, 0
; LMULMAX4-NEXT: vmerge.vim v12, v12, 1, v0 ; LMULMAX4-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX4-NEXT: vmv.v.i v13, 0 ; LMULMAX4-NEXT: vmv.v.i v13, 0
; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX4-NEXT: vslideup.vi v13, v12, 0 ; LMULMAX4-NEXT: vslideup.vi v13, v12, 0
; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX4-NEXT: vmsne.vi v12, v13, 0 ; LMULMAX4-NEXT: vmsne.vi v12, v13, 0
; LMULMAX4-NEXT: addi a0, sp, 136 ; LMULMAX4-NEXT: addi a0, sp, 136
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
; LMULMAX4-NEXT: li a7, 7 ; LMULMAX4-NEXT: li a7, 7
; LMULMAX4-NEXT: vsm.v v12, (a0) ; LMULMAX4-NEXT: vsm.v v12, (a0)
Show All 27 Lines
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: addi a0, sp, 32 ; LMULMAX2-NEXT: addi a0, sp, 32
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; LMULMAX2-NEXT: vmv.v.i v10, 0 ; LMULMAX2-NEXT: vmv.v.i v10, 0
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmv.v.i v11, 0 ; LMULMAX2-NEXT: vmv.v.i v11, 0
; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v11, v10, 0 ; LMULMAX2-NEXT: vslideup.vi v11, v10, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v10, v11, 0 ; LMULMAX2-NEXT: vmsne.vi v10, v11, 0
; LMULMAX2-NEXT: addi a0, sp, 136 ; LMULMAX2-NEXT: addi a0, sp, 136
; LMULMAX2-NEXT: li a5, 5 ; LMULMAX2-NEXT: li a5, 5
; LMULMAX2-NEXT: li a6, 6 ; LMULMAX2-NEXT: li a6, 6
; LMULMAX2-NEXT: li a7, 7 ; LMULMAX2-NEXT: li a7, 7
; LMULMAX2-NEXT: vsm.v v10, (a0) ; LMULMAX2-NEXT: vsm.v v10, (a0)
Show All 39 Lines
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: addi a0, sp, 16 ; LMULMAX1-NEXT: addi a0, sp, 16
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v10, 0 ; LMULMAX1-NEXT: vmv.v.i v10, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 0 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v9, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v9, v10, 0
; LMULMAX1-NEXT: addi a0, sp, 136 ; LMULMAX1-NEXT: addi a0, sp, 136
; LMULMAX1-NEXT: li a5, 5 ; LMULMAX1-NEXT: li a5, 5
; LMULMAX1-NEXT: li a6, 6 ; LMULMAX1-NEXT: li a6, 6
; LMULMAX1-NEXT: li a7, 7 ; LMULMAX1-NEXT: li a7, 7
; LMULMAX1-NEXT: vsm.v v9, (a0) ; LMULMAX1-NEXT: vsm.v v9, (a0)
Show All 27 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

Show First 20 Lines • Show All 552 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = trunc <2 x i8> %x to <2 x i1> %y = trunc <2 x i8> %x to <2 x i1>
store <2 x i1> %y, <2 x i1>* %z store <2 x i1> %y, <2 x i1>* %z
ret void ret void
▲ Show 20 Lines • Show All 274 Lines • ▼ Show 20 Lines
} }
define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) { define void @truncstore_v16i16_v16i8(<16 x i16> %x, <16 x i8>* %z) {
; LMULMAX1-LABEL: truncstore_v16i16_v16i8: ; LMULMAX1-LABEL: truncstore_v16i16_v16i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i16_v16i8: ; LMULMAX4-LABEL: truncstore_v16i16_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i8: ; LMULMAX4-LABEL: truncstore_v8i32_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v10 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v10
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i32> %x to <8 x i8> %y = trunc <8 x i32> %x to <8 x i8>
store <8 x i8> %y, <8 x i8>* %z store <8 x i8> %y, <8 x i8>* %z
ret void ret void
} }
define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) { define void @truncstore_v8i32_v8i16(<8 x i32> %x, <8 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v8i32_v8i16: ; LMULMAX1-LABEL: truncstore_v8i32_v8i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i32_v8i16: ; LMULMAX4-LABEL: truncstore_v8i32_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i8: ; LMULMAX4-LABEL: truncstore_v16i32_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v12
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i32> %x to <16 x i8> %y = trunc <16 x i32> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) { define void @truncstore_v16i32_v16i16(<16 x i32> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i32_v16i16: ; LMULMAX1-LABEL: truncstore_v16i32_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i32_v16i16: ; LMULMAX4-LABEL: truncstore_v16i32_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i8: ; LMULMAX4-LABEL: truncstore_v4i64_v4i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
Show All 14 Lines
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i16: ; LMULMAX4-LABEL: truncstore_v4i64_v4i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v10 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v10
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <4 x i64> %x to <4 x i16> %y = trunc <4 x i64> %x to <4 x i16>
store <4 x i16> %y, <4 x i16>* %z store <4 x i16> %y, <4 x i16>* %z
ret void ret void
} }
define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) { define void @truncstore_v4i64_v4i32(<4 x i64> %x, <4 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v4i64_v4i32: ; LMULMAX1-LABEL: truncstore_v4i64_v4i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v4i64_v4i32: ; LMULMAX4-LABEL: truncstore_v4i64_v4i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v10, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v10, v8
Show All 14 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i8: ; LMULMAX4-LABEL: truncstore_v8i64_v8i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v8
Show All 14 Lines
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i16: ; LMULMAX4-LABEL: truncstore_v8i64_v8i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v12
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <8 x i64> %x to <8 x i16> %y = trunc <8 x i64> %x to <8 x i16>
store <8 x i16> %y, <8 x i16>* %z store <8 x i16> %y, <8 x i16>* %z
ret void ret void
} }
define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) { define void @truncstore_v8i64_v8i32(<8 x i64> %x, <8 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v8i64_v8i32: ; LMULMAX1-LABEL: truncstore_v8i64_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v8i64_v8i32: ; LMULMAX4-LABEL: truncstore_v8i64_v8i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
Show All 16 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v12 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 10, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 8
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v13 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v13
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 10 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 10
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v14 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v14
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 14, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 12
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v15 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v15
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 14 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 14
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i8: ; LMULMAX4-LABEL: truncstore_v16i64_v16i8:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v16, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v16, v12
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v16 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v16
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v12
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v14, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v14, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v14 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v14
; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v8
; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse8.v v8, (a0) ; LMULMAX4-NEXT: vse8.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i8> %y = trunc <16 x i64> %x to <16 x i8>
store <16 x i8> %y, <16 x i8>* %z store <16 x i8> %y, <16 x i8>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) { define void @truncstore_v16i64_v16i16(<16 x i64> %x, <16 x i16>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i16: ; LMULMAX1-LABEL: truncstore_v16i64_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v13 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v13
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v10, v12 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v14 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v14
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v15 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v15
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 6
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i16: ; LMULMAX4-LABEL: truncstore_v16i64_v16i16:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v16, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v16, v12
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v12, v16 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v16
; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v14, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v14, v8
; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; LMULMAX4-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v8, v14 ; LMULMAX4-NEXT: vncvt.x.x.w v8, v14
; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; LMULMAX4-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX4-NEXT: vslideup.vi v8, v12, 8
; LMULMAX4-NEXT: vse16.v v8, (a0) ; LMULMAX4-NEXT: vse16.v v8, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i16> %y = trunc <16 x i64> %x to <16 x i16>
store <16 x i16> %y, <16 x i16>* %z store <16 x i16> %y, <16 x i16>* %z
ret void ret void
} }
define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) { define void @truncstore_v16i64_v16i32(<16 x i64> %x, <16 x i32>* %z) {
; LMULMAX1-LABEL: truncstore_v16i64_v16i32: ; LMULMAX1-LABEL: truncstore_v16i64_v16i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v13 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v13
; LMULMAX1-NEXT: vncvt.x.x.w v11, v12 ; LMULMAX1-NEXT: vncvt.x.x.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v11, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v11, v9, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v15 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v15
; LMULMAX1-NEXT: vncvt.x.x.w v12, v14 ; LMULMAX1-NEXT: vncvt.x.x.w v12, v14
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v12, v9, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v9, 2
; LMULMAX1-NEXT: addi a1, a0, 48 ; LMULMAX1-NEXT: addi a1, a0, 48
; LMULMAX1-NEXT: vse32.v v12, (a1) ; LMULMAX1-NEXT: vse32.v v12, (a1)
; LMULMAX1-NEXT: addi a1, a0, 32 ; LMULMAX1-NEXT: addi a1, a0, 32
; LMULMAX1-NEXT: vse32.v v11, (a1) ; LMULMAX1-NEXT: vse32.v v11, (a1)
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: vse32.v v10, (a1) ; LMULMAX1-NEXT: vse32.v v10, (a1)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX4-LABEL: truncstore_v16i64_v16i32: ; LMULMAX4-LABEL: truncstore_v16i64_v16i32:
; LMULMAX4: # %bb.0: ; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX4-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX4-NEXT: vncvt.x.x.w v16, v12 ; LMULMAX4-NEXT: vncvt.x.x.w v16, v12
; LMULMAX4-NEXT: vncvt.x.x.w v12, v8 ; LMULMAX4-NEXT: vncvt.x.x.w v12, v8
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX4-NEXT: vslideup.vi v12, v16, 8 ; LMULMAX4-NEXT: vslideup.vi v12, v16, 8
; LMULMAX4-NEXT: vse32.v v12, (a0) ; LMULMAX4-NEXT: vse32.v v12, (a0)
; LMULMAX4-NEXT: ret ; LMULMAX4-NEXT: ret
%y = trunc <16 x i64> %x to <16 x i32> %y = trunc <16 x i64> %x to <16 x i32>
store <16 x i32> %y, <16 x i32>* %z store <16 x i32> %y, <16 x i32>* %z
ret void ret void
} }
▲ Show 20 Lines • Show All 313 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v0, (a0) ; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_0: ; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0) ; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
Show All 11 Lines
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX2-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX2-NEXT: vmsne.vi v0, v8, 0
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_2: ; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0) ; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
Show All 12 Lines
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
; LMULMAX2-NEXT: vslidedown.vi v8, v8, 10 ; LMULMAX2-NEXT: vslidedown.vi v8, v8, 10
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX2-NEXT: vmsne.vi v0, v8, 0
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmv.v.i v9, 0 ; LMULMAX2-NEXT: vmv.v.i v9, 0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX2-NEXT: vslideup.vi v9, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX2-NEXT: vmsne.vi v8, v9, 0
; LMULMAX2-NEXT: vsm.v v8, (a1) ; LMULMAX2-NEXT: vsm.v v8, (a1)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: extract_v2i1_v64i1_42: ; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 4 ; LMULMAX1-NEXT: addi a0, a0, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v0, (a0) ; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 10 ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 10
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v8, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v8, v9, 0
; LMULMAX1-NEXT: vsm.v v8, (a1) ; LMULMAX1-NEXT: vsm.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x %a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_0: ; CHECK-LABEL: extract_v2i1_nxv2i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv2i1_2: ; CHECK-LABEL: extract_v2i1_nxv2i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_0: ; CHECK-LABEL: extract_v2i1_nxv64i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv64i1_2: ; CHECK-LABEL: extract_v2i1_nxv64i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
Show All 9 Lines
; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
} }
define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) { define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
; CHECK-LABEL: extract_v2i1_nxv32i1_26: ; CHECK-LABEL: extract_v2i1_nxv32i1_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 26 ; CHECK-NEXT: vslidedown.vi v8, v8, 26
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26) %c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, <2 x i1>* %y store <2 x i1> %c, <2 x i1>* %y
ret void ret void
Show All 35 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
define void @buildvec_dominant0_v4f32(<4 x float>* %x) { define void @buildvec_dominant0_v4f32(<4 x float>* %x) {
; CHECK-LABEL: buildvec_dominant0_v4f32: ; CHECK-LABEL: buildvec_dominant0_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: lui a1, %hi(.LCPI4_0) ; CHECK-NEXT: lui a1, %hi(.LCPI4_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0)
; CHECK-NEXT: vlse32.v v8, (a1), zero ; CHECK-NEXT: vlse32.v v8, (a1), zero
; CHECK-NEXT: vmv.s.x v9, zero ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant1_v4f32: ; CHECK-LABEL: buildvec_dominant1_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v8, zero ; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0 %v0 = insertelement <4 x float> poison, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 0.0, i32 1 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant2_v4f32: ; CHECK-LABEL: buildvec_dominant2_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI6_0) ; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1) ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> poison, float %f, i32 0 %v0 = insertelement <4 x float> poison, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
▲ Show 20 Lines • Show All 162 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a2, a0, 16 ; LMULMAX1-NEXT: addi a2, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a0) ; LMULMAX1-NEXT: vle32.v v8, (a0)
; LMULMAX1-NEXT: vle32.v v9, (a2) ; LMULMAX1-NEXT: vle32.v v9, (a2)
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x float>, <8 x float>* %x %a = load <8 x float>, <8 x float>* %x
%d = fptrunc <8 x float> %a to <8 x half> %d = fptrunc <8 x float> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
Show All 23 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v11 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptrunc <8 x double> %a to <8 x half> %d = fptrunc <8 x double> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

Show All 40 Lines
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1) ; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y %b = load <4 x float>, <4 x float>* %y
%c = fcmp une <4 x float> %a, %b %c = fcmp une <4 x float> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) { define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vv_v4f32_nonans: ; CHECK-LABEL: fcmp_une_vv_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v9, (a1) ; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y %b = load <4 x float>, <4 x float>* %y
%c = fcmp nnan une <4 x float> %a, %b %c = fcmp nnan une <4 x float> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) { define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64: ; CHECK-LABEL: fcmp_ogt_vv_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1) ; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y %b = load <2 x double>, <2 x double>* %y
%c = fcmp ogt <2 x double> %a, %b %c = fcmp ogt <2 x double> %a, %b
store <2 x i1> %c, <2 x i1>* %z store <2 x i1> %c, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) { define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_vv_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v9, (a1) ; CHECK-NEXT: vle64.v v9, (a1)
; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y %b = load <2 x double>, <2 x double>* %y
%c = fcmp nnan ogt <2 x double> %a, %b %c = fcmp nnan ogt <2 x double> %a, %b
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1) ; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y %b = load <4 x double>, <4 x double>* %y
%c = fcmp ole <4 x double> %a, %b %c = fcmp ole <4 x double> %a, %b
store <4 x i1> %c, <4 x i1>* %z store <4 x i1> %c, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) { define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_vv_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v10, (a1) ; CHECK-NEXT: vle64.v v10, (a1)
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y %b = load <4 x double>, <4 x double>* %y
%c = fcmp nnan ole <4 x double> %a, %b %c = fcmp nnan ole <4 x double> %a, %b
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmfeq.vv v8, v8, v8 ; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmfeq.vv v9, v9, v9 ; CHECK-NEXT: vmfeq.vv v9, v9, v9
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = load <4 x half>, <4 x half>* %y %b = load <4 x half>, <4 x half>* %y
%c = fcmp ord <4 x half> %a, %b %c = fcmp ord <4 x half> %a, %b
Show All 10 Lines
; CHECK-NEXT: vmfne.vv v8, v8, v8 ; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmfne.vv v9, v9, v9 ; CHECK-NEXT: vmfne.vv v9, v9, v9
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a2) ; CHECK-NEXT: vsm.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = load <2 x half>, <2 x half>* %y %b = load <2 x half>, <2 x half>* %y
%c = fcmp uno <2 x half> %a, %b %c = fcmp uno <2 x half> %a, %b
Show All 39 Lines
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> poison, float %y, i32 0 %b = insertelement <4 x float> poison, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
%d = fcmp une <4 x float> %a, %c %d = fcmp une <4 x float> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans: ; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> poison, float %y, i32 0 %b = insertelement <4 x float> poison, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
%d = fcmp nnan une <4 x float> %a, %c %d = fcmp nnan une <4 x float> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64: ; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> poison, double %y, i32 0 %b = insertelement <2 x double> poison, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
%d = fcmp ogt <2 x double> %a, %c %d = fcmp ogt <2 x double> %a, %c
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> poison, double %y, i32 0 %b = insertelement <2 x double> poison, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> poison, double %y, i32 0 %b = insertelement <4 x double> poison, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
%d = fcmp ole <4 x double> %a, %c %d = fcmp ole <4 x double> %a, %c
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_vf_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> poison, double %y, i32 0 %b = insertelement <4 x double> poison, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmfeq.vf v9, v9, fa0 ; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8 ; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> poison, half %y, i32 0 %b = insertelement <4 x half> poison, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
Show All 11 Lines
; CHECK-NEXT: vmfne.vf v9, v9, fa0 ; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8 ; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> poison, half %y, i32 0 %b = insertelement <2 x half> poison, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
Show All 40 Lines
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> poison, float %y, i32 0 %b = insertelement <4 x float> poison, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
%d = fcmp une <4 x float> %c, %a %d = fcmp une <4 x float> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) { define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans: ; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> poison, float %y, i32 0 %b = insertelement <4 x float> poison, float %y, i32 0
%c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x float> %b, <4 x float> poison, <4 x i32> zeroinitializer
%d = fcmp nnan une <4 x float> %c, %a %d = fcmp nnan une <4 x float> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64: ; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> poison, double %y, i32 0 %b = insertelement <2 x double> poison, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
%d = fcmp ogt <2 x double> %c, %a %d = fcmp ogt <2 x double> %c, %a
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }
define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) { define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans: ; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> poison, double %y, i32 0 %b = insertelement <2 x double> poison, double %y, i32 0
%c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x double> %b, <2 x double> poison, <2 x i32> zeroinitializer
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> poison, double %y, i32 0 %b = insertelement <4 x double> poison, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
%d = fcmp ole <4 x double> %c, %a %d = fcmp ole <4 x double> %c, %a
store <4 x i1> %d, <4 x i1>* %z store <4 x i1> %d, <4 x i1>* %z
ret void ret void
} }
define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) { define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans: ; CHECK-LABEL: fcmp_ole_fv_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x %a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> poison, double %y, i32 0 %b = insertelement <4 x double> poison, double %y, i32 0
%c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> zeroinitializer
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmfeq.vf v9, v9, fa0 ; CHECK-NEXT: vmfeq.vf v9, v9, fa0
; CHECK-NEXT: vmfeq.vv v8, v8, v8 ; CHECK-NEXT: vmfeq.vv v8, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x %a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> poison, half %y, i32 0 %b = insertelement <4 x half> poison, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer %c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
Show All 11 Lines
; CHECK-NEXT: vmfne.vf v9, v9, fa0 ; CHECK-NEXT: vmfne.vf v9, v9, fa0
; CHECK-NEXT: vmfne.vv v8, v8, v8 ; CHECK-NEXT: vmfne.vv v8, v8, v8
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x %a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> poison, half %y, i32 0 %b = insertelement <2 x half> poison, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer %c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
%d = fcmp uno <2 x half> %c, %a %d = fcmp uno <2 x half> %c, %a
store <2 x i1> %d, <2 x i1>* %z store <2 x i1> %d, <2 x i1>* %z
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x float> @splice_unary(<8 x float> %x) { define <8 x float> @splice_unary(<8 x float> %x) {
; CHECK-LABEL: splice_unary: ; CHECK-LABEL: splice_unary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v8, 7 ; CHECK-NEXT: vslideup.vi v10, v8, 7
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0> %s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x double> @splice_unary2(<8 x double> %x) { define <8 x double> @splice_unary2(<8 x double> %x) {
; CHECK-LABEL: splice_unary2: ; CHECK-LABEL: splice_unary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v12, v8, 6 ; CHECK-NEXT: vslidedown.vi v12, v8, 6
; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v12, v8, 2 ; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x double> %x, <8 x double> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> %s = shufflevector <8 x double> %x, <8 x double> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
ret <8 x double> %s ret <8 x double> %s
} }
define <8 x float> @splice_binary(<8 x float> %x, <8 x float> %y) { define <8 x float> @splice_binary(<8 x float> %x, <8 x float> %y) {
; CHECK-LABEL: splice_binary: ; CHECK-LABEL: splice_binary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 6 ; CHECK-NEXT: vslideup.vi v8, v10, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9> %s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9>
ret <8 x float> %s ret <8 x float> %s
} }
define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) { define <8 x double> @splice_binary2(<8 x double> %x, <8 x double> %y) {
; CHECK-LABEL: splice_binary2: ; CHECK-LABEL: splice_binary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 3, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v12, v12, 5 ; CHECK-NEXT: vslidedown.vi v12, v12, 5
; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v12, v8, 3 ; CHECK-NEXT: vslideup.vi v12, v8, 3
; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x double> %x, <8 x double> %y, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x double> %s ret <8 x double> %s
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v10, 1 ; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptosi <8 x float> %x to <8 x i1> %z = fptosi <8 x float> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) { define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) {
; LMULMAX8-LABEL: fp2ui_v8f32_v8i1: ; LMULMAX8-LABEL: fp2ui_v8f32_v8i1:
Show All 15 Lines
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v9
; LMULMAX1-NEXT: vand.vi v9, v10, 1 ; LMULMAX1-NEXT: vand.vi v9, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptoui <8 x float> %x to <8 x i1> %z = fptoui <8 x float> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) { define void @fp2si_v2f32_v2i64(<2 x float>* %x, <2 x i64>* %y) {
; CHECK-LABEL: fp2si_v2f32_v2i64: ; CHECK-LABEL: fp2si_v2f32_v2i64:
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v11 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v11, v12 ; LMULMAX1-NEXT: vncvt.x.x.w v11, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v11, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v11, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptosi <8 x double> %a to <8 x i8> %d = fptosi <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
} }
Show All 29 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v10, v10 ; LMULMAX1-NEXT: vncvt.x.x.w v10, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v11 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v11, v12 ; LMULMAX1-NEXT: vncvt.x.x.w v11, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v11, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v11, v11
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v11 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse8.v v10, (a1) ; LMULMAX1-NEXT: vse8.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x double>, <8 x double>* %x %a = load <8 x double>, <8 x double>* %x
%d = fptoui <8 x double> %a to <8 x i8> %d = fptoui <8 x double> %a to <8 x i8>
store <8 x i8> %d, <8 x i8>* %y store <8 x i8> %d, <8 x i8>* %y
ret void ret void
} }
Show All 18 Lines
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v9 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v13, 1 ; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v12, v13, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v13, v10
; LMULMAX1-NEXT: vand.vi v10, v13, 1 ; LMULMAX1-NEXT: vand.vi v10, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 4 ; LMULMAX1-NEXT: vslideup.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11 ; LMULMAX1-NEXT: vfncvt.rtz.x.f.w v10, v11
; LMULMAX1-NEXT: vand.vi v10, v10, 1 ; LMULMAX1-NEXT: vand.vi v10, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptosi <8 x double> %x to <8 x i1> %z = fptosi <8 x double> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }
define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) { define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) {
; LMULMAX8-LABEL: fp2ui_v8f64_v8i1: ; LMULMAX8-LABEL: fp2ui_v8f64_v8i1:
Show All 15 Lines
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v9 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v9
; LMULMAX1-NEXT: vand.vi v9, v13, 1 ; LMULMAX1-NEXT: vand.vi v9, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v9, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v9, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v9, 0 ; LMULMAX1-NEXT: vmv.v.i v9, 0
; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v13, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v12, v13, 2 ; LMULMAX1-NEXT: vslideup.vi v12, v13, 2
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v12, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v13, v10
; LMULMAX1-NEXT: vand.vi v10, v13, 1 ; LMULMAX1-NEXT: vand.vi v10, v13, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v10, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v12, v10, 4 ; LMULMAX1-NEXT: vslideup.vi v12, v10, 4
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v12, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v12, 0
; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v8, v8, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11 ; LMULMAX1-NEXT: vfncvt.rtz.xu.f.w v10, v11
; LMULMAX1-NEXT: vand.vi v10, v10, 1 ; LMULMAX1-NEXT: vand.vi v10, v10, 1
; LMULMAX1-NEXT: vmsne.vi v0, v10, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v10, 0
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0 ; LMULMAX1-NEXT: vmerge.vim v9, v9, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 6 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v0, v8, 0 ; LMULMAX1-NEXT: vmsne.vi v0, v8, 0
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%z = fptoui <8 x double> %x to <8 x i1> %z = fptoui <8 x double> %x to <8 x i1>
ret <8 x i1> %z ret <8 x i1> %z
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

Show First 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10 ; LMULMAX1-NEXT: vfncvt.f.x.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v12, v11 ; LMULMAX1-NEXT: vfncvt.f.x.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v11, v9 ; LMULMAX1-NEXT: vfncvt.f.x.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8 ; LMULMAX1-NEXT: vfncvt.f.x.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = sitofp <8 x i64> %a to <8 x half> %d = sitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
Show All 23 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10 ; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v10
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v11 ; LMULMAX1-NEXT: vfncvt.f.xu.w v12, v11
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12 ; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v11, 2 ; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v11, v9 ; LMULMAX1-NEXT: vfncvt.f.xu.w v11, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11 ; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8 ; LMULMAX1-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9 ; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
; LMULMAX1-NEXT: vse16.v v10, (a1) ; LMULMAX1-NEXT: vse16.v v10, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%d = uitofp <8 x i64> %a to <8 x half> %d = uitofp <8 x i64> %a to <8 x half>
store <8 x half> %d, <8 x half>* %y store <8 x half> %d, <8 x half>* %y
ret void ret void
} }
Show All 24 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

Show All 22 Lines
define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; RV32-LABEL: insertelt_idx_v1i1: ; RV32-LABEL: insertelt_idx_v1i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vand.vi v8, v9, 1 ; RV32-NEXT: vand.vi v8, v9, 1
; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_idx_v1i1: ; RV64-LABEL: insertelt_idx_v1i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vand.vi v8, v9, 1 ; RV64-NEXT: vand.vi v8, v9, 1
; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i32 %idx %y = insertelement <1 x i1> %x, i1 %elt, i32 %idx
ret <1 x i1> %y ret <1 x i1> %y
} }
define <2 x i1> @insertelt_v2i1(<2 x i1> %x, i1 %elt) nounwind { define <2 x i1> @insertelt_v2i1(<2 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v2i1: ; CHECK-LABEL: insertelt_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <2 x i1> %x, i1 %elt, i64 1 %y = insertelement <2 x i1> %x, i1 %elt, i64 1
ret <2 x i1> %y ret <2 x i1> %y
} }
define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; RV32-LABEL: insertelt_idx_v2i1: ; RV32-LABEL: insertelt_idx_v2i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vand.vi v8, v9, 1 ; RV32-NEXT: vand.vi v8, v9, 1
; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_idx_v2i1: ; RV64-LABEL: insertelt_idx_v2i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vand.vi v8, v9, 1 ; RV64-NEXT: vand.vi v8, v9, 1
; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
%y = insertelement <2 x i1> %x, i1 %elt, i32 %idx %y = insertelement <2 x i1> %x, i1 %elt, i32 %idx
ret <2 x i1> %y ret <2 x i1> %y
} }
define <8 x i1> @insertelt_v8i1(<8 x i1> %x, i1 %elt) nounwind { define <8 x i1> @insertelt_v8i1(<8 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v8i1: ; CHECK-LABEL: insertelt_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i64 1 %y = insertelement <8 x i1> %x, i1 %elt, i64 1
ret <8 x i1> %y ret <8 x i1> %y
} }
define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; RV32-LABEL: insertelt_idx_v8i1: ; RV32-LABEL: insertelt_idx_v8i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; RV32-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vx v9, v8, a1 ; RV32-NEXT: vslideup.vx v9, v8, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vand.vi v8, v9, 1 ; RV32-NEXT: vand.vi v8, v9, 1
; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_idx_v8i1: ; RV64-LABEL: insertelt_idx_v8i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; RV64-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vx v9, v8, a0 ; RV64-NEXT: vslideup.vx v9, v8, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vand.vi v8, v9, 1 ; RV64-NEXT: vand.vi v8, v9, 1
; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i32 %idx %y = insertelement <8 x i1> %x, i1 %elt, i32 %idx
ret <8 x i1> %y ret <8 x i1> %y
} }
define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind { define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v64i1: ; CHECK-LABEL: insertelt_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v12, v8, 1 ; CHECK-NEXT: vslideup.vi v12, v8, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vand.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v12, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i64 1 %y = insertelement <64 x i1> %x, i1 %elt, i64 1
ret <64 x i1> %y ret <64 x i1> %y
} }
define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; RV32-LABEL: insertelt_idx_v64i1: ; RV32-LABEL: insertelt_idx_v64i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 64 ; RV32-NEXT: li a2, 64
; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vmerge.vim v12, v12, 1, v0 ; RV32-NEXT: vmerge.vim v12, v12, 1, v0
; RV32-NEXT: addi a0, a1, 1 ; RV32-NEXT: addi a0, a1, 1
; RV32-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; RV32-NEXT: vslideup.vx v12, v8, a1 ; RV32-NEXT: vslideup.vx v12, v8, a1
; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; RV32-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; RV32-NEXT: vand.vi v8, v12, 1 ; RV32-NEXT: vand.vi v8, v12, 1
; RV32-NEXT: vmsne.vi v0, v8, 0 ; RV32-NEXT: vmsne.vi v0, v8, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_idx_v64i1: ; RV64-LABEL: insertelt_idx_v64i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a2, 64 ; RV64-NEXT: li a2, 64
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vmerge.vim v12, v12, 1, v0 ; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: sext.w a0, a1 ; RV64-NEXT: sext.w a0, a1
; RV64-NEXT: addi a1, a0, 1 ; RV64-NEXT: addi a1, a0, 1
; RV64-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; RV64-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; RV64-NEXT: vslideup.vx v12, v8, a0 ; RV64-NEXT: vslideup.vx v12, v8, a0
; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu ; RV64-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; RV64-NEXT: vand.vi v8, v12, 1 ; RV64-NEXT: vand.vi v8, v12, 1
; RV64-NEXT: vmsne.vi v0, v8, 0 ; RV64-NEXT: vmsne.vi v0, v8, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i32 %idx %y = insertelement <64 x i1> %x, i1 %elt, i32 %idx
ret <64 x i1> %y ret <64 x i1> %y
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_0: ; CHECK-LABEL: insert_nxv8i32_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 0 ; CHECK-NEXT: vslideup.vi v8, v12, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_2: ; CHECK-LABEL: insert_nxv8i32_v2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 2 ; CHECK-NEXT: vslideup.vi v8, v12, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 2)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v2i32_6(<vscale x 8 x i32> %vec, <2 x i32>* %svp) {
; CHECK-LABEL: insert_nxv8i32_v2i32_6: ; CHECK-LABEL: insert_nxv8i32_v2i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v12, (a0) ; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 6 ; CHECK-NEXT: vslideup.vi v8, v12, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6) %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, <8 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, <8 x i32>* %svp) {
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m4, ta, mu
; LMULMAX2-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX2-NEXT: vslideup.vi v8, v12, 0
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0: ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v12, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v12, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e32, m4, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v16, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v16, 4
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp %sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0) %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, <8 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, <8 x i32>* %svp) {
; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v12, (a0) ; LMULMAX2-NEXT: vle32.v v12, (a0)
; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX2-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX2-NEXT: vslideup.vi v8, v12, 8
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8: ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v12, (a0) ; LMULMAX1-NEXT: vle32.v v12, (a0)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vle32.v v16, (a0) ; LMULMAX1-NEXT: vle32.v v16, (a0)
; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 12, e32, m4, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v12, 8 ; LMULMAX1-NEXT: vslideup.vi v8, v12, 8
; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v16, 12 ; LMULMAX1-NEXT: vslideup.vi v8, v16, 12
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <8 x i32>, <8 x i32>* %svp %sv = load <8 x i32>, <8 x i32>* %svp
%v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8) %v = call <vscale x 8 x i32> @llvm.experimental.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 8)
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(<2 x i32>* %svp) { define <vscale x 8 x i32> @insert_nxv8i32_undef_v2i32_0(<2 x i32>* %svp) {
Show All 9 Lines
define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_v2i32_0(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_0: ; CHECK-LABEL: insert_v4i32_v2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp %vec = load <4 x i32>, <4 x i32>* %vp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
} }
define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v4i32_v2i32_2(<4 x i32>* %vp, <2 x i32>* %svp) {
; CHECK-LABEL: insert_v4i32_v2i32_2: ; CHECK-LABEL: insert_v4i32_v2i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a1) ; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a0) ; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vse32.v v9, (a0) ; CHECK-NEXT: vse32.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <4 x i32>, <4 x i32>* %vp %vec = load <4 x i32>, <4 x i32>* %vp
%v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <4 x i32> @llvm.experimental.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 2)
store <4 x i32> %v, <4 x i32>* %vp store <4 x i32> %v, <4 x i32>* %vp
ret void ret void
Show All 15 Lines
define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_0(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_0: ; LMULMAX2-LABEL: insert_v8i32_v2i32_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v10, v8, 0 ; LMULMAX2-NEXT: vslideup.vi v10, v8, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v8i32_v2i32_0: ; LMULMAX1-LABEL: insert_v8i32_v2i32_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 0 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 0
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0) %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_2(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_2: ; LMULMAX2-LABEL: insert_v8i32_v2i32_2:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetivli zero, 4, e32, m2, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 4, e32, m2, ta, mu
; LMULMAX2-NEXT: vslideup.vi v10, v8, 2 ; LMULMAX2-NEXT: vslideup.vi v10, v8, 2
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v8i32_v2i32_2: ; LMULMAX1-LABEL: insert_v8i32_v2i32_2:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2) %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 2)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
} }
define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) { define void @insert_v8i32_v2i32_6(<8 x i32>* %vp, <2 x i32>* %svp) {
; LMULMAX2-LABEL: insert_v8i32_v2i32_6: ; LMULMAX2-LABEL: insert_v8i32_v2i32_6:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX2-NEXT: vle32.v v8, (a1) ; LMULMAX2-NEXT: vle32.v v8, (a1)
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-NEXT: vle32.v v10, (a0) ; LMULMAX2-NEXT: vle32.v v10, (a0)
; LMULMAX2-NEXT: vsetvli zero, zero, e32, m2, tu, mu
; LMULMAX2-NEXT: vslideup.vi v10, v8, 6 ; LMULMAX2-NEXT: vslideup.vi v10, v8, 6
; LMULMAX2-NEXT: vse32.v v10, (a0) ; LMULMAX2-NEXT: vse32.v v10, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v8i32_v2i32_6: ; LMULMAX1-LABEL: insert_v8i32_v2i32_6:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; LMULMAX1-NEXT: vle32.v v8, (a1) ; LMULMAX1-NEXT: vle32.v v8, (a1)
; LMULMAX1-NEXT: addi a0, a0, 16 ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vle32.v v9, (a0) ; LMULMAX1-NEXT: vle32.v v9, (a0)
; LMULMAX1-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; LMULMAX1-NEXT: vslideup.vi v9, v8, 2 ; LMULMAX1-NEXT: vslideup.vi v9, v8, 2
; LMULMAX1-NEXT: vse32.v v9, (a0) ; LMULMAX1-NEXT: vse32.v v9, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%sv = load <2 x i32>, <2 x i32>* %svp %sv = load <2 x i32>, <2 x i32>* %svp
%vec = load <8 x i32>, <8 x i32>* %vp %vec = load <8 x i32>, <8 x i32>* %vp
%v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6) %v = call <8 x i32> @llvm.experimental.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 6)
store <8 x i32> %v, <8 x i32>* %vp store <8 x i32> %v, <8 x i32>* %vp
ret void ret void
Show All 26 Lines
define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) { define void @insert_v4i16_v2i16_0(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_0: ; CHECK-LABEL: insert_v4i16_v2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp %v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0) %c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0)
store <4 x i16> %c, <4 x i16>* %vp store <4 x i16> %c, <4 x i16>* %vp
ret void ret void
} }
define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) { define void @insert_v4i16_v2i16_2(<4 x i16>* %vp, <2 x i16>* %svp) {
; CHECK-LABEL: insert_v4i16_v2i16_2: ; CHECK-LABEL: insert_v4i16_v2i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %vp %v = load <4 x i16>, <4 x i16>* %vp
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2) %c = call <4 x i16> @llvm.experimental.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 2)
store <4 x i16> %c, <4 x i16>* %vp store <4 x i16> %c, <4 x i16>* %vp
ret void ret void
} }
define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) { define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2-LABEL: insert_v32i1_v8i1_0: ; LMULMAX2-LABEL: insert_v32i1_v8i1_0:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vlm.v v9, (a1) ; LMULMAX2-NEXT: vlm.v v9, (a1)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; LMULMAX2-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX2-NEXT: vslideup.vi v8, v9, 0
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v32i1_v8i1_0: ; LMULMAX1-LABEL: insert_v32i1_v8i1_0:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp %v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0) %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 0)
store <32 x i1> %c, <32 x i1>* %vp store <32 x i1> %c, <32 x i1>* %vp
ret void ret void
} }
define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) { define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2-LABEL: insert_v32i1_v8i1_16: ; LMULMAX2-LABEL: insert_v32i1_v8i1_16:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: li a2, 32 ; LMULMAX2-NEXT: li a2, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vlm.v v8, (a0) ; LMULMAX2-NEXT: vlm.v v8, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vlm.v v9, (a1) ; LMULMAX2-NEXT: vlm.v v9, (a1)
; LMULMAX2-NEXT: vsetivli zero, 3, e8, mf4, tu, mu ; LMULMAX2-NEXT: vsetivli zero, 3, e8, mf4, ta, mu
; LMULMAX2-NEXT: vslideup.vi v8, v9, 2 ; LMULMAX2-NEXT: vslideup.vi v8, v9, 2
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu ; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vsm.v v8, (a0) ; LMULMAX2-NEXT: vsm.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: insert_v32i1_v8i1_16: ; LMULMAX1-LABEL: insert_v32i1_v8i1_16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 2 ; LMULMAX1-NEXT: addi a0, a0, 2
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vlm.v v8, (a0) ; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vlm.v v9, (a1) ; LMULMAX1-NEXT: vlm.v v9, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 0 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-NEXT: vsm.v v8, (a0) ; LMULMAX1-NEXT: vsm.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp %v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16) %c = call <32 x i1> @llvm.experimental.vector.insert.v8i1.v32i1(<32 x i1> %v, <8 x i1> %sv, i64 16)
store <32 x i1> %c, <32 x i1>* %vp store <32 x i1> %c, <32 x i1>* %vp
Show All 9 Lines
; CHECK-NEXT: vlm.v v8, (a1) ; CHECK-NEXT: vlm.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp %v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0) %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 0)
Show All 10 Lines
; CHECK-NEXT: vlm.v v8, (a1) ; CHECK-NEXT: vlm.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp %v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4) %c = call <8 x i1> @llvm.experimental.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)
store <8 x i1> %c, <8 x i1>* %vp store <8 x i1> %c, <8 x i1>* %vp
ret void ret void
} }
define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i16>* %svp) { define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
; CHECK-LABEL: insert_nxv2i16_v2i16_0: ; CHECK-LABEL: insert_nxv2i16_v2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0) %c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)
ret <vscale x 2 x i16> %c ret <vscale x 2 x i16> %c
} }
define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i16>* %svp) { define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, <2 x i16>* %svp) {
; CHECK-LABEL: insert_nxv2i16_v2i16_2: ; CHECK-LABEL: insert_nxv2i16_v2i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v9, (a0) ; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vsetivli zero, 6, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 6, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <2 x i16>, <2 x i16>* %svp %sv = load <2 x i16>, <2 x i16>* %svp
%c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4) %c = call <vscale x 2 x i16> @llvm.experimental.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 4)
ret <vscale x 2 x i16> %c ret <vscale x 2 x i16> %c
} }
define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) { define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %svp) {
; CHECK-LABEL: insert_nxv2i1_v4i1_0: ; CHECK-LABEL: insert_nxv2i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <4 x i1>, <4 x i1>* %svp %sv = load <4 x i1>, <4 x i1>* %svp
%c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0) %c = call <vscale x 2 x i1> @llvm.experimental.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
ret <vscale x 2 x i1> %c ret <vscale x 2 x i1> %c
} }
define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) { define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
; CHECK-LABEL: insert_nxv8i1_v4i1_0: ; CHECK-LABEL: insert_nxv8i1_v4i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v0, v8, 0 ; CHECK-NEXT: vslideup.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0) %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 0)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) { define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>* %svp) {
; CHECK-LABEL: insert_nxv8i1_v8i1_16: ; CHECK-LABEL: insert_nxv8i1_v8i1_16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vlm.v v8, (a0) ; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv = load <8 x i1>, <8 x i1>* %svp %sv = load <8 x i1>, <8 x i1>* %svp
%c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16) %c = call <vscale x 8 x i1> @llvm.experimental.vector.insert.v8i1.nxv8i1(<vscale x 8 x i1> %v, <8 x i1> %sv, i64 16)
ret <vscale x 8 x i1> %c ret <vscale x 8 x i1> %c
} }
declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64) declare <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64>, <2 x i64>, i64)
define void @insert_v2i64_nxv16i64(<2 x i64>* %psv0, <2 x i64>* %psv1, <vscale x 16 x i64>* %out) { define void @insert_v2i64_nxv16i64(<2 x i64>* %psv0, <2 x i64>* %psv1, <vscale x 16 x i64>* %out) {
; CHECK-LABEL: insert_v2i64_nxv16i64: ; CHECK-LABEL: insert_v2i64_nxv16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v16, (a1) ; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: vsetivli zero, 6, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 6, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 4 ; CHECK-NEXT: vslideup.vi v8, v16, 4
; CHECK-NEXT: vs8r.v v8, (a2) ; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%sv0 = load <2 x i64>, <2 x i64>* %psv0 %sv0 = load <2 x i64>, <2 x i64>* %psv0
%sv1 = load <2 x i64>, <2 x i64>* %psv1 %sv1 = load <2 x i64>, <2 x i64>* %psv1
%v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0) %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
%v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4) %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
▲ Show 20 Lines • Show All 82 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; FIXME: This codegen needs to be improved. These tests previously asserted ; FIXME: This codegen needs to be improved. These tests previously asserted
; type legalizing the i64 type on RV32. ; type legalizing the i64 type on RV32.
define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) { define void @insertelt_v4i64(<4 x i64>* %x, i64 %y) {
; RV32-LABEL: insertelt_v4i64: ; RV32-LABEL: insertelt_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vslide1up.vx v12, v10, a2 ; RV32-NEXT: vslide1up.vx v12, v10, a2
; RV32-NEXT: vslide1up.vx v10, v12, a1 ; RV32-NEXT: vslide1up.vx v10, v12, a1
; RV32-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vslideup.vi v8, v10, 3 ; RV32-NEXT: vslideup.vi v8, v10, 3
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v4i64: ; RV64-LABEL: insertelt_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.s.x v10, a1 ; RV64-NEXT: vmv.s.x v10, a1
; RV64-NEXT: vsetvli zero, zero, e64, m2, tu, mu
; RV64-NEXT: vslideup.vi v8, v10, 3 ; RV64-NEXT: vslideup.vi v8, v10, 3
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = insertelement <4 x i64> %a, i64 %y, i32 3 %b = insertelement <4 x i64> %a, i64 %y, i32 3
store <4 x i64> %b, <4 x i64>* %x store <4 x i64> %b, <4 x i64>* %x
ret void ret void
} }
; This uses a non-power of 2 type so that it isn't an MVT. ; This uses a non-power of 2 type so that it isn't an MVT.
; The align keeps the type legalizer from using a 256 bit load so we must split ; The align keeps the type legalizer from using a 256 bit load so we must split
; it. This some operations that weren't support for scalable vectors when ; it. This some operations that weren't support for scalable vectors when
; this test was written. ; this test was written.
define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) { define void @insertelt_v3i64(<3 x i64>* %x, i64 %y) {
; RV32-LABEL: insertelt_v3i64: ; RV32-LABEL: insertelt_v3i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: lw a3, 16(a0) ; RV32-NEXT: lw a3, 16(a0)
; RV32-NEXT: addi a4, a0, 20 ; RV32-NEXT: addi a4, a0, 20
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vlse32.v v10, (a4), zero ; RV32-NEXT: vlse32.v v10, (a4), zero
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-NEXT: vmv.s.x v10, a3 ; RV32-NEXT: vmv.s.x v10, a3
; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vslideup.vi v8, v10, 2 ; RV32-NEXT: vslideup.vi v8, v10, 2
; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vslide1up.vx v12, v10, a2 ; RV32-NEXT: vslide1up.vx v12, v10, a2
; RV32-NEXT: vslide1up.vx v10, v12, a1 ; RV32-NEXT: vslide1up.vx v10, v12, a1
; RV32-NEXT: vsetivli zero, 3, e64, m2, tu, mu ; RV32-NEXT: vsetivli zero, 3, e64, m2, ta, mu
; RV32-NEXT: vslideup.vi v8, v10, 2 ; RV32-NEXT: vslideup.vi v8, v10, 2
; RV32-NEXT: sw a1, 16(a0) ; RV32-NEXT: sw a1, 16(a0)
; RV32-NEXT: sw a2, 20(a0) ; RV32-NEXT: sw a2, 20(a0)
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v3i64: ; RV64-LABEL: insertelt_v3i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: sd a1, 16(a0) ; RV64-NEXT: sd a1, 16(a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <3 x i64>, <3 x i64>* %x, align 8 %a = load <3 x i64>, <3 x i64>* %x, align 8
%b = insertelement <3 x i64> %a, i64 %y, i32 2 %b = insertelement <3 x i64> %a, i64 %y, i32 2
store <3 x i64> %b, <3 x i64>* %x store <3 x i64> %b, <3 x i64>* %x
ret void ret void
} }
define void @insertelt_v16i8(<16 x i8>* %x, i8 %y) { define void @insertelt_v16i8(<16 x i8>* %x, i8 %y) {
; CHECK-LABEL: insertelt_v16i8: ; CHECK-LABEL: insertelt_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: vsetivli zero, 15, e8, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 15, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 14 ; CHECK-NEXT: vslideup.vi v8, v9, 14
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x %a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> %a, i8 %y, i32 14 %b = insertelement <16 x i8> %a, i8 %y, i32 14
store <16 x i8> %b, <16 x i8>* %x store <16 x i8> %b, <16 x i8>* %x
ret void ret void
} }
define void @insertelt_v32i16(<32 x i16>* %x, i16 %y, i32 %idx) { define void @insertelt_v32i16(<32 x i16>* %x, i16 %y, i32 %idx) {
; RV32-LABEL: insertelt_v32i16: ; RV32-LABEL: insertelt_v32i16:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; RV32-NEXT: vle16.v v8, (a0) ; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vmv.s.x v12, a1 ; RV32-NEXT: vmv.s.x v12, a1
; RV32-NEXT: addi a1, a2, 1 ; RV32-NEXT: addi a1, a2, 1
; RV32-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: vslideup.vx v8, v12, a2 ; RV32-NEXT: vslideup.vx v8, v12, a2
; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV32-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; RV32-NEXT: vse16.v v8, (a0) ; RV32-NEXT: vse16.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v32i16: ; RV64-LABEL: insertelt_v32i16:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a3, 32 ; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: vmv.s.x v12, a1 ; RV64-NEXT: vmv.s.x v12, a1
; RV64-NEXT: sext.w a1, a2 ; RV64-NEXT: sext.w a1, a2
; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e16, m4, tu, mu ; RV64-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, mu
; RV64-NEXT: vse16.v v8, (a0) ; RV64-NEXT: vse16.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <32 x i16>, <32 x i16>* %x %a = load <32 x i16>, <32 x i16>* %x
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx %b = insertelement <32 x i16> %a, i16 %y, i32 %idx
store <32 x i16> %b, <32 x i16>* %x store <32 x i16> %b, <32 x i16>* %x
ret void ret void
} }
define void @insertelt_v8f32(<8 x float>* %x, float %y, i32 %idx) { define void @insertelt_v8f32(<8 x float>* %x, float %y, i32 %idx) {
; RV32-LABEL: insertelt_v8f32: ; RV32-LABEL: insertelt_v8f32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vfmv.s.f v10, fa0 ; RV32-NEXT: vfmv.s.f v10, fa0
; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e32, m2, tu, mu ; RV32-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; RV32-NEXT: vslideup.vx v8, v10, a1 ; RV32-NEXT: vslideup.vx v8, v10, a1
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v8f32: ; RV64-LABEL: insertelt_v8f32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vfmv.s.f v10, fa0 ; RV64-NEXT: vfmv.s.f v10, fa0
; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e32, m2, tu, mu ; RV64-NEXT: vsetvli zero, a2, e32, m2, ta, mu
; RV64-NEXT: vslideup.vx v8, v10, a1 ; RV64-NEXT: vslideup.vx v8, v10, a1
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <8 x float>, <8 x float>* %x %a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> %a, float %y, i32 %idx %b = insertelement <8 x float> %a, float %y, i32 %idx
store <8 x float> %b, <8 x float>* %x store <8 x float> %b, <8 x float>* %x
ret void ret void
Show All 18 Lines
define void @insertelt_v8i64(<8 x i64>* %x, i32 %idx) { define void @insertelt_v8i64(<8 x i64>* %x, i32 %idx) {
; RV32-LABEL: insertelt_v8i64: ; RV32-LABEL: insertelt_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a2, -1 ; RV32-NEXT: li a2, -1
; RV32-NEXT: vmv.s.x v12, a2 ; RV32-NEXT: vmv.s.x v12, a2
; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vslideup.vx v8, v12, a1 ; RV32-NEXT: vslideup.vx v8, v12, a1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_v8i64: ; RV64-LABEL: insertelt_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: li a2, -1 ; RV64-NEXT: li a2, -1
; RV64-NEXT: vmv.s.x v12, a2 ; RV64-NEXT: vmv.s.x v12, a2
; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV64-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 -1, i32 %idx %b = insertelement <8 x i64> %a, i64 -1, i32 %idx
store <8 x i64> %b, <8 x i64>* %x store <8 x i64> %b, <8 x i64>* %x
ret void ret void
Show All 18 Lines
define void @insertelt_c6_v8i64(<8 x i64>* %x, i32 %idx) { define void @insertelt_c6_v8i64(<8 x i64>* %x, i32 %idx) {
; RV32-LABEL: insertelt_c6_v8i64: ; RV32-LABEL: insertelt_c6_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a2, 6 ; RV32-NEXT: li a2, 6
; RV32-NEXT: vmv.s.x v12, a2 ; RV32-NEXT: vmv.s.x v12, a2
; RV32-NEXT: addi a2, a1, 1 ; RV32-NEXT: addi a2, a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV32-NEXT: vslideup.vx v8, v12, a1 ; RV32-NEXT: vslideup.vx v8, v12, a1
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: insertelt_c6_v8i64: ; RV64-LABEL: insertelt_c6_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: li a2, 6 ; RV64-NEXT: li a2, 6
; RV64-NEXT: vmv.s.x v12, a2 ; RV64-NEXT: vmv.s.x v12, a2
; RV64-NEXT: sext.w a1, a1 ; RV64-NEXT: sext.w a1, a1
; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: addi a2, a1, 1
; RV64-NEXT: vsetvli zero, a2, e64, m4, tu, mu ; RV64-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; RV64-NEXT: vslideup.vx v8, v12, a1 ; RV64-NEXT: vslideup.vx v8, v12, a1
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 %idx %b = insertelement <8 x i64> %a, i64 6, i32 %idx
store <8 x i64> %b, <8 x i64>* %x store <8 x i64> %b, <8 x i64>* %x
ret void ret void
Show All 24 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
; FIXME: RV32 doesn't catch this pattern due to BUILD_VECTOR legalization. ; FIXME: RV32 doesn't catch this pattern due to BUILD_VECTOR legalization.
define <4 x i64> @buildvec_vid_step1_add0_v4i64() { define <4 x i64> @buildvec_vid_step1_add0_v4i64() {
; RV32-LABEL: buildvec_vid_step1_add0_v4i64: ; RV32-LABEL: buildvec_vid_step1_add0_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; RV32-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; RV32-NEXT: vslideup.vi v8, v9, 2 ; RV32-NEXT: vslideup.vi v8, v9, 2
; RV32-NEXT: lui a0, %hi(.LCPI12_0) ; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vle32.v v9, (a0) ; RV32-NEXT: vle32.v v9, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: buildvec_vid_step1_add0_v4i64: ; RV64-LABEL: buildvec_vid_step1_add0_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vid.v v8 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vi v9, v8, 2 ; RV64-NEXT: vadd.vi v9, v8, 2
; RV64-NEXT: ret ; RV64-NEXT: ret
ret <4 x i64> <i64 0, i64 1, i64 2, i64 3> ret <4 x i64> <i64 0, i64 1, i64 2, i64 3>
} }
define <4 x i64> @buildvec_vid_step2_add0_v4i64() { define <4 x i64> @buildvec_vid_step2_add0_v4i64() {
; RV32-LABEL: buildvec_vid_step2_add0_v4i64: ; RV32-LABEL: buildvec_vid_step2_add0_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 2 ; RV32-NEXT: li a0, 2
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; RV32-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; RV32-NEXT: vslideup.vi v8, v9, 2 ; RV32-NEXT: vslideup.vi v8, v9, 2
; RV32-NEXT: lui a0, %hi(.LCPI13_0) ; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vle32.v v9, (a0) ; RV32-NEXT: vle32.v v9, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: buildvec_vid_step2_add0_v4i64: ; RV64-LABEL: buildvec_vid_step2_add0_v4i64:
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
} }
define void @buildvec_dominant0_v8i16(<8 x i16>* %x) { define void @buildvec_dominant0_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: buildvec_dominant0_v8i16: ; CHECK-LABEL: buildvec_dominant0_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vmv.s.x v8, zero ; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vmv.v.i v9, 8 ; CHECK-NEXT: vmv.v.i v9, 8
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 3 ; CHECK-NEXT: vslideup.vi v9, v8, 3
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, <8 x i16>* %x store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, <8 x i16>* %x
ret void ret void
} }
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v8, v8, 1 ; RV32-NEXT: vsrl.vi v8, v8, 1
; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: vmv.v.i v9, 1 ; RV32-NEXT: vmv.v.i v9, 1
; RV32-NEXT: vse32.v v8, (a2) ; RV32-NEXT: vse32.v v8, (a2)
; RV32-NEXT: vse32.v v8, (a3) ; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: vse32.v v8, (a4) ; RV32-NEXT: vse32.v v8, (a4)
; RV32-NEXT: vmv.s.x v8, zero ; RV32-NEXT: vmv.s.x v8, zero
; RV32-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32-NEXT: vslideup.vi v9, v8, 1 ; RV32-NEXT: vslideup.vi v9, v8, 1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vse32.v v9, (a5) ; RV32-NEXT: vse32.v v9, (a5)
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-NEXT: vslideup.vi v9, v8, 3 ; RV32-NEXT: vslideup.vi v9, v8, 3
; RV32-NEXT: vse32.v v9, (a6) ; RV32-NEXT: vse32.v v9, (a6)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: buildvec_vid_step1o2_v4i32: ; RV64-LABEL: buildvec_vid_step1o2_v4i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vid.v v8 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vsrl.vi v8, v8, 1 ; RV64-NEXT: vsrl.vi v8, v8, 1
; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: vmv.v.i v9, 1 ; RV64-NEXT: vmv.v.i v9, 1
; RV64-NEXT: vse32.v v8, (a1) ; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: vse32.v v8, (a2) ; RV64-NEXT: vse32.v v8, (a2)
; RV64-NEXT: vse32.v v8, (a3) ; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: vse32.v v8, (a4) ; RV64-NEXT: vse32.v v8, (a4)
; RV64-NEXT: vmv.s.x v8, zero ; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; RV64-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64-NEXT: vslideup.vi v9, v8, 1 ; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vse32.v v9, (a5) ; RV64-NEXT: vse32.v v9, (a5)
; RV64-NEXT: li a0, 1 ; RV64-NEXT: li a0, 1
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV64-NEXT: vslideup.vi v9, v8, 3 ; RV64-NEXT: vslideup.vi v9, v8, 3
; RV64-NEXT: vse32.v v9, (a6) ; RV64-NEXT: vse32.v v9, (a6)
; RV64-NEXT: ret ; RV64-NEXT: ret
store <4 x i32> <i32 0, i32 0, i32 1, i32 1>, <4 x i32>* %z0 store <4 x i32> <i32 0, i32 0, i32 1, i32 1>, <4 x i32>* %z0
store <4 x i32> <i32 0, i32 0, i32 1, i32 undef>, <4 x i32>* %z1 store <4 x i32> <i32 0, i32 0, i32 1, i32 undef>, <4 x i32>* %z1
store <4 x i32> <i32 0, i32 undef, i32 1, i32 1>, <4 x i32>* %z2 store <4 x i32> <i32 0, i32 undef, i32 1, i32 1>, <4 x i32>* %z2
store <4 x i32> <i32 undef, i32 0, i32 undef, i32 1>, <4 x i32>* %z3 store <4 x i32> <i32 undef, i32 0, i32 undef, i32 1>, <4 x i32>* %z3
store <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>, <4 x i32>* %z4 store <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>, <4 x i32>* %z4
Show All 15 Lines
; CHECK-NEXT: vmv.v.i v9, 3 ; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: vse16.v v8, (a3) ; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: vse16.v v8, (a4) ; CHECK-NEXT: vse16.v v8, (a4)
; CHECK-NEXT: li a0, 3 ; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v8, 1 ; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vse16.v v10, (a5) ; CHECK-NEXT: vse16.v v10, (a5)
; CHECK-NEXT: li a0, 4 ; CHECK-NEXT: li a0, 4
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 3 ; CHECK-NEXT: vslideup.vi v9, v8, 3
; CHECK-NEXT: vse16.v v9, (a6) ; CHECK-NEXT: vse16.v v9, (a6)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x i16> <i16 3, i16 3, i16 4, i16 4>, <4 x i16>* %z0 store <4 x i16> <i16 3, i16 3, i16 4, i16 4>, <4 x i16>* %z0
store <4 x i16> <i16 3, i16 3, i16 4, i16 undef>, <4 x i16>* %z1 store <4 x i16> <i16 3, i16 3, i16 4, i16 undef>, <4 x i16>* %z1
store <4 x i16> <i16 3, i16 undef, i16 4, i16 4>, <4 x i16>* %z2 store <4 x i16> <i16 3, i16 undef, i16 4, i16 4>, <4 x i16>* %z2
store <4 x i16> <i16 undef, i16 3, i16 undef, i16 4>, <4 x i16>* %z3 store <4 x i16> <i16 undef, i16 3, i16 undef, i16 4>, <4 x i16>* %z3
store <4 x i16> <i16 3, i16 undef, i16 4, i16 undef>, <4 x i16>* %z4 store <4 x i16> <i16 3, i16 undef, i16 4, i16 undef>, <4 x i16>* %z4
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
; division to compute it. ; division to compute it.
define <16 x i8> @buildvec_not_vid_v16i8() { define <16 x i8> @buildvec_not_vid_v16i8() {
; CHECK-LABEL: buildvec_not_vid_v16i8: ; CHECK-LABEL: buildvec_not_vid_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 3 ; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 6 ; CHECK-NEXT: vslideup.vi v8, v9, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0> ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0>
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v8, v8 ; LMULMAX1-NEXT: vncvt.x.x.w v8, v8
; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu ; LMULMAX1-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; LMULMAX1-NEXT: vncvt.x.x.w v9, v9 ; LMULMAX1-NEXT: vncvt.x.x.w v9, v9
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vslideup.vi v8, v9, 4 ; LMULMAX1-NEXT: vslideup.vi v8, v9, 4
; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: vse8.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = trunc <8 x i32> %a to <8 x i8> %b = trunc <8 x i32> %a to <8 x i8>
store <8 x i8> %b, <8 x i8>* %z store <8 x i8> %b, <8 x i8>* %z
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines
} }
define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32-LABEL: vrgather_shuffle_vv_v8i64: ; RV32-LABEL: vrgather_shuffle_vv_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 5 ; RV32-NEXT: li a0, 5
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vmv.s.x v16, a0 ; RV32-NEXT: vmv.s.x v16, a0
; RV32-NEXT: vmv.v.i v20, 2
; RV32-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; RV32-NEXT: vslideup.vi v20, v16, 7
; RV32-NEXT: lui a0, %hi(.LCPI11_0) ; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vle16.v v20, (a0)
; RV32-NEXT: vle16.v v21, (a0) ; RV32-NEXT: vmv.v.i v21, 2
; RV32-NEXT: vslideup.vi v21, v16, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v8, v21 ; RV32-NEXT: vrgatherei16.vv v16, v8, v20
; RV32-NEXT: li a0, 164 ; RV32-NEXT: li a0, 164
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t ; RV32-NEXT: vrgatherei16.vv v16, v12, v21, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_vv_v8i64: ; RV64-LABEL: vrgather_shuffle_vv_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vmv.s.x v16, a0
; RV64-NEXT: vmv.v.i v20, 2
; RV64-NEXT: vsetvli zero, zero, e64, m4, tu, mu
; RV64-NEXT: vslideup.vi v20, v16, 7
; RV64-NEXT: lui a0, %hi(.LCPI11_0) ; RV64-NEXT: lui a0, %hi(.LCPI11_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV64-NEXT: vle64.v v20, (a0)
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: li a0, 5
; RV64-NEXT: vrgather.vv v16, v8, v24 ; RV64-NEXT: vmv.s.x v16, a0
; RV64-NEXT: vmv.v.i v24, 2
; RV64-NEXT: vslideup.vi v24, v16, 7
; RV64-NEXT: vrgather.vv v16, v8, v20
; RV64-NEXT: li a0, 164 ; RV64-NEXT: li a0, 164
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vrgather.vv v16, v12, v20, v0.t ; RV64-NEXT: vrgather.vv v16, v12, v24, v0.t
; RV64-NEXT: vmv.v.v v8, v16 ; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13> %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v8i64: ; RV32-LABEL: vrgather_shuffle_xv_v8i64:
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) { define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
; CHECK-LABEL: splat_ve4_ins_i1ve3: ; CHECK-LABEL: splat_ve4_ins_i1ve3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 3 ; CHECK-NEXT: li a0, 3
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v9, 1 ; CHECK-NEXT: vslideup.vi v10, v9, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4> %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4: ; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 4 ; CHECK-NEXT: li a0, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v11, v10, 2 ; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: li a0, 70 ; CHECK-NEXT: li a0, 70
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a0, 6 ; RV32-NEXT: li a0, 6
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.s.x v10, a0 ; RV32-NEXT: vmv.s.x v10, a0
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v11, v10, 5 ; RV32-NEXT: vslideup.vi v11, v10, 5
; RV32-NEXT: lui a0, 8256 ; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2 ; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: li a0, 98 ; RV32-NEXT: li a0, 98
; RV32-NEXT: vmv.s.x v0, a0 ; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vrgather.vv v10, v8, v12 ; RV32-NEXT: vrgather.vv v10, v8, v12
; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 6 ; RV64-NEXT: li a0, 6
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.s.x v10, a0 ; RV64-NEXT: vmv.s.x v10, a0
; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v11, v10, 5 ; RV64-NEXT: vslideup.vi v11, v10, 5
; RV64-NEXT: lui a0, 8256 ; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2 ; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: li a0, 98 ; RV64-NEXT: li a0, 98
; RV64-NEXT: vmv.s.x v0, a0 ; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vrgather.vv v10, v8, v12 ; RV64-NEXT: vrgather.vv v10, v8, v12
; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @widen_splat_ve3(<4 x i8> %v) { define <8 x i8> @widen_splat_ve3(<4 x i8> %v) {
; CHECK-LABEL: widen_splat_ve3: ; CHECK-LABEL: widen_splat_ve3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 3 ; CHECK-NEXT: vrgather.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuf = shufflevector <4 x i8> %v, <4 x i8> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> %shuf = shufflevector <4 x i8> %v, <4 x i8> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <8 x i8> %shuf ret <8 x i8> %shuf
} }
Show All 39 Lines; CHECK-NEXT: ret
ret <8 x i32> %s ret <8 x i32> %s
} }
define <8 x i16> @splice_unary(<8 x i16> %x) { define <8 x i16> @splice_unary(<8 x i16> %x) {
; CHECK-LABEL: splice_unary: ; CHECK-LABEL: splice_unary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v9, v8, 2 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 6 ; CHECK-NEXT: vslideup.vi v9, v8, 6
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1> %s = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
ret <8 x i16> %s ret <8 x i16> %s
} }
define <8 x i32> @splice_unary2(<8 x i32> %x) { define <8 x i32> @splice_unary2(<8 x i32> %x) {
; CHECK-LABEL: splice_unary2: ; CHECK-LABEL: splice_unary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v8, 5 ; CHECK-NEXT: vslidedown.vi v10, v8, 5
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v8, 3 ; CHECK-NEXT: vslideup.vi v10, v8, 3
; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4> %s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 undef, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x i32> %s ret <8 x i32> %s
} }
define <8 x i16> @splice_binary(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @splice_binary(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: splice_binary: ; CHECK-LABEL: splice_binary:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 6 ; CHECK-NEXT: vslideup.vi v8, v9, 6
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9> %s = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 9>
ret <8 x i16> %s ret <8 x i16> %s
} }
define <8 x i32> @splice_binary2(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @splice_binary2(<8 x i32> %x, <8 x i32> %y) {
; CHECK-LABEL: splice_binary2: ; CHECK-LABEL: splice_binary2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 3, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 5 ; CHECK-NEXT: vslidedown.vi v8, v8, 5
; CHECK-NEXT: vsetivli zero, 8, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12> %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
ret <8 x i32> %s ret <8 x i32> %s
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Show First 20 Lines • Show All 943 Lines • ▼ Show 20 Lines
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: li a1, 33 ; CHECK-NEXT: li a1, 33
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a1 ; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v10, 3 ; CHECK-NEXT: vmv.v.i v10, 3
; CHECK-NEXT: vmerge.vim v10, v10, 2, v0 ; CHECK-NEXT: vmerge.vim v10, v10, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v10, v9, 6 ; CHECK-NEXT: vslideup.vi v10, v9, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmv.s.x v12, a1 ; CHECK-NEXT: vmv.s.x v12, a1
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v11, v9, 6 ; CHECK-NEXT: vslideup.vi v11, v9, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: lui a1, %hi(.LCPI53_0) ; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0)
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vsrl.vv v11, v8, v11 ; CHECK-NEXT: vsrl.vv v11, v8, v11
; CHECK-NEXT: vmulhu.vv v9, v11, v9 ; CHECK-NEXT: vmulhu.vv v9, v11, v9
; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v9
Show All 11 Lines
define void @mulhu_v4i32(<4 x i32>* %x) { define void @mulhu_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: mulhu_v4i32: ; CHECK-LABEL: mulhu_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v10, v9, 2 ; CHECK-NEXT: vslideup.vi v10, v9, 2
; CHECK-NEXT: lui a1, %hi(.LCPI54_0) ; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v9, (a1) ; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmulhu.vv v9, v8, v9 ; CHECK-NEXT: vmulhu.vv v9, v8, v9
; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: vmulhu.vv v8, v8, v10 ; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vmv.s.x v9, a1 ; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: vmv.v.i v10, 2 ; CHECK-NEXT: vmv.v.i v10, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; CHECK-NEXT: vslideup.vi v10, v9, 3 ; CHECK-NEXT: vslideup.vi v10, v9, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x %a = load <4 x i32>, <4 x i32>* %x
%b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9> %b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9>
store <4 x i32> %b, <4 x i32>* %x store <4 x i32> %b, <4 x i32>* %x
ret void ret void
} }
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vi v10, v10, 1 ; RV32-NEXT: vsrl.vi v10, v10, 1
; RV32-NEXT: vrsub.vi v10, v10, 0 ; RV32-NEXT: vrsub.vi v10, v10, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vmadd.vv v10, v8, v9 ; RV32-NEXT: vmadd.vv v10, v8, v9
; RV32-NEXT: li a1, 1 ; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vmv.s.x v8, a1 ; RV32-NEXT: vmv.s.x v8, a1
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; RV32-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; RV32-NEXT: vslideup.vi v9, v8, 2 ; RV32-NEXT: vslideup.vi v9, v8, 2
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vsra.vv v8, v10, v9 ; RV32-NEXT: vsra.vv v8, v10, v9
; RV32-NEXT: li a1, 63 ; RV32-NEXT: li a1, 63
; RV32-NEXT: vsrl.vx v9, v10, a1 ; RV32-NEXT: vsrl.vx v9, v10, a1
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
▲ Show 20 Lines • Show All 2,977 Lines • ▼ Show 20 Lines
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, 524288 ; LMULMAX1-RV32-NEXT: lui a2, 524288
; LMULMAX1-RV32-NEXT: vmv.s.x v10, a2 ; LMULMAX1-RV32-NEXT: vmv.s.x v10, a2
; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vslideup.vi v11, v10, 2 ; LMULMAX1-RV32-NEXT: vslideup.vi v11, v10, 2
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0) ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0) ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vle32.v v10, (a2) ; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
; LMULMAX1-RV32-NEXT: vmulhu.vv v12, v9, v10 ; LMULMAX1-RV32-NEXT: vmulhu.vv v12, v9, v10
; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v12 ; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v9, v11 ; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: li a2, 1 ; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vmv.s.x v12, a2 ; LMULMAX1-RV32-NEXT: vmv.s.x v12, a2
; LMULMAX1-RV32-NEXT: vmv.v.i v13, 2 ; LMULMAX1-RV32-NEXT: vmv.v.i v13, 2
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; LMULMAX1-RV32-NEXT: vslideup.vi v13, v12, 3 ; LMULMAX1-RV32-NEXT: vslideup.vi v13, v12, 3
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v13 ; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v8, v10 ; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v13 ; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v9, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a1)
Show All 30 Lines
; LMULMAX2-RV32-NEXT: vle32.v v10, (a1) ; LMULMAX2-RV32-NEXT: vle32.v v10, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v8, v10 ; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, 524288 ; LMULMAX2-RV32-NEXT: lui a1, 524288
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmv.s.x v12, a1 ; LMULMAX2-RV32-NEXT: vmv.s.x v12, a1
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: vsetivli zero, 6, e32, m2, tu, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 6, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vslideup.vi v14, v12, 5 ; LMULMAX2-RV32-NEXT: vslideup.vi v14, v12, 5
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v14 ; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v14
; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; LMULMAX2-RV32-NEXT: vle32.v v10, (a1) ; LMULMAX2-RV32-NEXT: vle32.v v10, (a1)
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v4i64: ; LMULMAX2-RV64-LABEL: mulhu_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: li a1, -1 ; LMULMAX2-RV64-NEXT: li a1, -1
; LMULMAX2-RV64-NEXT: slli a1, a1, 63 ; LMULMAX2-RV64-NEXT: slli a1, a1, 63
; LMULMAX2-RV64-NEXT: vmv.s.x v10, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v10, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0 ; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, tu, mu ; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: vslideup.vi v12, v10, 2 ; LMULMAX2-RV64-NEXT: vslideup.vi v12, v10, 2
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; LMULMAX2-RV64-NEXT: vle64.v v10, (a1) ; LMULMAX2-RV64-NEXT: vle64.v v10, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10 ; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1)
▲ Show 20 Lines • Show All 3,171 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

Show First 20 Lines • Show All 661 Lines • ▼ Show 20 Lines
; RV32-LMULMAX4: # %bb.0: ; RV32-LMULMAX4: # %bb.0:
; RV32-LMULMAX4-NEXT: lui a0, 748388 ; RV32-LMULMAX4-NEXT: lui a0, 748388
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: lui a0, 748384 ; RV32-LMULMAX4-NEXT: lui a0, 748384
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX4-NEXT: ret ; RV32-LMULMAX4-NEXT: ret
; ;
; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1: ; RV64-LMULMAX4-LABEL: buildvec_mask_v64i1:
; RV64-LMULMAX4: # %bb.0: ; RV64-LMULMAX4: # %bb.0:
; RV64-LMULMAX4-NEXT: lui a0, %hi(.LCPI19_0) ; RV64-LMULMAX4-NEXT: lui a0, %hi(.LCPI19_0)
; RV64-LMULMAX4-NEXT: ld a0, %lo(.LCPI19_0)(a0) ; RV64-LMULMAX4-NEXT: ld a0, %lo(.LCPI19_0)(a0)
; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX4-NEXT: ret ; RV64-LMULMAX4-NEXT: ret
; ;
; RV32-LMULMAX8-LABEL: buildvec_mask_v64i1: ; RV32-LMULMAX8-LABEL: buildvec_mask_v64i1:
; RV32-LMULMAX8: # %bb.0: ; RV32-LMULMAX8: # %bb.0:
; RV32-LMULMAX8-NEXT: lui a0, 748388 ; RV32-LMULMAX8-NEXT: lui a0, 748388
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: lui a0, 748384 ; RV32-LMULMAX8-NEXT: lui a0, 748384
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX8-NEXT: ret ; RV32-LMULMAX8-NEXT: ret
; ;
; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1: ; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1:
; RV64-LMULMAX8: # %bb.0: ; RV64-LMULMAX8: # %bb.0:
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI19_0) ; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI19_0)
; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI19_0)(a0) ; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI19_0)(a0)
; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e64, m1, ta, mu
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; RV32-LMULMAX4: # %bb.0: ; RV32-LMULMAX4: # %bb.0:
; RV32-LMULMAX4-NEXT: lui a0, 748388 ; RV32-LMULMAX4-NEXT: lui a0, 748388
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-LMULMAX4-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: lui a0, 748384 ; RV32-LMULMAX4-NEXT: lui a0, 748384
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX4-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX4-NEXT: lui a0, 945060 ; RV32-LMULMAX4-NEXT: lui a0, 945060
; RV32-LMULMAX4-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX4-NEXT: addi a0, a0, -1793
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32-LMULMAX4-NEXT: vmv.s.x v9, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v9, a0
; RV32-LMULMAX4-NEXT: lui a0, 551776 ; RV32-LMULMAX4-NEXT: lui a0, 551776
; RV32-LMULMAX4-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX4-NEXT: addi a0, a0, 1776
; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX4-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX4-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-LMULMAX4-NEXT: vslideup.vi v8, v9, 1 ; RV32-LMULMAX4-NEXT: vslideup.vi v8, v9, 1
; RV32-LMULMAX4-NEXT: ret ; RV32-LMULMAX4-NEXT: ret
; ;
; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1: ; RV64-LMULMAX4-LABEL: buildvec_mask_v128i1:
; RV64-LMULMAX4: # %bb.0: ; RV64-LMULMAX4: # %bb.0:
; RV64-LMULMAX4-NEXT: lui a0, %hi(.LCPI20_0) ; RV64-LMULMAX4-NEXT: lui a0, %hi(.LCPI20_0)
; RV64-LMULMAX4-NEXT: ld a0, %lo(.LCPI20_0)(a0) ; RV64-LMULMAX4-NEXT: ld a0, %lo(.LCPI20_0)(a0)
; RV64-LMULMAX4-NEXT: lui a1, %hi(.LCPI20_1) ; RV64-LMULMAX4-NEXT: lui a1, %hi(.LCPI20_1)
; RV64-LMULMAX4-NEXT: ld a1, %lo(.LCPI20_1)(a1) ; RV64-LMULMAX4-NEXT: ld a1, %lo(.LCPI20_1)(a1)
; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX4-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX4-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX4-NEXT: vmv.s.x v8, a1 ; RV64-LMULMAX4-NEXT: vmv.s.x v8, a1
; RV64-LMULMAX4-NEXT: ret ; RV64-LMULMAX4-NEXT: ret
; ;
; RV32-LMULMAX8-LABEL: buildvec_mask_v128i1: ; RV32-LMULMAX8-LABEL: buildvec_mask_v128i1:
; RV32-LMULMAX8: # %bb.0: ; RV32-LMULMAX8: # %bb.0:
; RV32-LMULMAX8-NEXT: lui a0, 748388 ; RV32-LMULMAX8-NEXT: lui a0, 748388
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: lui a0, 748384 ; RV32-LMULMAX8-NEXT: lui a0, 748384
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, m1, tu, mu ; RV32-LMULMAX8-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV32-LMULMAX8-NEXT: lui a0, 551776 ; RV32-LMULMAX8-NEXT: lui a0, 551776
; RV32-LMULMAX8-NEXT: addi a0, a0, 1776 ; RV32-LMULMAX8-NEXT: addi a0, a0, 1776
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetivli zero, 3, e32, m1, tu, mu ; RV32-LMULMAX8-NEXT: vsetivli zero, 3, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 2 ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 2
; RV32-LMULMAX8-NEXT: lui a0, 945060 ; RV32-LMULMAX8-NEXT: lui a0, 945060
; RV32-LMULMAX8-NEXT: addi a0, a0, -1793 ; RV32-LMULMAX8-NEXT: addi a0, a0, -1793
; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV32-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV32-LMULMAX8-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; RV32-LMULMAX8-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 3 ; RV32-LMULMAX8-NEXT: vslideup.vi v0, v8, 3
; RV32-LMULMAX8-NEXT: ret ; RV32-LMULMAX8-NEXT: ret
; ;
; RV64-LMULMAX8-LABEL: buildvec_mask_v128i1: ; RV64-LMULMAX8-LABEL: buildvec_mask_v128i1:
; RV64-LMULMAX8: # %bb.0: ; RV64-LMULMAX8: # %bb.0:
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI20_0) ; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI20_0)
; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI20_0)(a0) ; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI20_0)(a0)
; RV64-LMULMAX8-NEXT: lui a1, %hi(.LCPI20_1) ; RV64-LMULMAX8-NEXT: lui a1, %hi(.LCPI20_1)
; RV64-LMULMAX8-NEXT: ld a1, %lo(.LCPI20_1)(a1) ; RV64-LMULMAX8-NEXT: ld a1, %lo(.LCPI20_1)(a1)
; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX8-NEXT: vmv.s.x v0, a1 ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a1
; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV64-LMULMAX8-NEXT: ret ; RV64-LMULMAX8-NEXT: ret
ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1> ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
} }
define <128 x i1> @buildvec_mask_optsize_v128i1() optsize { define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1: ; RV32-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1:
; RV32-LMULMAX1: # %bb.0: ; RV32-LMULMAX1: # %bb.0:
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) { define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
; CHECK-LABEL: load_store_v1i1: ; CHECK-LABEL: load_store_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <1 x i1>, <1 x i1>* %x %a = load <1 x i1>, <1 x i1>* %x
store <1 x i1> %a, <1 x i1>* %y store <1 x i1> %a, <1 x i1>* %y
ret void ret void
} }
define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) { define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
; CHECK-LABEL: load_store_v2i1: ; CHECK-LABEL: load_store_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x i1>, <2 x i1>* %x %a = load <2 x i1>, <2 x i1>* %x
store <2 x i1> %a, <2 x i1>* %y store <2 x i1> %a, <2 x i1>* %y
ret void ret void
} }
define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) { define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
; CHECK-LABEL: load_store_v4i1: ; CHECK-LABEL: load_store_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vlm.v v0, (a0) ; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: vsm.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i1>, <4 x i1>* %x %a = load <4 x i1>, <4 x i1>* %x
store <4 x i1> %a, <4 x i1>* %y store <4 x i1> %a, <4 x i1>* %y
ret void ret void
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1-RV64
define void @splat_ones_v1i1(<1 x i1>* %x) { define void @splat_ones_v1i1(<1 x i1>* %x) {
; CHECK-LABEL: splat_ones_v1i1: ; CHECK-LABEL: splat_ones_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <1 x i1> <i1 1>, <1 x i1>* %x store <1 x i1> <i1 1>, <1 x i1>* %x
ret void ret void
} }
define void @splat_zeros_v2i1(<2 x i1>* %x) { define void @splat_zeros_v2i1(<2 x i1>* %x) {
; CHECK-LABEL: splat_zeros_v2i1: ; CHECK-LABEL: splat_zeros_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i1> zeroinitializer, <2 x i1>* %x store <2 x i1> zeroinitializer, <2 x i1>* %x
ret void ret void
} }
define void @splat_v1i1(<1 x i1>* %x, i1 %y) { define void @splat_v1i1(<1 x i1>* %x, i1 %y) {
; CHECK-LABEL: splat_v1i1: ; CHECK-LABEL: splat_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = insertelement <1 x i1> poison, i1 %y, i32 0 %a = insertelement <1 x i1> poison, i1 %y, i32 0
%b = shufflevector <1 x i1> %a, <1 x i1> poison, <1 x i32> zeroinitializer %b = shufflevector <1 x i1> %a, <1 x i1> poison, <1 x i32> zeroinitializer
store <1 x i1> %b, <1 x i1>* %x store <1 x i1> %b, <1 x i1>* %x
ret void ret void
} }
define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) { define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) {
; CHECK-LABEL: splat_v1i1_icmp: ; CHECK-LABEL: splat_v1i1_icmp:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xor a1, a1, a2 ; CHECK-NEXT: xor a1, a1, a2
; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = icmp eq i32 %y, %z %c = icmp eq i32 %y, %z
%a = insertelement <1 x i1> poison, i1 %c, i32 0 %a = insertelement <1 x i1> poison, i1 %c, i32 0
%b = shufflevector <1 x i1> %a, <1 x i1> poison, <1 x i32> zeroinitializer %b = shufflevector <1 x i1> %a, <1 x i1> poison, <1 x i32> zeroinitializer
store <1 x i1> %b, <1 x i1>* %x store <1 x i1> %b, <1 x i1>* %x
ret void ret void
} }
define void @splat_ones_v4i1(<4 x i1>* %x) { define void @splat_ones_v4i1(<4 x i1>* %x) {
; CHECK-LABEL: splat_ones_v4i1: ; CHECK-LABEL: splat_ones_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
ret void ret void
} }
define void @splat_v4i1(<4 x i1>* %x, i1 %y) { define void @splat_v4i1(<4 x i1>* %x, i1 %y) {
; CHECK-LABEL: splat_v4i1: ; CHECK-LABEL: splat_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1 ; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v8, v9, 0 ; CHECK-NEXT: vmsne.vi v8, v9, 0
; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = insertelement <4 x i1> poison, i1 %y, i32 0 %a = insertelement <4 x i1> poison, i1 %y, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer
store <4 x i1> %b, <4 x i1>* %x store <4 x i1> %b, <4 x i1>* %x
▲ Show 20 Lines • Show All 210 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Show First 20 Lines • Show All 2,172 Lines • ▼ Show 20 Lines
; RV64-NEXT: vslidedown.vi v8, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: li a0, 32 ; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; RV64-NEXT: vslideup.vi v12, v10, 16 ; RV64-NEXT: vslideup.vi v12, v10, 16
; RV64-NEXT: vmv2r.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru) %v = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, i32 2, <32 x i1> %m, <32 x i8> %passthru)
ret <32 x i8> %v ret <32 x i8> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15 ; RV32-NEXT: addi a0, sp, 15
; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: beqz a1, .LBB4_2 ; RV32-NEXT: beqz a1, .LBB4_2
Show All 14 Lines
; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: lb a1, 1(a0) ; RV32-NEXT: lb a1, 1(a0)
; RV32-NEXT: lbu a0, 0(a0) ; RV32-NEXT: lbu a0, 0(a0)
; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: slli a1, a1, 8
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV32-NEXT: vmv.s.x v8, a0 ; RV32-NEXT: vmv.s.x v8, a0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
; RV32-NEXT: vslideup.vi v9, v8, 1 ; RV32-NEXT: vslideup.vi v9, v8, 1
; RV32-NEXT: .LBB4_4: # %else2 ; RV32-NEXT: .LBB4_4: # %else2
; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_v2i16_align1: ; RV64-LABEL: mgather_v2i16_align1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15 ; RV64-NEXT: addi a0, sp, 15
; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB4_2 ; RV64-NEXT: beqz a1, .LBB4_2
Show All 14 Lines
; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: lb a1, 1(a0) ; RV64-NEXT: lb a1, 1(a0)
; RV64-NEXT: lbu a0, 0(a0) ; RV64-NEXT: lbu a0, 0(a0)
; RV64-NEXT: slli a1, a1, 8 ; RV64-NEXT: slli a1, a1, 8
; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vsetvli zero, zero, e16, mf4, tu, mu
; RV64-NEXT: vslideup.vi v9, v8, 1 ; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: .LBB4_4: # %else2 ; RV64-NEXT: .LBB4_4: # %else2
; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 1, <2 x i1> %m, <2 x i16> %passthru) %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 1, <2 x i1> %m, <2 x i16> %passthru)
ret <2 x i16> %v ret <2 x i16> %v
} }
declare <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*>, i32, <2 x i1>, <2 x i64>) declare <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*>, i32, <2 x i1>, <2 x i64>)
define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64> %passthru) { define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64> %passthru) {
; RV32-LABEL: mgather_v2i64_align4: ; RV32-LABEL: mgather_v2i64_align4:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15 ; RV32-NEXT: addi a0, sp, 15
; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: beqz a1, .LBB5_2 ; RV32-NEXT: beqz a1, .LBB5_2
; RV32-NEXT: # %bb.1: # %cond.load ; RV32-NEXT: # %bb.1: # %cond.load
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: lw a2, 4(a1) ; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1) ; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: vslide1up.vx v11, v10, a2 ; RV32-NEXT: vslide1up.vx v11, v10, a2
; RV32-NEXT: vslide1up.vx v12, v11, a1 ; RV32-NEXT: vslide1up.vx v12, v11, a1
; RV32-NEXT: vsetivli zero, 1, e64, m1, tu, mu ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV32-NEXT: vslideup.vi v9, v12, 0 ; RV32-NEXT: vslideup.vi v9, v12, 0
; RV32-NEXT: .LBB5_2: # %else ; RV32-NEXT: .LBB5_2: # %else
; RV32-NEXT: andi a0, a0, 2 ; RV32-NEXT: andi a0, a0, 2
; RV32-NEXT: beqz a0, .LBB5_4 ; RV32-NEXT: beqz a0, .LBB5_4
; RV32-NEXT: # %bb.3: # %cond.load1 ; RV32-NEXT: # %bb.3: # %cond.load1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: lw a1, 4(a0) ; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a0, 0(a0) ; RV32-NEXT: lw a0, 0(a0)
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32-NEXT: vslide1up.vx v8, v10, a1 ; RV32-NEXT: vslide1up.vx v8, v10, a1
; RV32-NEXT: vslide1up.vx v10, v8, a0 ; RV32-NEXT: vslide1up.vx v10, v8, a0
; RV32-NEXT: vsetivli zero, 2, e64, m1, tu, mu ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV32-NEXT: vslideup.vi v9, v10, 1 ; RV32-NEXT: vslideup.vi v9, v10, 1
; RV32-NEXT: .LBB5_4: # %else2 ; RV32-NEXT: .LBB5_4: # %else2
; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_v2i64_align4: ; RV64-LABEL: mgather_v2i64_align4:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15 ; RV64-NEXT: addi a0, sp, 15
; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB5_2 ; RV64-NEXT: beqz a1, .LBB5_2
Show All 13 Lines
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: lwu a1, 4(a0) ; RV64-NEXT: lwu a1, 4(a0)
; RV64-NEXT: lwu a0, 0(a0) ; RV64-NEXT: lwu a0, 0(a0)
; RV64-NEXT: slli a1, a1, 32 ; RV64-NEXT: slli a1, a1, 32
; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: vmv.s.x v8, a0 ; RV64-NEXT: vmv.s.x v8, a0
; RV64-NEXT: vsetivli zero, 2, e64, m1, tu, mu ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-NEXT: vslideup.vi v9, v8, 1 ; RV64-NEXT: vslideup.vi v9, v8, 1
; RV64-NEXT: .LBB5_4: # %else2 ; RV64-NEXT: .LBB5_4: # %else2
; RV64-NEXT: vmv1r.v v8, v9 ; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> %ptrs, i32 4, <2 x i1> %m, <2 x i64> %passthru) %v = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> %ptrs, i32 4, <2 x i1> %m, <2 x i64> %passthru)
ret <2 x i64> %v ret <2 x i64> %v
} }
declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>) declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>)
define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m) { define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m) {
; RV32-LABEL: mscatter_v4i16_align1: ; RV32-LABEL: mscatter_v4i16_align1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15 ; RV32-NEXT: addi a0, sp, 15
; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB6_5 ; RV32-NEXT: bnez a1, .LBB6_5
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v12, 0 ; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v12, v9, 0 ; RV64-NEXT: vslideup.vi v12, v9, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v9, v12, 0 ; RV64-NEXT: vmsne.vi v9, v12, 0
; RV64-NEXT: addi a0, sp, 15 ; RV64-NEXT: addi a0, sp, 15
; RV64-NEXT: vsm.v v9, (a0) ; RV64-NEXT: vsm.v v9, (a0)
; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB6_5 ; RV64-NEXT: bnez a1, .LBB6_5
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v11, v10, 0 ; RV32-NEXT: vslideup.vi v11, v10, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v10, v11, 0 ; RV32-NEXT: vmsne.vi v10, v11, 0
; RV32-NEXT: addi a0, sp, 15 ; RV32-NEXT: addi a0, sp, 15
; RV32-NEXT: vsm.v v10, (a0) ; RV32-NEXT: vsm.v v10, (a0)
; RV32-NEXT: lbu a0, 15(sp) ; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1 ; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB7_3 ; RV32-NEXT: bnez a1, .LBB7_3
Show All 28 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v11, v10, 0 ; RV64-NEXT: vslideup.vi v11, v10, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v10, v11, 0 ; RV64-NEXT: vmsne.vi v10, v11, 0
; RV64-NEXT: addi a0, sp, 15 ; RV64-NEXT: addi a0, sp, 15
; RV64-NEXT: vsm.v v10, (a0) ; RV64-NEXT: vsm.v v10, (a0)
; RV64-NEXT: lbu a0, 15(sp) ; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1 ; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB7_3 ; RV64-NEXT: bnez a1, .LBB7_3
Show All 37 Lines
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmseq.vi v0, v8, 0 ; RV32-NEXT: vmseq.vi v0, v8, 0
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV32-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-NEXT: vslideup.vi v9, v8, 0 ; RV32-NEXT: vslideup.vi v9, v8, 0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v8, v9, 0 ; RV32-NEXT: vmsne.vi v8, v9, 0
; RV32-NEXT: addi a2, sp, 15 ; RV32-NEXT: addi a2, sp, 15
; RV32-NEXT: vsm.v v8, (a2) ; RV32-NEXT: vsm.v v8, (a2)
; RV32-NEXT: lbu a2, 15(sp) ; RV32-NEXT: lbu a2, 15(sp)
; RV32-NEXT: andi a3, a2, 1 ; RV32-NEXT: andi a3, a2, 1
; RV32-NEXT: beqz a3, .LBB8_2 ; RV32-NEXT: beqz a3, .LBB8_2
Show All 25 Lines
; RV32-NEXT: lbu a0, 6(a0) ; RV32-NEXT: lbu a0, 6(a0)
; RV32-NEXT: slli a2, a2, 8 ; RV32-NEXT: slli a2, a2, 8
; RV32-NEXT: or a2, a2, a3 ; RV32-NEXT: or a2, a2, a3
; RV32-NEXT: slli a3, a4, 8 ; RV32-NEXT: slli a3, a4, 8
; RV32-NEXT: or a0, a3, a0 ; RV32-NEXT: or a0, a3, a0
; RV32-NEXT: slli a0, a0, 16 ; RV32-NEXT: slli a0, a0, 16
; RV32-NEXT: or a0, a0, a2 ; RV32-NEXT: or a0, a0, a2
; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV32-NEXT: vslideup.vi v8, v9, 1 ; RV32-NEXT: vslideup.vi v8, v9, 1
; RV32-NEXT: .LBB8_4: # %else2 ; RV32-NEXT: .LBB8_4: # %else2
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: masked_load_v2i32_align1: ; RV64-LABEL: masked_load_v2i32_align1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmseq.vi v0, v8, 0 ; RV64-NEXT: vmseq.vi v0, v8, 0
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; RV64-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-NEXT: vslideup.vi v9, v8, 0 ; RV64-NEXT: vslideup.vi v9, v8, 0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v8, v9, 0 ; RV64-NEXT: vmsne.vi v8, v9, 0
; RV64-NEXT: addi a2, sp, 15 ; RV64-NEXT: addi a2, sp, 15
; RV64-NEXT: vsm.v v8, (a2) ; RV64-NEXT: vsm.v v8, (a2)
; RV64-NEXT: lbu a2, 15(sp) ; RV64-NEXT: lbu a2, 15(sp)
; RV64-NEXT: andi a3, a2, 1 ; RV64-NEXT: andi a3, a2, 1
; RV64-NEXT: beqz a3, .LBB8_2 ; RV64-NEXT: beqz a3, .LBB8_2
Show All 25 Lines
; RV64-NEXT: lbu a0, 6(a0) ; RV64-NEXT: lbu a0, 6(a0)
; RV64-NEXT: slli a2, a2, 8 ; RV64-NEXT: slli a2, a2, 8
; RV64-NEXT: or a2, a2, a3 ; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: slli a3, a4, 8 ; RV64-NEXT: slli a3, a4, 8
; RV64-NEXT: or a0, a3, a0 ; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: slli a0, a0, 16 ; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: or a0, a0, a2 ; RV64-NEXT: or a0, a0, a2
; RV64-NEXT: vmv.s.x v9, a0 ; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
; RV64-NEXT: vslideup.vi v8, v9, 1 ; RV64-NEXT: vslideup.vi v8, v9, 1
; RV64-NEXT: .LBB8_4: # %else2 ; RV64-NEXT: .LBB8_4: # %else2
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64-NEXT: vse32.v v8, (a1) ; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%mask = icmp eq <2 x i32> %m, zeroinitializer %mask = icmp eq <2 x i32> %m, zeroinitializer
%load = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %a, i32 1, <2 x i1> %mask, <2 x i32> undef) %load = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %a, i32 1, <2 x i1> %mask, <2 x i32> undef)
store <2 x i32> %load, <2 x i32>* %res_ptr store <2 x i32> %load, <2 x i32>* %res_ptr
ret void ret void
} }
declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>) declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> %m) nounwind { define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32> %m) nounwind {
; CHECK-LABEL: masked_store_v2i32_align2: ; CHECK-LABEL: masked_store_v2i32_align2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vmseq.vi v0, v9, 0 ; CHECK-NEXT: vmseq.vi v0, v9, 0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v9, 0 ; CHECK-NEXT: vslideup.vi v10, v9, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v9, v10, 0 ; CHECK-NEXT: vmsne.vi v9, v10, 0
; CHECK-NEXT: addi a1, sp, 15 ; CHECK-NEXT: addi a1, sp, 15
; CHECK-NEXT: vsm.v v9, (a1) ; CHECK-NEXT: vsm.v v9, (a1)
; CHECK-NEXT: lbu a1, 15(sp) ; CHECK-NEXT: lbu a1, 15(sp)
; CHECK-NEXT: andi a2, a1, 1 ; CHECK-NEXT: andi a2, a1, 1
; CHECK-NEXT: bnez a2, .LBB9_3 ; CHECK-NEXT: bnez a2, .LBB9_3
Show All 27 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Show First 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB13_4: ; RV64-NEXT: .LBB13_4:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v10 ; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: li a0, 32 ; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; RV64-NEXT: vslideup.vi v8, v12, 16 ; RV64-NEXT: vslideup.vi v8, v12, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs %ptrs = getelementptr inbounds i8, i8* %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.vp.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x i8> @llvm.vp.gather.v32i8.v32p0i8(<32 x i8*> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x i8> %v ret <32 x i8> %v
} }
declare <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*>, <2 x i1>, i32) declare <2 x i16> @llvm.vp.gather.v2i16.v2p0i16(<2 x i16*>, <2 x i1>, i32)
▲ Show 20 Lines • Show All 2,345 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i32> %v ret <vscale x 8 x i32> %v
} }
define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv1i8_nxv4i8_0: ; CHECK-LABEL: insert_nxv1i8_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0) %v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv1i8_nxv4i8_3: ; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3) %v = call <vscale x 4 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
ret <vscale x 4 x i8> %v ret <vscale x 4 x i8> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv8i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_0: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 0 ; CHECK-NEXT: vslideup.vi v8, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0) %v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_1: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1) %v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) { define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
; CHECK-LABEL: insert_nxv16i32_nxv1i32_6: ; CHECK-LABEL: insert_nxv16i32_nxv1i32_6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v11, v16, 0 ; CHECK-NEXT: vslideup.vi v11, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6) %v = call <vscale x 16 x i32> @llvm.experimental.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6)
ret <vscale x 16 x i32> %v ret <vscale x 16 x i32> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_0: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 0 ; CHECK-NEXT: vslideup.vi v8, v10, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_1: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_2: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_3: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_7: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 3 ; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) { define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
; CHECK-LABEL: insert_nxv16i8_nxv1i8_15: ; CHECK-LABEL: insert_nxv16i8_nxv1i8_15:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 3 ; CHECK-NEXT: slli a1, a0, 3
; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: sub a0, a1, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v9, v10, a0 ; CHECK-NEXT: vslideup.vx v9, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15) %v = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_0: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 0 ; CHECK-NEXT: vslideup.vi v8, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0) %v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_2: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2) %v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_nxv2f16_26: ; CHECK-LABEL: insert_nxv32f16_nxv2f16_26:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v14, v16, a0 ; CHECK-NEXT: vslideup.vx v14, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26) %v = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) { define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {
; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0: ; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:
Show All 19 Lines; CHECK-NEXT: ret
ret <vscale x 32 x half> %v ret <vscale x 32 x half> %v
} }
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) { define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv32i1_nxv8i1_0: ; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v0, v8, 0 ; CHECK-NEXT: vslideup.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0) %vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0)
ret <vscale x 32 x i1> %vec ret <vscale x 32 x i1> %vec
} }
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) { define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
; CHECK-LABEL: insert_nxv32i1_nxv8i1_8: ; CHECK-LABEL: insert_nxv32i1_nxv8i1_8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v0, v8, a0 ; CHECK-NEXT: vslideup.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8) %vec = call <vscale x 32 x i1> @llvm.experimental.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8)
ret <vscale x 32 x i1> %vec ret <vscale x 32 x i1> %vec
} }
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) { define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
; CHECK-LABEL: insert_nxv4i1_nxv1i1_0: ; CHECK-LABEL: insert_nxv4i1_nxv1i1_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 0 ; CHECK-NEXT: vslideup.vi v9, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0) %vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)
ret <vscale x 4 x i1> %vec ret <vscale x 4 x i1> %vec
} }
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) { define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
; CHECK-LABEL: insert_nxv4i1_nxv1i1_2: ; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vslideup.vx v9, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2) %vec = call <vscale x 4 x i1> @llvm.experimental.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
ret <vscale x 4 x i1> %vec ret <vscale x 4 x i1> %vec
} }
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

Show All 11 Lines; CHECK-NEXT: ret
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 %idx) { define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 %idx) { define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 %idx) { define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 %idx) { define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 %idx) { define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 %idx) { define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv32f16_idx: ; CHECK-LABEL: insertelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_0: ; CHECK-LABEL: insertelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK-LABEL: insertelt_nxv1f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 %idx) { define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1f32_idx: ; CHECK-LABEL: insertelt_nxv1f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_0: ; CHECK-LABEL: insertelt_nxv2f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK-LABEL: insertelt_nxv2f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 %idx) { define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2f32_idx: ; CHECK-LABEL: insertelt_nxv2f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_0: ; CHECK-LABEL: insertelt_nxv4f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK-LABEL: insertelt_nxv4f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 %idx) { define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4f32_idx: ; CHECK-LABEL: insertelt_nxv4f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_0: ; CHECK-LABEL: insertelt_nxv8f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK-LABEL: insertelt_nxv8f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 %idx) { define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8f32_idx: ; CHECK-LABEL: insertelt_nxv8f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_0: ; CHECK-LABEL: insertelt_nxv16f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_imm: ; CHECK-LABEL: insertelt_nxv16f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 3
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 %idx) { define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv16f32_idx: ; CHECK-LABEL: insertelt_nxv16f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_0: ; CHECK-LABEL: insertelt_nxv1f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK-LABEL: insertelt_nxv1f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 %idx) { define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1f64_idx: ; CHECK-LABEL: insertelt_nxv1f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_0: ; CHECK-LABEL: insertelt_nxv2f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK-LABEL: insertelt_nxv2f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 %idx) { define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2f64_idx: ; CHECK-LABEL: insertelt_nxv2f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_0: ; CHECK-LABEL: insertelt_nxv4f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK-LABEL: insertelt_nxv4f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 %idx) { define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4f64_idx: ; CHECK-LABEL: insertelt_nxv4f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_0: ; CHECK-LABEL: insertelt_nxv8f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_imm: ; CHECK-LABEL: insertelt_nxv8f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 3
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 %idx) { define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8f64_idx: ; CHECK-LABEL: insertelt_nxv8f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

Show All 11 Lines; CHECK-NEXT: ret
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 signext %idx) { define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 signext %idx) { define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 signext %idx) { define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 signext %idx) { define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 signext %idx) { define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 signext %idx) { define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32f16_idx: ; CHECK-LABEL: insertelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_0: ; CHECK-LABEL: insertelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK-LABEL: insertelt_nxv1f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 signext %idx) { define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1f32_idx: ; CHECK-LABEL: insertelt_nxv1f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_0: ; CHECK-LABEL: insertelt_nxv2f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK-LABEL: insertelt_nxv2f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 signext %idx) { define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2f32_idx: ; CHECK-LABEL: insertelt_nxv2f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_0: ; CHECK-LABEL: insertelt_nxv4f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK-LABEL: insertelt_nxv4f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 3
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 signext %idx) { define <vscale x 4 x float> @insertelt_nxv4f32_idx(<vscale x 4 x float> %v, float %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4f32_idx: ; CHECK-LABEL: insertelt_nxv4f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_0: ; CHECK-LABEL: insertelt_nxv8f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK-LABEL: insertelt_nxv8f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 3
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 signext %idx) { define <vscale x 8 x float> @insertelt_nxv8f32_idx(<vscale x 8 x float> %v, float %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8f32_idx: ; CHECK-LABEL: insertelt_nxv8f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_0: ; CHECK-LABEL: insertelt_nxv16f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_imm: ; CHECK-LABEL: insertelt_nxv16f32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 3
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 signext %idx) { define <vscale x 16 x float> @insertelt_nxv16f32_idx(<vscale x 16 x float> %v, float %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16f32_idx: ; CHECK-LABEL: insertelt_nxv16f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_0: ; CHECK-LABEL: insertelt_nxv1f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK-LABEL: insertelt_nxv1f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 signext %idx) { define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1f64_idx: ; CHECK-LABEL: insertelt_nxv1f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_0: ; CHECK-LABEL: insertelt_nxv2f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK-LABEL: insertelt_nxv2f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 3
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 signext %idx) { define <vscale x 2 x double> @insertelt_nxv2f64_idx(<vscale x 2 x double> %v, double %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2f64_idx: ; CHECK-LABEL: insertelt_nxv2f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vfmv.s.f v10, fa0 ; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_0: ; CHECK-LABEL: insertelt_nxv4f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK-LABEL: insertelt_nxv4f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 3
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 signext %idx) { define <vscale x 4 x double> @insertelt_nxv4f64_idx(<vscale x 4 x double> %v, double %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4f64_idx: ; CHECK-LABEL: insertelt_nxv4f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_0: ; CHECK-LABEL: insertelt_nxv8f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_imm: ; CHECK-LABEL: insertelt_nxv8f64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 3
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 signext %idx) { define <vscale x 8 x double> @insertelt_nxv8f64_idx(<vscale x 8 x double> %v, double %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8f64_idx: ; CHECK-LABEL: insertelt_nxv8f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 8 x double> %v, double %elt, i32 %idx
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }

llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i1> @insertelt_nxv1i1(<vscale x 1 x i1> %x, i1 %elt) { define <vscale x 1 x i1> @insertelt_nxv1i1(<vscale x 1 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv1i1: ; CHECK-LABEL: insertelt_nxv1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 2
ret <vscale x 1 x i1> %y ret <vscale x 1 x i1> %y
} }
define <vscale x 1 x i1> @insertelt_idx_nxv1i1(<vscale x 1 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 1 x i1> @insertelt_idx_nxv1i1(<vscale x 1 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv1i1: ; CHECK-LABEL: insertelt_idx_nxv1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 1 x i1> %y ret <vscale x 1 x i1> %y
} }
define <vscale x 2 x i1> @insertelt_nxv2i1(<vscale x 2 x i1> %x, i1 %elt) { define <vscale x 2 x i1> @insertelt_nxv2i1(<vscale x 2 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv2i1: ; CHECK-LABEL: insertelt_nxv2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 2
ret <vscale x 2 x i1> %y ret <vscale x 2 x i1> %y
} }
define <vscale x 2 x i1> @insertelt_idx_nxv2i1(<vscale x 2 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 2 x i1> @insertelt_idx_nxv2i1(<vscale x 2 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv2i1: ; CHECK-LABEL: insertelt_idx_nxv2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 2 x i1> %y ret <vscale x 2 x i1> %y
} }
define <vscale x 4 x i1> @insertelt_nxv4i1(<vscale x 4 x i1> %x, i1 %elt) { define <vscale x 4 x i1> @insertelt_nxv4i1(<vscale x 4 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv4i1: ; CHECK-LABEL: insertelt_nxv4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 2
ret <vscale x 4 x i1> %y ret <vscale x 4 x i1> %y
} }
define <vscale x 4 x i1> @insertelt_idx_nxv4i1(<vscale x 4 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 4 x i1> @insertelt_idx_nxv4i1(<vscale x 4 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv4i1: ; CHECK-LABEL: insertelt_idx_nxv4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 4 x i1> %y ret <vscale x 4 x i1> %y
} }
define <vscale x 8 x i1> @insertelt_nxv8i1(<vscale x 8 x i1> %x, i1 %elt) { define <vscale x 8 x i1> @insertelt_nxv8i1(<vscale x 8 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv8i1: ; CHECK-LABEL: insertelt_nxv8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v9, v8, 2 ; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 2
ret <vscale x 8 x i1> %y ret <vscale x 8 x i1> %y
} }
define <vscale x 8 x i1> @insertelt_idx_nxv8i1(<vscale x 8 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 8 x i1> @insertelt_idx_nxv8i1(<vscale x 8 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv8i1: ; CHECK-LABEL: insertelt_idx_nxv8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a1 ; CHECK-NEXT: vslideup.vx v9, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vand.vi v8, v9, 1 ; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 8 x i1> %y ret <vscale x 8 x i1> %y
} }
define <vscale x 16 x i1> @insertelt_nxv16i1(<vscale x 16 x i1> %x, i1 %elt) { define <vscale x 16 x i1> @insertelt_nxv16i1(<vscale x 16 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv16i1: ; CHECK-LABEL: insertelt_nxv16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v10, v8, 2 ; CHECK-NEXT: vslideup.vi v10, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vand.vi v8, v10, 1 ; CHECK-NEXT: vand.vi v8, v10, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 2
ret <vscale x 16 x i1> %y ret <vscale x 16 x i1> %y
} }
define <vscale x 16 x i1> @insertelt_idx_nxv16i1(<vscale x 16 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 16 x i1> @insertelt_idx_nxv16i1(<vscale x 16 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv16i1: ; CHECK-LABEL: insertelt_idx_nxv16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 ; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v10, v8, a1 ; CHECK-NEXT: vslideup.vx v10, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vand.vi v8, v10, 1 ; CHECK-NEXT: vand.vi v8, v10, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 16 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 16 x i1> %y ret <vscale x 16 x i1> %y
} }
define <vscale x 32 x i1> @insertelt_nxv32i1(<vscale x 32 x i1> %x, i1 %elt) { define <vscale x 32 x i1> @insertelt_nxv32i1(<vscale x 32 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv32i1: ; CHECK-LABEL: insertelt_nxv32i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v12, v8, 2 ; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vand.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v12, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 2
ret <vscale x 32 x i1> %y ret <vscale x 32 x i1> %y
} }
define <vscale x 32 x i1> @insertelt_idx_nxv32i1(<vscale x 32 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 32 x i1> @insertelt_idx_nxv32i1(<vscale x 32 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv32i1: ; CHECK-LABEL: insertelt_idx_nxv32i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v12, v8, a1 ; CHECK-NEXT: vslideup.vx v12, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vand.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v12, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 32 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 32 x i1> %y ret <vscale x 32 x i1> %y
} }
define <vscale x 64 x i1> @insertelt_nxv64i1(<vscale x 64 x i1> %x, i1 %elt) { define <vscale x 64 x i1> @insertelt_nxv64i1(<vscale x 64 x i1> %x, i1 %elt) {
; CHECK-LABEL: insertelt_nxv64i1: ; CHECK-LABEL: insertelt_nxv64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0 ; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vsetivli zero, 3, e8, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 3, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vi v16, v8, 2 ; CHECK-NEXT: vslideup.vi v16, v8, 2
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vand.vi v8, v16, 1 ; CHECK-NEXT: vand.vi v8, v16, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 64 x i1> %x, i1 %elt, i64 2 %y = insertelement <vscale x 64 x i1> %x, i1 %elt, i64 2
ret <vscale x 64 x i1> %y ret <vscale x 64 x i1> %y
} }
define <vscale x 64 x i1> @insertelt_idx_nxv64i1(<vscale x 64 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 64 x i1> @insertelt_idx_nxv64i1(<vscale x 64 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv64i1: ; CHECK-LABEL: insertelt_idx_nxv64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0 ; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vx v16, v8, a1 ; CHECK-NEXT: vslideup.vx v16, v8, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vand.vi v8, v16, 1 ; CHECK-NEXT: vand.vi v8, v16, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 64 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 64 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 64 x i1> %y ret <vscale x 64 x i1> %y
} }

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

Show All 11 Lines; CHECK-NEXT: ret
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK-LABEL: insertelt_nxv1i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK-LABEL: insertelt_nxv2i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK-LABEL: insertelt_nxv4i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK-LABEL: insertelt_nxv8i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK-LABEL: insertelt_nxv16i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16i8_idx: ; CHECK-LABEL: insertelt_nxv16i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_0: ; CHECK-LABEL: insertelt_nxv32i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK-LABEL: insertelt_nxv32i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32i8_idx: ; CHECK-LABEL: insertelt_nxv32i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_0: ; CHECK-LABEL: insertelt_nxv64i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_imm: ; CHECK-LABEL: insertelt_nxv64i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv64i8_idx: ; CHECK-LABEL: insertelt_nxv64i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_0: ; CHECK-LABEL: insertelt_nxv1i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK-LABEL: insertelt_nxv1i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK-LABEL: insertelt_nxv2i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK-LABEL: insertelt_nxv4i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK-LABEL: insertelt_nxv8i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i16_idx: ; CHECK-LABEL: insertelt_nxv8i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_0: ; CHECK-LABEL: insertelt_nxv16i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK-LABEL: insertelt_nxv16i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16i16_idx: ; CHECK-LABEL: insertelt_nxv16i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_0: ; CHECK-LABEL: insertelt_nxv32i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_imm: ; CHECK-LABEL: insertelt_nxv32i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32i16_idx: ; CHECK-LABEL: insertelt_nxv32i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv1i32_0: ; CHECK-LABEL: insertelt_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK-LABEL: insertelt_nxv1i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK-LABEL: insertelt_nxv2i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK-LABEL: insertelt_nxv4i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4i32_idx: ; CHECK-LABEL: insertelt_nxv4i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv8i32_0: ; CHECK-LABEL: insertelt_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK-LABEL: insertelt_nxv8i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8i32_idx: ; CHECK-LABEL: insertelt_nxv8i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv16i32_0: ; CHECK-LABEL: insertelt_nxv16i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv16i32_imm: ; CHECK-LABEL: insertelt_nxv16i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv16i32_idx: ; CHECK-LABEL: insertelt_nxv16i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_0: ; CHECK-LABEL: insertelt_nxv1i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vslide1up.vx v10, v9, a1 ; CHECK-NEXT: vslide1up.vx v10, v9, a1
; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 0 ; CHECK-NEXT: vslideup.vi v8, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_imm: ; CHECK-LABEL: insertelt_nxv1i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vslide1up.vx v10, v9, a1 ; CHECK-NEXT: vslide1up.vx v10, v9, a1
; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1i64_idx: ; CHECK-LABEL: insertelt_nxv1i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vslide1up.vx v10, v9, a1 ; CHECK-NEXT: vslide1up.vx v10, v9, a1
; CHECK-NEXT: vslide1up.vx v9, v10, a0 ; CHECK-NEXT: vslide1up.vx v9, v10, a0
; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a2 ; CHECK-NEXT: vslideup.vx v8, v9, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_0: ; CHECK-LABEL: insertelt_nxv2i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vslide1up.vx v12, v10, a1 ; CHECK-NEXT: vslide1up.vx v12, v10, a1
; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 0 ; CHECK-NEXT: vslideup.vi v8, v10, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_imm: ; CHECK-LABEL: insertelt_nxv2i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vslide1up.vx v12, v10, a1 ; CHECK-NEXT: vslide1up.vx v12, v10, a1
; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i64_idx: ; CHECK-LABEL: insertelt_nxv2i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, mu
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vslide1up.vx v12, v10, a1 ; CHECK-NEXT: vslide1up.vx v12, v10, a1
; CHECK-NEXT: vslide1up.vx v10, v12, a0 ; CHECK-NEXT: vslide1up.vx v10, v12, a0
; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a2 ; CHECK-NEXT: vslideup.vx v8, v10, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_0: ; CHECK-LABEL: insertelt_nxv4i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vslide1up.vx v16, v12, a1 ; CHECK-NEXT: vslide1up.vx v16, v12, a1
; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 0 ; CHECK-NEXT: vslideup.vi v8, v12, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_imm: ; CHECK-LABEL: insertelt_nxv4i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vslide1up.vx v16, v12, a1 ; CHECK-NEXT: vslide1up.vx v16, v12, a1
; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4i64_idx: ; CHECK-LABEL: insertelt_nxv4i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m4, ta, mu
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vslide1up.vx v16, v12, a1 ; CHECK-NEXT: vslide1up.vx v16, v12, a1
; CHECK-NEXT: vslide1up.vx v12, v16, a0 ; CHECK-NEXT: vslide1up.vx v12, v16, a0
; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a2 ; CHECK-NEXT: vslideup.vx v8, v12, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_0: ; CHECK-LABEL: insertelt_nxv8i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vslide1up.vx v24, v16, a1 ; CHECK-NEXT: vslide1up.vx v24, v16, a1
; CHECK-NEXT: vslide1up.vx v16, v24, a0 ; CHECK-NEXT: vslide1up.vx v16, v24, a0
; CHECK-NEXT: vsetivli zero, 1, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 0 ; CHECK-NEXT: vslideup.vi v8, v16, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_imm: ; CHECK-LABEL: insertelt_nxv8i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vslide1up.vx v24, v16, a1 ; CHECK-NEXT: vslide1up.vx v24, v16, a1
; CHECK-NEXT: vslide1up.vx v16, v24, a0 ; CHECK-NEXT: vslide1up.vx v16, v24, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8i64_idx: ; CHECK-LABEL: insertelt_nxv8i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, m8, ta, mu
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vslide1up.vx v24, v16, a1 ; CHECK-NEXT: vslide1up.vx v24, v16, a1
; CHECK-NEXT: vslide1up.vx v16, v24, a0 ; CHECK-NEXT: vslide1up.vx v16, v24, a0
; CHECK-NEXT: addi a0, a2, 1 ; CHECK-NEXT: addi a0, a2, 1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a2 ; CHECK-NEXT: vslideup.vx v8, v16, a2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
; Extra tests to check lowering of constant values ; Extra tests to check lowering of constant values
define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_0_c10: ; CHECK-LABEL: insertelt_nxv2i64_0_c10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 10 ; CHECK-NEXT: li a0, 10
; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_imm_c10: ; CHECK-LABEL: insertelt_nxv2i64_imm_c10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 10 ; CHECK-NEXT: li a0, 10
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 3 %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 3
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_idx_c10(<vscale x 2 x i64> %v, i32 %idx) { define <vscale x 2 x i64> @insertelt_nxv2i64_idx_c10(<vscale x 2 x i64> %v, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i64_idx_c10: ; CHECK-LABEL: insertelt_nxv2i64_idx_c10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 10 ; CHECK-NEXT: li a1, 10
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a1 ; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_0_cn1: ; CHECK-LABEL: insertelt_nxv2i64_0_cn1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_imm_cn1: ; CHECK-LABEL: insertelt_nxv2i64_imm_cn1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 3 %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 3
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_idx_cn1(<vscale x 2 x i64> %v, i32 %idx) { define <vscale x 2 x i64> @insertelt_nxv2i64_idx_cn1(<vscale x 2 x i64> %v, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i64_idx_cn1: ; CHECK-LABEL: insertelt_nxv2i64_idx_cn1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a1 ; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

Show All 11 Lines; CHECK-NEXT: ret
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK-LABEL: insertelt_nxv1i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK-LABEL: insertelt_nxv2i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK-LABEL: insertelt_nxv4i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK-LABEL: insertelt_nxv8i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK-LABEL: insertelt_nxv16i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 3
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 16 x i8> @insertelt_nxv16i8_idx(<vscale x 16 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16i8_idx: ; CHECK-LABEL: insertelt_nxv16i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_0: ; CHECK-LABEL: insertelt_nxv32i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK-LABEL: insertelt_nxv32i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 3
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 32 x i8> @insertelt_nxv32i8_idx(<vscale x 32 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32i8_idx: ; CHECK-LABEL: insertelt_nxv32i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_0: ; CHECK-LABEL: insertelt_nxv64i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_imm: ; CHECK-LABEL: insertelt_nxv64i8_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e8, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 3
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 64 x i8> @insertelt_nxv64i8_idx(<vscale x 64 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv64i8_idx: ; CHECK-LABEL: insertelt_nxv64i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_0: ; CHECK-LABEL: insertelt_nxv1i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK-LABEL: insertelt_nxv1i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK-LABEL: insertelt_nxv2i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK-LABEL: insertelt_nxv4i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK-LABEL: insertelt_nxv8i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 3
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 8 x i16> @insertelt_nxv8i16_idx(<vscale x 8 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i16_idx: ; CHECK-LABEL: insertelt_nxv8i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_0: ; CHECK-LABEL: insertelt_nxv16i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK-LABEL: insertelt_nxv16i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 3
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 16 x i16> @insertelt_nxv16i16_idx(<vscale x 16 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16i16_idx: ; CHECK-LABEL: insertelt_nxv16i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_0: ; CHECK-LABEL: insertelt_nxv32i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_imm: ; CHECK-LABEL: insertelt_nxv32i16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 3
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 32 x i16> @insertelt_nxv32i16_idx(<vscale x 32 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32i16_idx: ; CHECK-LABEL: insertelt_nxv32i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i32_0: ; CHECK-LABEL: insertelt_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK-LABEL: insertelt_nxv1i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 signext %idx) { define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK-LABEL: insertelt_nxv2i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 signext %idx) { define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK-LABEL: insertelt_nxv4i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 3
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %elt, i32 signext %idx) { define <vscale x 4 x i32> @insertelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i32_idx: ; CHECK-LABEL: insertelt_nxv4i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i32_0: ; CHECK-LABEL: insertelt_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK-LABEL: insertelt_nxv8i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 3
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %elt, i32 signext %idx) { define <vscale x 8 x i32> @insertelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i32_idx: ; CHECK-LABEL: insertelt_nxv8i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i32_0: ; CHECK-LABEL: insertelt_nxv16i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i32_imm: ; CHECK-LABEL: insertelt_nxv16i32_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 3
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %elt, i32 signext %idx) { define <vscale x 16 x i32> @insertelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16i32_idx: ; CHECK-LABEL: insertelt_nxv16i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_0: ; CHECK-LABEL: insertelt_nxv1i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_imm: ; CHECK-LABEL: insertelt_nxv1i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 3 ; CHECK-NEXT: vslideup.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 3
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 1 x i64> @insertelt_nxv1i64_idx(<vscale x 1 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1i64_idx: ; CHECK-LABEL: insertelt_nxv1i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, mu
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_0: ; CHECK-LABEL: insertelt_nxv2i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_imm: ; CHECK-LABEL: insertelt_nxv2i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 3 ; CHECK-NEXT: vslideup.vi v8, v10, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 3
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 2 x i64> @insertelt_nxv2i64_idx(<vscale x 2 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i64_idx: ; CHECK-LABEL: insertelt_nxv2i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, mu
; CHECK-NEXT: vmv.s.x v10, a0 ; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_0: ; CHECK-LABEL: insertelt_nxv4i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_imm: ; CHECK-LABEL: insertelt_nxv4i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 3 ; CHECK-NEXT: vslideup.vi v8, v12, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 3
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 4 x i64> @insertelt_nxv4i64_idx(<vscale x 4 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4i64_idx: ; CHECK-LABEL: insertelt_nxv4i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, mu
; CHECK-NEXT: vmv.s.x v12, a0 ; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_0: ; CHECK-LABEL: insertelt_nxv8i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_imm: ; CHECK-LABEL: insertelt_nxv8i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: vsetivli zero, 4, e64, m8, tu, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 3
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) { define <vscale x 8 x i64> @insertelt_nxv8i64_idx(<vscale x 8 x i64> %v, i64 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8i64_idx: ; CHECK-LABEL: insertelt_nxv8i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; CHECK-NEXT: vmv.s.x v16, a0 ; CHECK-NEXT: vmv.s.x v16, a0
; CHECK-NEXT: sext.w a0, a1 ; CHECK-NEXT: sext.w a0, a1
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

Show First 20 Lines • Show All 1,140 Lines • ▼ Show 20 Lines
declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
iXLen, iXLen,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen);
define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vx v9, v8, a0, v0.t ; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
iXLen %1, <vscale x 1 x i8> %1,
<vscale x 1 x i1> %2, iXLen %2,
iXLen %3, iXLen 3) <vscale x 1 x i1> %3,
iXLen %4, iXLen 3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8( declare <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll

Show First 20 Lines • Show All 2,515 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: fcvt.d.w ft0, zero ; RV32-NEXT: fcvt.d.w ft0, zero
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: vmfeq.vf v24, v16, ft0 ; RV32-NEXT: vmfeq.vf v24, v16, ft0
; RV32-NEXT: vmfeq.vf v0, v8, ft0 ; RV32-NEXT: vmfeq.vf v0, v8, ft0
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: srli a0, a0, 3 ; RV32-NEXT: srli a0, a0, 3
; RV32-NEXT: add a1, a0, a0 ; RV32-NEXT: add a1, a0, a0
; RV32-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; RV32-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; RV32-NEXT: vslideup.vx v0, v24, a0 ; RV32-NEXT: vslideup.vx v0, v24, a0
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fcmp_oeq_vf_nx16f64: ; RV64-LABEL: fcmp_oeq_vf_nx16f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.d.x ft0, zero ; RV64-NEXT: fmv.d.x ft0, zero
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV64-NEXT: vmfeq.vf v24, v16, ft0 ; RV64-NEXT: vmfeq.vf v24, v16, ft0
; RV64-NEXT: vmfeq.vf v0, v8, ft0 ; RV64-NEXT: vmfeq.vf v0, v8, ft0
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: srli a0, a0, 3 ; RV64-NEXT: srli a0, a0, 3
; RV64-NEXT: add a1, a0, a0 ; RV64-NEXT: add a1, a0, a0
; RV64-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; RV64-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; RV64-NEXT: vslideup.vx v0, v24, a0 ; RV64-NEXT: vslideup.vx v0, v24, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer %vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc ret <vscale x 16 x i1> %vc
} }
attributes #0 = { "no-nans-fp-math"="true" } attributes #0 = { "no-nans-fp-math"="true" }

llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll

Show First 20 Lines • Show All 3,195 Lines • ▼ Show 20 Lines
; CHECK-LABEL: icmp_eq_vi_nx16i64: ; CHECK-LABEL: icmp_eq_vi_nx16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; CHECK-NEXT: vmseq.vi v24, v16, 0 ; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v0, v24, a0 ; CHECK-NEXT: vslideup.vx v0, v24, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer %vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer
ret <vscale x 16 x i1> %vc ret <vscale x 16 x i1> %vc
} }

llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll

Show First 20 Lines • Show All 861 Lines • ▼ Show 20 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
iXLen, iXLen,
iXLen,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8> undef, <vscale x 1 x i8> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
iXLen %1, iXLen %1,
iXLen %2) iXLen %2,
iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
iXLen, iXLen,
iXLen,
iXLen); iXLen);
define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
iXLen %1, <vscale x 1 x i8> %1,
iXLen %2) iXLen %2,
iXLen %3,
iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, iXLen); declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, iXLen);
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwind {
; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64:
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

Show All 15 Lines
define <vscale x 1 x i8> @splice_nxv1i8_offset_negone(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { define <vscale x 1 x i8> @splice_nxv1i8_offset_negone(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv1i8_offset_negone: ; CHECK-LABEL: splice_nxv1i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -1) %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -1)
ret <vscale x 1 x i8> %res ret <vscale x 1 x i8> %res
} }
define <vscale x 1 x i8> @splice_nxv1i8_offset_min(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { define <vscale x 1 x i8> @splice_nxv1i8_offset_min(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv1i8_offset_min: ; CHECK-LABEL: splice_nxv1i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -2) %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -2)
ret <vscale x 1 x i8> %res ret <vscale x 1 x i8> %res
} }
define <vscale x 1 x i8> @splice_nxv1i8_offset_max(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 { define <vscale x 1 x i8> @splice_nxv1i8_offset_max(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv1i8_offset_max: ; CHECK-LABEL: splice_nxv1i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 1) %res = call <vscale x 1 x i8> @llvm.experimental.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 1)
ret <vscale x 1 x i8> %res ret <vscale x 1 x i8> %res
} }
declare <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32) declare <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32)
define <vscale x 2 x i8> @splice_nxv2i8_offset_zero(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { define <vscale x 2 x i8> @splice_nxv2i8_offset_zero(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv2i8_offset_zero: ; CHECK-LABEL: splice_nxv2i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 0) %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 0)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @splice_nxv2i8_offset_negone(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { define <vscale x 2 x i8> @splice_nxv2i8_offset_negone(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv2i8_offset_negone: ; CHECK-LABEL: splice_nxv2i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -1) %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -1)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @splice_nxv2i8_offset_min(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { define <vscale x 2 x i8> @splice_nxv2i8_offset_min(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv2i8_offset_min: ; CHECK-LABEL: splice_nxv2i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -4) %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -4)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 2 x i8> @splice_nxv2i8_offset_max(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 { define <vscale x 2 x i8> @splice_nxv2i8_offset_max(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv2i8_offset_max: ; CHECK-LABEL: splice_nxv2i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 3) %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 3)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
declare <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, i32) declare <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, i32)
define <vscale x 4 x i8> @splice_nxv4i8_offset_zero(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { define <vscale x 4 x i8> @splice_nxv4i8_offset_zero(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv4i8_offset_zero: ; CHECK-LABEL: splice_nxv4i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 0) %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 0)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @splice_nxv4i8_offset_negone(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { define <vscale x 4 x i8> @splice_nxv4i8_offset_negone(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv4i8_offset_negone: ; CHECK-LABEL: splice_nxv4i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -1) %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -1)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @splice_nxv4i8_offset_min(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { define <vscale x 4 x i8> @splice_nxv4i8_offset_min(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv4i8_offset_min: ; CHECK-LABEL: splice_nxv4i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: vslideup.vi v8, v9, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -8) %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -8)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
define <vscale x 4 x i8> @splice_nxv4i8_offset_max(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 { define <vscale x 4 x i8> @splice_nxv4i8_offset_max(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv4i8_offset_max: ; CHECK-LABEL: splice_nxv4i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 7) %res = call <vscale x 4 x i8> @llvm.experimental.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 7)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
declare <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i32) declare <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i32)
define <vscale x 8 x i8> @splice_nxv8i8_offset_zero(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { define <vscale x 8 x i8> @splice_nxv8i8_offset_zero(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv8i8_offset_zero: ; CHECK-LABEL: splice_nxv8i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 0) %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 0)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @splice_nxv8i8_offset_negone(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { define <vscale x 8 x i8> @splice_nxv8i8_offset_negone(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv8i8_offset_negone: ; CHECK-LABEL: splice_nxv8i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -1) %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -1)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @splice_nxv8i8_offset_min(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { define <vscale x 8 x i8> @splice_nxv8i8_offset_min(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv8i8_offset_min: ; CHECK-LABEL: splice_nxv8i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 16 ; CHECK-NEXT: vslideup.vi v8, v9, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -16) %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -16)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 8 x i8> @splice_nxv8i8_offset_max(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 { define <vscale x 8 x i8> @splice_nxv8i8_offset_max(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv8i8_offset_max: ; CHECK-LABEL: splice_nxv8i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e8, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 15) %res = call <vscale x 8 x i8> @llvm.experimental.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 15)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
declare <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32) declare <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
define <vscale x 16 x i8> @splice_nxv16i8_offset_zero(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { define <vscale x 16 x i8> @splice_nxv16i8_offset_zero(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv16i8_offset_zero: ; CHECK-LABEL: splice_nxv16i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0) %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0)
ret <vscale x 16 x i8> %res ret <vscale x 16 x i8> %res
} }
define <vscale x 16 x i8> @splice_nxv16i8_offset_negone(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { define <vscale x 16 x i8> @splice_nxv16i8_offset_negone(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv16i8_offset_negone: ; CHECK-LABEL: splice_nxv16i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -1) %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -1)
ret <vscale x 16 x i8> %res ret <vscale x 16 x i8> %res
} }
define <vscale x 16 x i8> @splice_nxv16i8_offset_min(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { define <vscale x 16 x i8> @splice_nxv16i8_offset_min(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv16i8_offset_min: ; CHECK-LABEL: splice_nxv16i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a1 ; CHECK-NEXT: vslideup.vx v8, v10, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -32) %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -32)
ret <vscale x 16 x i8> %res ret <vscale x 16 x i8> %res
} }
define <vscale x 16 x i8> @splice_nxv16i8_offset_max(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 { define <vscale x 16 x i8> @splice_nxv16i8_offset_max(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv16i8_offset_max: ; CHECK-LABEL: splice_nxv16i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: addi a0, a0, -31
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vslidedown.vi v8, v8, 31
; CHECK-NEXT: vsetvli a1, zero, e8, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 31) %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 31)
ret <vscale x 16 x i8> %res ret <vscale x 16 x i8> %res
} }
declare <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, i32) declare <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, i32)
define <vscale x 32 x i8> @splice_nxv32i8_offset_zero(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { define <vscale x 32 x i8> @splice_nxv32i8_offset_zero(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv32i8_offset_zero: ; CHECK-LABEL: splice_nxv32i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 0) %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 0)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
define <vscale x 32 x i8> @splice_nxv32i8_offset_negone(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { define <vscale x 32 x i8> @splice_nxv32i8_offset_negone(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv32i8_offset_negone: ; CHECK-LABEL: splice_nxv32i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -1) %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -1)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
define <vscale x 32 x i8> @splice_nxv32i8_offset_min(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { define <vscale x 32 x i8> @splice_nxv32i8_offset_min(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv32i8_offset_min: ; CHECK-LABEL: splice_nxv32i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: addi a0, a0, -64
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -64) %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -64)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
define <vscale x 32 x i8> @splice_nxv32i8_offset_max(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 { define <vscale x 32 x i8> @splice_nxv32i8_offset_max(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv32i8_offset_max: ; CHECK-LABEL: splice_nxv32i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: addi a0, a0, -63
; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 63) %res = call <vscale x 32 x i8> @llvm.experimental.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 63)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
declare <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, i32) declare <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, i32)
define <vscale x 64 x i8> @splice_nxv64i8_offset_zero(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { define <vscale x 64 x i8> @splice_nxv64i8_offset_zero(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv64i8_offset_zero: ; CHECK-LABEL: splice_nxv64i8_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 0) %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 0)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
define <vscale x 64 x i8> @splice_nxv64i8_offset_negone(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { define <vscale x 64 x i8> @splice_nxv64i8_offset_negone(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv64i8_offset_negone: ; CHECK-LABEL: splice_nxv64i8_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -1) %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -1)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
define <vscale x 64 x i8> @splice_nxv64i8_offset_min(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { define <vscale x 64 x i8> @splice_nxv64i8_offset_min(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv64i8_offset_min: ; CHECK-LABEL: splice_nxv64i8_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -128 ; CHECK-NEXT: addi a0, a0, -128
; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -128) %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -128)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
define <vscale x 64 x i8> @splice_nxv64i8_offset_max(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 { define <vscale x 64 x i8> @splice_nxv64i8_offset_max(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
; CHECK-LABEL: splice_nxv64i8_offset_max: ; CHECK-LABEL: splice_nxv64i8_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -127 ; CHECK-NEXT: addi a0, a0, -127
; CHECK-NEXT: li a1, 127 ; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 127) %res = call <vscale x 64 x i8> @llvm.experimental.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 127)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
declare <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, i32) declare <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, i32)
define <vscale x 1 x i16> @splice_nxv1i16_offset_zero(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { define <vscale x 1 x i16> @splice_nxv1i16_offset_zero(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv1i16_offset_zero: ; CHECK-LABEL: splice_nxv1i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 0) %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 0)
ret <vscale x 1 x i16> %res ret <vscale x 1 x i16> %res
} }
define <vscale x 1 x i16> @splice_nxv1i16_offset_negone(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { define <vscale x 1 x i16> @splice_nxv1i16_offset_negone(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv1i16_offset_negone: ; CHECK-LABEL: splice_nxv1i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -1) %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -1)
ret <vscale x 1 x i16> %res ret <vscale x 1 x i16> %res
} }
define <vscale x 1 x i16> @splice_nxv1i16_offset_min(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { define <vscale x 1 x i16> @splice_nxv1i16_offset_min(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv1i16_offset_min: ; CHECK-LABEL: splice_nxv1i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -2) %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -2)
ret <vscale x 1 x i16> %res ret <vscale x 1 x i16> %res
} }
define <vscale x 1 x i16> @splice_nxv1i16_offset_max(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 { define <vscale x 1 x i16> @splice_nxv1i16_offset_max(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv1i16_offset_max: ; CHECK-LABEL: splice_nxv1i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 1) %res = call <vscale x 1 x i16> @llvm.experimental.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 1)
ret <vscale x 1 x i16> %res ret <vscale x 1 x i16> %res
} }
declare <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, i32) declare <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, i32)
define <vscale x 2 x i16> @splice_nxv2i16_offset_zero(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { define <vscale x 2 x i16> @splice_nxv2i16_offset_zero(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv2i16_offset_zero: ; CHECK-LABEL: splice_nxv2i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 0) %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 0)
ret <vscale x 2 x i16> %res ret <vscale x 2 x i16> %res
} }
define <vscale x 2 x i16> @splice_nxv2i16_offset_negone(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { define <vscale x 2 x i16> @splice_nxv2i16_offset_negone(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv2i16_offset_negone: ; CHECK-LABEL: splice_nxv2i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -1) %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -1)
ret <vscale x 2 x i16> %res ret <vscale x 2 x i16> %res
} }
define <vscale x 2 x i16> @splice_nxv2i16_offset_min(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { define <vscale x 2 x i16> @splice_nxv2i16_offset_min(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv2i16_offset_min: ; CHECK-LABEL: splice_nxv2i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -4) %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -4)
ret <vscale x 2 x i16> %res ret <vscale x 2 x i16> %res
} }
define <vscale x 2 x i16> @splice_nxv2i16_offset_max(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 { define <vscale x 2 x i16> @splice_nxv2i16_offset_max(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv2i16_offset_max: ; CHECK-LABEL: splice_nxv2i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 3) %res = call <vscale x 2 x i16> @llvm.experimental.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 3)
ret <vscale x 2 x i16> %res ret <vscale x 2 x i16> %res
} }
declare <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, i32) declare <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, i32)
define <vscale x 4 x i16> @splice_nxv4i16_offset_zero(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { define <vscale x 4 x i16> @splice_nxv4i16_offset_zero(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv4i16_offset_zero: ; CHECK-LABEL: splice_nxv4i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 0) %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 0)
ret <vscale x 4 x i16> %res ret <vscale x 4 x i16> %res
} }
define <vscale x 4 x i16> @splice_nxv4i16_offset_negone(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { define <vscale x 4 x i16> @splice_nxv4i16_offset_negone(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv4i16_offset_negone: ; CHECK-LABEL: splice_nxv4i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -1) %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -1)
ret <vscale x 4 x i16> %res ret <vscale x 4 x i16> %res
} }
define <vscale x 4 x i16> @splice_nxv4i16_offset_min(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { define <vscale x 4 x i16> @splice_nxv4i16_offset_min(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv4i16_offset_min: ; CHECK-LABEL: splice_nxv4i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: vslideup.vi v8, v9, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -8) %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -8)
ret <vscale x 4 x i16> %res ret <vscale x 4 x i16> %res
} }
define <vscale x 4 x i16> @splice_nxv4i16_offset_max(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 { define <vscale x 4 x i16> @splice_nxv4i16_offset_max(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv4i16_offset_max: ; CHECK-LABEL: splice_nxv4i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 7) %res = call <vscale x 4 x i16> @llvm.experimental.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 7)
ret <vscale x 4 x i16> %res ret <vscale x 4 x i16> %res
} }
declare <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32) declare <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
define <vscale x 8 x i16> @splice_nxv8i16_offset_zero(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { define <vscale x 8 x i16> @splice_nxv8i16_offset_zero(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv8i16_offset_zero: ; CHECK-LABEL: splice_nxv8i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 0) %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 0)
ret <vscale x 8 x i16> %res ret <vscale x 8 x i16> %res
} }
define <vscale x 8 x i16> @splice_nxv8i16_offset_negone(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { define <vscale x 8 x i16> @splice_nxv8i16_offset_negone(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv8i16_offset_negone: ; CHECK-LABEL: splice_nxv8i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -1) %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -1)
ret <vscale x 8 x i16> %res ret <vscale x 8 x i16> %res
} }
define <vscale x 8 x i16> @splice_nxv8i16_offset_min(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { define <vscale x 8 x i16> @splice_nxv8i16_offset_min(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv8i16_offset_min: ; CHECK-LABEL: splice_nxv8i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 16 ; CHECK-NEXT: vslideup.vi v8, v10, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -16) %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -16)
ret <vscale x 8 x i16> %res ret <vscale x 8 x i16> %res
} }
define <vscale x 8 x i16> @splice_nxv8i16_offset_max(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 { define <vscale x 8 x i16> @splice_nxv8i16_offset_max(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv8i16_offset_max: ; CHECK-LABEL: splice_nxv8i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 15) %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 15)
ret <vscale x 8 x i16> %res ret <vscale x 8 x i16> %res
} }
declare <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, i32) declare <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, i32)
define <vscale x 16 x i16> @splice_nxv16i16_offset_zero(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { define <vscale x 16 x i16> @splice_nxv16i16_offset_zero(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv16i16_offset_zero: ; CHECK-LABEL: splice_nxv16i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 0) %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 0)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
define <vscale x 16 x i16> @splice_nxv16i16_offset_negone(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { define <vscale x 16 x i16> @splice_nxv16i16_offset_negone(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv16i16_offset_negone: ; CHECK-LABEL: splice_nxv16i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -1) %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -1)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
define <vscale x 16 x i16> @splice_nxv16i16_offset_min(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { define <vscale x 16 x i16> @splice_nxv16i16_offset_min(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv16i16_offset_min: ; CHECK-LABEL: splice_nxv16i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -32) %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -32)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
define <vscale x 16 x i16> @splice_nxv16i16_offset_max(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 { define <vscale x 16 x i16> @splice_nxv16i16_offset_max(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv16i16_offset_max: ; CHECK-LABEL: splice_nxv16i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: addi a0, a0, -31
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vslidedown.vi v8, v8, 31
; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 31) %res = call <vscale x 16 x i16> @llvm.experimental.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 31)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
declare <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, i32) declare <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, i32)
define <vscale x 32 x i16> @splice_nxv32i16_offset_zero(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { define <vscale x 32 x i16> @splice_nxv32i16_offset_zero(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv32i16_offset_zero: ; CHECK-LABEL: splice_nxv32i16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 0) %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 0)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
define <vscale x 32 x i16> @splice_nxv32i16_offset_negone(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { define <vscale x 32 x i16> @splice_nxv32i16_offset_negone(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv32i16_offset_negone: ; CHECK-LABEL: splice_nxv32i16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -1) %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -1)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
define <vscale x 32 x i16> @splice_nxv32i16_offset_min(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { define <vscale x 32 x i16> @splice_nxv32i16_offset_min(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv32i16_offset_min: ; CHECK-LABEL: splice_nxv32i16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: addi a0, a0, -64
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -64) %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -64)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
define <vscale x 32 x i16> @splice_nxv32i16_offset_max(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 { define <vscale x 32 x i16> @splice_nxv32i16_offset_max(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
; CHECK-LABEL: splice_nxv32i16_offset_max: ; CHECK-LABEL: splice_nxv32i16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: addi a0, a0, -63
; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 63) %res = call <vscale x 32 x i16> @llvm.experimental.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 63)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
declare <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, i32) declare <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, i32)
define <vscale x 1 x i32> @splice_nxv1i32_offset_zero(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { define <vscale x 1 x i32> @splice_nxv1i32_offset_zero(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv1i32_offset_zero: ; CHECK-LABEL: splice_nxv1i32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 0) %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 0)
ret <vscale x 1 x i32> %res ret <vscale x 1 x i32> %res
} }
define <vscale x 1 x i32> @splice_nxv1i32_offset_negone(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { define <vscale x 1 x i32> @splice_nxv1i32_offset_negone(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv1i32_offset_negone: ; CHECK-LABEL: splice_nxv1i32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -1) %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -1)
ret <vscale x 1 x i32> %res ret <vscale x 1 x i32> %res
} }
define <vscale x 1 x i32> @splice_nxv1i32_offset_min(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { define <vscale x 1 x i32> @splice_nxv1i32_offset_min(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv1i32_offset_min: ; CHECK-LABEL: splice_nxv1i32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -2) %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -2)
ret <vscale x 1 x i32> %res ret <vscale x 1 x i32> %res
} }
define <vscale x 1 x i32> @splice_nxv1i32_offset_max(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 { define <vscale x 1 x i32> @splice_nxv1i32_offset_max(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv1i32_offset_max: ; CHECK-LABEL: splice_nxv1i32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 1) %res = call <vscale x 1 x i32> @llvm.experimental.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 1)
ret <vscale x 1 x i32> %res ret <vscale x 1 x i32> %res
} }
declare <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i32) declare <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i32)
define <vscale x 2 x i32> @splice_nxv2i32_offset_zero(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { define <vscale x 2 x i32> @splice_nxv2i32_offset_zero(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv2i32_offset_zero: ; CHECK-LABEL: splice_nxv2i32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 0) %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 0)
ret <vscale x 2 x i32> %res ret <vscale x 2 x i32> %res
} }
define <vscale x 2 x i32> @splice_nxv2i32_offset_negone(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { define <vscale x 2 x i32> @splice_nxv2i32_offset_negone(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv2i32_offset_negone: ; CHECK-LABEL: splice_nxv2i32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -1) %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -1)
ret <vscale x 2 x i32> %res ret <vscale x 2 x i32> %res
} }
define <vscale x 2 x i32> @splice_nxv2i32_offset_min(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { define <vscale x 2 x i32> @splice_nxv2i32_offset_min(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv2i32_offset_min: ; CHECK-LABEL: splice_nxv2i32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -4) %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -4)
ret <vscale x 2 x i32> %res ret <vscale x 2 x i32> %res
} }
define <vscale x 2 x i32> @splice_nxv2i32_offset_max(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 { define <vscale x 2 x i32> @splice_nxv2i32_offset_max(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv2i32_offset_max: ; CHECK-LABEL: splice_nxv2i32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 3) %res = call <vscale x 2 x i32> @llvm.experimental.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 3)
ret <vscale x 2 x i32> %res ret <vscale x 2 x i32> %res
} }
declare <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32) declare <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
define <vscale x 4 x i32> @splice_nxv4i32_offset_zero(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { define <vscale x 4 x i32> @splice_nxv4i32_offset_zero(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv4i32_offset_zero: ; CHECK-LABEL: splice_nxv4i32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 0) %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 0)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
define <vscale x 4 x i32> @splice_nxv4i32_offset_negone(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { define <vscale x 4 x i32> @splice_nxv4i32_offset_negone(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv4i32_offset_negone: ; CHECK-LABEL: splice_nxv4i32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -1) %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -1)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
define <vscale x 4 x i32> @splice_nxv4i32_offset_min(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { define <vscale x 4 x i32> @splice_nxv4i32_offset_min(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv4i32_offset_min: ; CHECK-LABEL: splice_nxv4i32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 8 ; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -8) %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -8)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
define <vscale x 4 x i32> @splice_nxv4i32_offset_max(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 { define <vscale x 4 x i32> @splice_nxv4i32_offset_max(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv4i32_offset_max: ; CHECK-LABEL: splice_nxv4i32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 7) %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 7)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
declare <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32) declare <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32)
define <vscale x 8 x i32> @splice_nxv8i32_offset_zero(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { define <vscale x 8 x i32> @splice_nxv8i32_offset_zero(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv8i32_offset_zero: ; CHECK-LABEL: splice_nxv8i32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 0) %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 0)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 8 x i32> @splice_nxv8i32_offset_negone(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { define <vscale x 8 x i32> @splice_nxv8i32_offset_negone(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv8i32_offset_negone: ; CHECK-LABEL: splice_nxv8i32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -1) %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -1)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 8 x i32> @splice_nxv8i32_offset_min(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { define <vscale x 8 x i32> @splice_nxv8i32_offset_min(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv8i32_offset_min: ; CHECK-LABEL: splice_nxv8i32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 16 ; CHECK-NEXT: vslideup.vi v8, v12, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -16) %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -16)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 8 x i32> @splice_nxv8i32_offset_max(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 { define <vscale x 8 x i32> @splice_nxv8i32_offset_max(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv8i32_offset_max: ; CHECK-LABEL: splice_nxv8i32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 15) %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 15)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
declare <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, i32) declare <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, i32)
define <vscale x 16 x i32> @splice_nxv16i32_offset_zero(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { define <vscale x 16 x i32> @splice_nxv16i32_offset_zero(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv16i32_offset_zero: ; CHECK-LABEL: splice_nxv16i32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 0) %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 0)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
define <vscale x 16 x i32> @splice_nxv16i32_offset_negone(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { define <vscale x 16 x i32> @splice_nxv16i32_offset_negone(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv16i32_offset_negone: ; CHECK-LABEL: splice_nxv16i32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -1) %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -1)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
define <vscale x 16 x i32> @splice_nxv16i32_offset_min(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { define <vscale x 16 x i32> @splice_nxv16i32_offset_min(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv16i32_offset_min: ; CHECK-LABEL: splice_nxv16i32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -32) %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -32)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
define <vscale x 16 x i32> @splice_nxv16i32_offset_max(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 { define <vscale x 16 x i32> @splice_nxv16i32_offset_max(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
; CHECK-LABEL: splice_nxv16i32_offset_max: ; CHECK-LABEL: splice_nxv16i32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: addi a0, a0, -31
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vslidedown.vi v8, v8, 31
; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 31) %res = call <vscale x 16 x i32> @llvm.experimental.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 31)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
declare <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i32) declare <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i32)
define <vscale x 1 x i64> @splice_nxv1i64_offset_zero(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { define <vscale x 1 x i64> @splice_nxv1i64_offset_zero(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv1i64_offset_zero: ; CHECK-LABEL: splice_nxv1i64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 0) %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 0)
ret <vscale x 1 x i64> %res ret <vscale x 1 x i64> %res
} }
define <vscale x 1 x i64> @splice_nxv1i64_offset_negone(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { define <vscale x 1 x i64> @splice_nxv1i64_offset_negone(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv1i64_offset_negone: ; CHECK-LABEL: splice_nxv1i64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -1) %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -1)
ret <vscale x 1 x i64> %res ret <vscale x 1 x i64> %res
} }
define <vscale x 1 x i64> @splice_nxv1i64_offset_min(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { define <vscale x 1 x i64> @splice_nxv1i64_offset_min(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv1i64_offset_min: ; CHECK-LABEL: splice_nxv1i64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -2) %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -2)
ret <vscale x 1 x i64> %res ret <vscale x 1 x i64> %res
} }
define <vscale x 1 x i64> @splice_nxv1i64_offset_max(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 { define <vscale x 1 x i64> @splice_nxv1i64_offset_max(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv1i64_offset_max: ; CHECK-LABEL: splice_nxv1i64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 1) %res = call <vscale x 1 x i64> @llvm.experimental.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 1)
ret <vscale x 1 x i64> %res ret <vscale x 1 x i64> %res
} }
declare <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32) declare <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
define <vscale x 2 x i64> @splice_nxv2i64_offset_zero(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { define <vscale x 2 x i64> @splice_nxv2i64_offset_zero(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv2i64_offset_zero: ; CHECK-LABEL: splice_nxv2i64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 0) %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 0)
ret <vscale x 2 x i64> %res ret <vscale x 2 x i64> %res
} }
define <vscale x 2 x i64> @splice_nxv2i64_offset_negone(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { define <vscale x 2 x i64> @splice_nxv2i64_offset_negone(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv2i64_offset_negone: ; CHECK-LABEL: splice_nxv2i64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -1) %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -1)
ret <vscale x 2 x i64> %res ret <vscale x 2 x i64> %res
} }
define <vscale x 2 x i64> @splice_nxv2i64_offset_min(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { define <vscale x 2 x i64> @splice_nxv2i64_offset_min(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv2i64_offset_min: ; CHECK-LABEL: splice_nxv2i64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 4 ; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -4) %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -4)
ret <vscale x 2 x i64> %res ret <vscale x 2 x i64> %res
} }
define <vscale x 2 x i64> @splice_nxv2i64_offset_max(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 { define <vscale x 2 x i64> @splice_nxv2i64_offset_max(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv2i64_offset_max: ; CHECK-LABEL: splice_nxv2i64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 3) %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 3)
ret <vscale x 2 x i64> %res ret <vscale x 2 x i64> %res
} }
declare <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i32) declare <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i32)
define <vscale x 4 x i64> @splice_nxv4i64_offset_zero(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { define <vscale x 4 x i64> @splice_nxv4i64_offset_zero(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv4i64_offset_zero: ; CHECK-LABEL: splice_nxv4i64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 0) %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 0)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
define <vscale x 4 x i64> @splice_nxv4i64_offset_negone(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { define <vscale x 4 x i64> @splice_nxv4i64_offset_negone(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv4i64_offset_negone: ; CHECK-LABEL: splice_nxv4i64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -1) %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -1)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
define <vscale x 4 x i64> @splice_nxv4i64_offset_min(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { define <vscale x 4 x i64> @splice_nxv4i64_offset_min(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv4i64_offset_min: ; CHECK-LABEL: splice_nxv4i64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 8 ; CHECK-NEXT: vslideup.vi v8, v12, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -8) %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -8)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
define <vscale x 4 x i64> @splice_nxv4i64_offset_max(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 { define <vscale x 4 x i64> @splice_nxv4i64_offset_max(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv4i64_offset_max: ; CHECK-LABEL: splice_nxv4i64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 7) %res = call <vscale x 4 x i64> @llvm.experimental.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 7)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
declare <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i32) declare <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i32)
define <vscale x 8 x i64> @splice_nxv8i64_offset_zero(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { define <vscale x 8 x i64> @splice_nxv8i64_offset_zero(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv8i64_offset_zero: ; CHECK-LABEL: splice_nxv8i64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 0) %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 0)
ret <vscale x 8 x i64> %res ret <vscale x 8 x i64> %res
} }
define <vscale x 8 x i64> @splice_nxv8i64_offset_negone(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { define <vscale x 8 x i64> @splice_nxv8i64_offset_negone(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv8i64_offset_negone: ; CHECK-LABEL: splice_nxv8i64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -1) %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -1)
ret <vscale x 8 x i64> %res ret <vscale x 8 x i64> %res
} }
define <vscale x 8 x i64> @splice_nxv8i64_offset_min(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { define <vscale x 8 x i64> @splice_nxv8i64_offset_min(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv8i64_offset_min: ; CHECK-LABEL: splice_nxv8i64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: vslideup.vi v8, v16, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -16) %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -16)
ret <vscale x 8 x i64> %res ret <vscale x 8 x i64> %res
} }
define <vscale x 8 x i64> @splice_nxv8i64_offset_max(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 { define <vscale x 8 x i64> @splice_nxv8i64_offset_max(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
; CHECK-LABEL: splice_nxv8i64_offset_max: ; CHECK-LABEL: splice_nxv8i64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 15) %res = call <vscale x 8 x i64> @llvm.experimental.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 15)
ret <vscale x 8 x i64> %res ret <vscale x 8 x i64> %res
} }
declare <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, i32) declare <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, i32)
define <vscale x 1 x half> @splice_nxv1f16_offset_zero(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { define <vscale x 1 x half> @splice_nxv1f16_offset_zero(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
; CHECK-LABEL: splice_nxv1f16_offset_zero: ; CHECK-LABEL: splice_nxv1f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 0) %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 0)
ret <vscale x 1 x half> %res ret <vscale x 1 x half> %res
} }
define <vscale x 1 x half> @splice_nxv1f16_offset_negone(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { define <vscale x 1 x half> @splice_nxv1f16_offset_negone(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
; CHECK-LABEL: splice_nxv1f16_offset_negone: ; CHECK-LABEL: splice_nxv1f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -1) %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -1)
ret <vscale x 1 x half> %res ret <vscale x 1 x half> %res
} }
define <vscale x 1 x half> @splice_nxv1f16_offset_min(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { define <vscale x 1 x half> @splice_nxv1f16_offset_min(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
; CHECK-LABEL: splice_nxv1f16_offset_min: ; CHECK-LABEL: splice_nxv1f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -2) %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -2)
ret <vscale x 1 x half> %res ret <vscale x 1 x half> %res
} }
define <vscale x 1 x half> @splice_nxv1f16_offset_max(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 { define <vscale x 1 x half> @splice_nxv1f16_offset_max(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
; CHECK-LABEL: splice_nxv1f16_offset_max: ; CHECK-LABEL: splice_nxv1f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 1) %res = call <vscale x 1 x half> @llvm.experimental.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 1)
ret <vscale x 1 x half> %res ret <vscale x 1 x half> %res
} }
declare <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32) declare <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32)
define <vscale x 2 x half> @splice_nxv2f16_offset_zero(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { define <vscale x 2 x half> @splice_nxv2f16_offset_zero(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
; CHECK-LABEL: splice_nxv2f16_offset_zero: ; CHECK-LABEL: splice_nxv2f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 0) %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 0)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @splice_nxv2f16_offset_negone(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { define <vscale x 2 x half> @splice_nxv2f16_offset_negone(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
; CHECK-LABEL: splice_nxv2f16_offset_negone: ; CHECK-LABEL: splice_nxv2f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1) %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @splice_nxv2f16_offset_min(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { define <vscale x 2 x half> @splice_nxv2f16_offset_min(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
; CHECK-LABEL: splice_nxv2f16_offset_min: ; CHECK-LABEL: splice_nxv2f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -4) %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -4)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 2 x half> @splice_nxv2f16_offset_max(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 { define <vscale x 2 x half> @splice_nxv2f16_offset_max(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
; CHECK-LABEL: splice_nxv2f16_offset_max: ; CHECK-LABEL: splice_nxv2f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 3) %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 3)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
declare <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32) declare <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32)
define <vscale x 4 x half> @splice_nxv4f16_offset_zero(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { define <vscale x 4 x half> @splice_nxv4f16_offset_zero(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
; CHECK-LABEL: splice_nxv4f16_offset_zero: ; CHECK-LABEL: splice_nxv4f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 0) %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 0)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @splice_nxv4f16_offset_negone(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { define <vscale x 4 x half> @splice_nxv4f16_offset_negone(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
; CHECK-LABEL: splice_nxv4f16_offset_negone: ; CHECK-LABEL: splice_nxv4f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1) %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @splice_nxv4f16_offset_min(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { define <vscale x 4 x half> @splice_nxv4f16_offset_min(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
; CHECK-LABEL: splice_nxv4f16_offset_min: ; CHECK-LABEL: splice_nxv4f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 8 ; CHECK-NEXT: vslideup.vi v8, v9, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -8) %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -8)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
define <vscale x 4 x half> @splice_nxv4f16_offset_max(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 { define <vscale x 4 x half> @splice_nxv4f16_offset_max(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
; CHECK-LABEL: splice_nxv4f16_offset_max: ; CHECK-LABEL: splice_nxv4f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e16, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 7) %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 7)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
declare <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32) declare <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32)
define <vscale x 8 x half> @splice_nxv8f16_offset_zero(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { define <vscale x 8 x half> @splice_nxv8f16_offset_zero(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
; CHECK-LABEL: splice_nxv8f16_offset_zero: ; CHECK-LABEL: splice_nxv8f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 0) %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 0)
ret <vscale x 8 x half> %res ret <vscale x 8 x half> %res
} }
define <vscale x 8 x half> @splice_nxv8f16_offset_negone(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { define <vscale x 8 x half> @splice_nxv8f16_offset_negone(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
; CHECK-LABEL: splice_nxv8f16_offset_negone: ; CHECK-LABEL: splice_nxv8f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -1) %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -1)
ret <vscale x 8 x half> %res ret <vscale x 8 x half> %res
} }
define <vscale x 8 x half> @splice_nxv8f16_offset_min(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { define <vscale x 8 x half> @splice_nxv8f16_offset_min(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
; CHECK-LABEL: splice_nxv8f16_offset_min: ; CHECK-LABEL: splice_nxv8f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 16 ; CHECK-NEXT: vslideup.vi v8, v10, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -16) %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -16)
ret <vscale x 8 x half> %res ret <vscale x 8 x half> %res
} }
define <vscale x 8 x half> @splice_nxv8f16_offset_max(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 { define <vscale x 8 x half> @splice_nxv8f16_offset_max(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
; CHECK-LABEL: splice_nxv8f16_offset_max: ; CHECK-LABEL: splice_nxv8f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e16, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 15) %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 15)
ret <vscale x 8 x half> %res ret <vscale x 8 x half> %res
} }
declare <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, i32) declare <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, i32)
define <vscale x 16 x half> @splice_nxv16f16_offset_zero(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { define <vscale x 16 x half> @splice_nxv16f16_offset_zero(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
; CHECK-LABEL: splice_nxv16f16_offset_zero: ; CHECK-LABEL: splice_nxv16f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 0) %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 0)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
define <vscale x 16 x half> @splice_nxv16f16_offset_negone(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { define <vscale x 16 x half> @splice_nxv16f16_offset_negone(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
; CHECK-LABEL: splice_nxv16f16_offset_negone: ; CHECK-LABEL: splice_nxv16f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -1) %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -1)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
define <vscale x 16 x half> @splice_nxv16f16_offset_min(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { define <vscale x 16 x half> @splice_nxv16f16_offset_min(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
; CHECK-LABEL: splice_nxv16f16_offset_min: ; CHECK-LABEL: splice_nxv16f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -32) %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -32)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
define <vscale x 16 x half> @splice_nxv16f16_offset_max(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 { define <vscale x 16 x half> @splice_nxv16f16_offset_max(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
; CHECK-LABEL: splice_nxv16f16_offset_max: ; CHECK-LABEL: splice_nxv16f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: addi a0, a0, -31
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vslidedown.vi v8, v8, 31
; CHECK-NEXT: vsetvli a1, zero, e16, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 31) %res = call <vscale x 16 x half> @llvm.experimental.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 31)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
declare <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, i32) declare <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, i32)
define <vscale x 32 x half> @splice_nxv32f16_offset_zero(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { define <vscale x 32 x half> @splice_nxv32f16_offset_zero(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
; CHECK-LABEL: splice_nxv32f16_offset_zero: ; CHECK-LABEL: splice_nxv32f16_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 0) %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 0)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
define <vscale x 32 x half> @splice_nxv32f16_offset_negone(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { define <vscale x 32 x half> @splice_nxv32f16_offset_negone(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
; CHECK-LABEL: splice_nxv32f16_offset_negone: ; CHECK-LABEL: splice_nxv32f16_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -1) %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -1)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
define <vscale x 32 x half> @splice_nxv32f16_offset_min(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { define <vscale x 32 x half> @splice_nxv32f16_offset_min(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
; CHECK-LABEL: splice_nxv32f16_offset_min: ; CHECK-LABEL: splice_nxv32f16_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -64 ; CHECK-NEXT: addi a0, a0, -64
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -64) %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -64)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
define <vscale x 32 x half> @splice_nxv32f16_offset_max(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 { define <vscale x 32 x half> @splice_nxv32f16_offset_max(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
; CHECK-LABEL: splice_nxv32f16_offset_max: ; CHECK-LABEL: splice_nxv32f16_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -63 ; CHECK-NEXT: addi a0, a0, -63
; CHECK-NEXT: li a1, 63 ; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 63) %res = call <vscale x 32 x half> @llvm.experimental.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 63)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
declare <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, i32) declare <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, i32)
define <vscale x 1 x float> @splice_nxv1f32_offset_zero(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { define <vscale x 1 x float> @splice_nxv1f32_offset_zero(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
; CHECK-LABEL: splice_nxv1f32_offset_zero: ; CHECK-LABEL: splice_nxv1f32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 0) %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 0)
ret <vscale x 1 x float> %res ret <vscale x 1 x float> %res
} }
define <vscale x 1 x float> @splice_nxv1f32_offset_negone(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { define <vscale x 1 x float> @splice_nxv1f32_offset_negone(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
; CHECK-LABEL: splice_nxv1f32_offset_negone: ; CHECK-LABEL: splice_nxv1f32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -1) %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -1)
ret <vscale x 1 x float> %res ret <vscale x 1 x float> %res
} }
define <vscale x 1 x float> @splice_nxv1f32_offset_min(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { define <vscale x 1 x float> @splice_nxv1f32_offset_min(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
; CHECK-LABEL: splice_nxv1f32_offset_min: ; CHECK-LABEL: splice_nxv1f32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -2) %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -2)
ret <vscale x 1 x float> %res ret <vscale x 1 x float> %res
} }
define <vscale x 1 x float> @splice_nxv1f32_offset_max(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 { define <vscale x 1 x float> @splice_nxv1f32_offset_max(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
; CHECK-LABEL: splice_nxv1f32_offset_max: ; CHECK-LABEL: splice_nxv1f32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 1) %res = call <vscale x 1 x float> @llvm.experimental.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 1)
ret <vscale x 1 x float> %res ret <vscale x 1 x float> %res
} }
declare <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32) declare <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32)
define <vscale x 2 x float> @splice_nxv2f32_offset_zero(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { define <vscale x 2 x float> @splice_nxv2f32_offset_zero(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
; CHECK-LABEL: splice_nxv2f32_offset_zero: ; CHECK-LABEL: splice_nxv2f32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 0) %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 0)
ret <vscale x 2 x float> %res ret <vscale x 2 x float> %res
} }
define <vscale x 2 x float> @splice_nxv2f32_offset_negone(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { define <vscale x 2 x float> @splice_nxv2f32_offset_negone(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
; CHECK-LABEL: splice_nxv2f32_offset_negone: ; CHECK-LABEL: splice_nxv2f32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1) %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1)
ret <vscale x 2 x float> %res ret <vscale x 2 x float> %res
} }
define <vscale x 2 x float> @splice_nxv2f32_offset_min(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { define <vscale x 2 x float> @splice_nxv2f32_offset_min(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
; CHECK-LABEL: splice_nxv2f32_offset_min: ; CHECK-LABEL: splice_nxv2f32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -4) %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -4)
ret <vscale x 2 x float> %res ret <vscale x 2 x float> %res
} }
define <vscale x 2 x float> @splice_nxv2f32_offset_max(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 { define <vscale x 2 x float> @splice_nxv2f32_offset_max(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
; CHECK-LABEL: splice_nxv2f32_offset_max: ; CHECK-LABEL: splice_nxv2f32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e32, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 3) %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 3)
ret <vscale x 2 x float> %res ret <vscale x 2 x float> %res
} }
declare <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32) declare <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32)
define <vscale x 4 x float> @splice_nxv4f32_offset_zero(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { define <vscale x 4 x float> @splice_nxv4f32_offset_zero(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
; CHECK-LABEL: splice_nxv4f32_offset_zero: ; CHECK-LABEL: splice_nxv4f32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 0) %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 0)
ret <vscale x 4 x float> %res ret <vscale x 4 x float> %res
} }
define <vscale x 4 x float> @splice_nxv4f32_offset_negone(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { define <vscale x 4 x float> @splice_nxv4f32_offset_negone(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
; CHECK-LABEL: splice_nxv4f32_offset_negone: ; CHECK-LABEL: splice_nxv4f32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -1) %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -1)
ret <vscale x 4 x float> %res ret <vscale x 4 x float> %res
} }
define <vscale x 4 x float> @splice_nxv4f32_offset_min(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { define <vscale x 4 x float> @splice_nxv4f32_offset_min(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
; CHECK-LABEL: splice_nxv4f32_offset_min: ; CHECK-LABEL: splice_nxv4f32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 8 ; CHECK-NEXT: vslideup.vi v8, v10, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -8) %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -8)
ret <vscale x 4 x float> %res ret <vscale x 4 x float> %res
} }
define <vscale x 4 x float> @splice_nxv4f32_offset_max(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 { define <vscale x 4 x float> @splice_nxv4f32_offset_max(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
; CHECK-LABEL: splice_nxv4f32_offset_max: ; CHECK-LABEL: splice_nxv4f32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e32, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 7) %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 7)
ret <vscale x 4 x float> %res ret <vscale x 4 x float> %res
} }
declare <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, i32) declare <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, i32)
define <vscale x 8 x float> @splice_nxv8f32_offset_zero(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { define <vscale x 8 x float> @splice_nxv8f32_offset_zero(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
; CHECK-LABEL: splice_nxv8f32_offset_zero: ; CHECK-LABEL: splice_nxv8f32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 0) %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 0)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
define <vscale x 8 x float> @splice_nxv8f32_offset_negone(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { define <vscale x 8 x float> @splice_nxv8f32_offset_negone(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
; CHECK-LABEL: splice_nxv8f32_offset_negone: ; CHECK-LABEL: splice_nxv8f32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -1) %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -1)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
define <vscale x 8 x float> @splice_nxv8f32_offset_min(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { define <vscale x 8 x float> @splice_nxv8f32_offset_min(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
; CHECK-LABEL: splice_nxv8f32_offset_min: ; CHECK-LABEL: splice_nxv8f32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 16 ; CHECK-NEXT: vslideup.vi v8, v12, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -16) %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -16)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
define <vscale x 8 x float> @splice_nxv8f32_offset_max(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 { define <vscale x 8 x float> @splice_nxv8f32_offset_max(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
; CHECK-LABEL: splice_nxv8f32_offset_max: ; CHECK-LABEL: splice_nxv8f32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e32, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 15) %res = call <vscale x 8 x float> @llvm.experimental.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 15)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
declare <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32) declare <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32)
define <vscale x 16 x float> @splice_nxv16f32_offset_zero(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_offset_zero(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_offset_zero: ; CHECK-LABEL: splice_nxv16f32_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 0) %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 0)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
define <vscale x 16 x float> @splice_nxv16f32_offset_negone(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_offset_negone(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_offset_negone: ; CHECK-LABEL: splice_nxv16f32_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -1) %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -1)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
define <vscale x 16 x float> @splice_nxv16f32_offset_min(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_offset_min(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_offset_min: ; CHECK-LABEL: splice_nxv16f32_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -32 ; CHECK-NEXT: addi a0, a0, -32
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: vslideup.vx v8, v16, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -32) %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -32)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
define <vscale x 16 x float> @splice_nxv16f32_offset_max(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 { define <vscale x 16 x float> @splice_nxv16f32_offset_max(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
; CHECK-LABEL: splice_nxv16f32_offset_max: ; CHECK-LABEL: splice_nxv16f32_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -31 ; CHECK-NEXT: addi a0, a0, -31
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 31 ; CHECK-NEXT: vslidedown.vi v8, v8, 31
; CHECK-NEXT: vsetvli a1, zero, e32, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 31) %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 31)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
declare <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i32) declare <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i32)
define <vscale x 1 x double> @splice_nxv1f64_offset_zero(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { define <vscale x 1 x double> @splice_nxv1f64_offset_zero(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
; CHECK-LABEL: splice_nxv1f64_offset_zero: ; CHECK-LABEL: splice_nxv1f64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 0) %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 0)
ret <vscale x 1 x double> %res ret <vscale x 1 x double> %res
} }
define <vscale x 1 x double> @splice_nxv1f64_offset_negone(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { define <vscale x 1 x double> @splice_nxv1f64_offset_negone(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
; CHECK-LABEL: splice_nxv1f64_offset_negone: ; CHECK-LABEL: splice_nxv1f64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -1) %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -1)
ret <vscale x 1 x double> %res ret <vscale x 1 x double> %res
} }
define <vscale x 1 x double> @splice_nxv1f64_offset_min(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { define <vscale x 1 x double> @splice_nxv1f64_offset_min(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
; CHECK-LABEL: splice_nxv1f64_offset_min: ; CHECK-LABEL: splice_nxv1f64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -2 ; CHECK-NEXT: addi a0, a0, -2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -2) %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -2)
ret <vscale x 1 x double> %res ret <vscale x 1 x double> %res
} }
define <vscale x 1 x double> @splice_nxv1f64_offset_max(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 { define <vscale x 1 x double> @splice_nxv1f64_offset_max(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
; CHECK-LABEL: splice_nxv1f64_offset_max: ; CHECK-LABEL: splice_nxv1f64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 1) %res = call <vscale x 1 x double> @llvm.experimental.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 1)
ret <vscale x 1 x double> %res ret <vscale x 1 x double> %res
} }
declare <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32) declare <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32)
define <vscale x 2 x double> @splice_nxv2f64_offset_zero(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { define <vscale x 2 x double> @splice_nxv2f64_offset_zero(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
; CHECK-LABEL: splice_nxv2f64_offset_zero: ; CHECK-LABEL: splice_nxv2f64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 0) %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 0)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
define <vscale x 2 x double> @splice_nxv2f64_offset_negone(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { define <vscale x 2 x double> @splice_nxv2f64_offset_negone(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
; CHECK-LABEL: splice_nxv2f64_offset_negone: ; CHECK-LABEL: splice_nxv2f64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -1) %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -1)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
define <vscale x 2 x double> @splice_nxv2f64_offset_min(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { define <vscale x 2 x double> @splice_nxv2f64_offset_min(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
; CHECK-LABEL: splice_nxv2f64_offset_min: ; CHECK-LABEL: splice_nxv2f64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: addi a0, a0, -4
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 4 ; CHECK-NEXT: vslideup.vi v8, v10, 4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -4) %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -4)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
define <vscale x 2 x double> @splice_nxv2f64_offset_max(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 { define <vscale x 2 x double> @splice_nxv2f64_offset_max(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
; CHECK-LABEL: splice_nxv2f64_offset_max: ; CHECK-LABEL: splice_nxv2f64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -3 ; CHECK-NEXT: addi a0, a0, -3
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3 ; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: vsetvli a1, zero, e64, m2, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 3) %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 3)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
declare <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, i32) declare <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, i32)
define <vscale x 4 x double> @splice_nxv4f64_offset_zero(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { define <vscale x 4 x double> @splice_nxv4f64_offset_zero(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
; CHECK-LABEL: splice_nxv4f64_offset_zero: ; CHECK-LABEL: splice_nxv4f64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 0) %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 0)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
define <vscale x 4 x double> @splice_nxv4f64_offset_negone(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { define <vscale x 4 x double> @splice_nxv4f64_offset_negone(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
; CHECK-LABEL: splice_nxv4f64_offset_negone: ; CHECK-LABEL: splice_nxv4f64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -1) %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -1)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
define <vscale x 4 x double> @splice_nxv4f64_offset_min(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { define <vscale x 4 x double> @splice_nxv4f64_offset_min(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
; CHECK-LABEL: splice_nxv4f64_offset_min: ; CHECK-LABEL: splice_nxv4f64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -8 ; CHECK-NEXT: addi a0, a0, -8
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 8 ; CHECK-NEXT: vslideup.vi v8, v12, 8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -8) %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -8)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
define <vscale x 4 x double> @splice_nxv4f64_offset_max(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 { define <vscale x 4 x double> @splice_nxv4f64_offset_max(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
; CHECK-LABEL: splice_nxv4f64_offset_max: ; CHECK-LABEL: splice_nxv4f64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -7 ; CHECK-NEXT: addi a0, a0, -7
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetvli a1, zero, e64, m4, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 7) %res = call <vscale x 4 x double> @llvm.experimental.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 7)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
declare <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, i32) declare <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, i32)
define <vscale x 8 x double> @splice_nxv8f64_offset_zero(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { define <vscale x 8 x double> @splice_nxv8f64_offset_zero(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
; CHECK-LABEL: splice_nxv8f64_offset_zero: ; CHECK-LABEL: splice_nxv8f64_offset_zero:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 0) %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 0)
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
define <vscale x 8 x double> @splice_nxv8f64_offset_negone(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { define <vscale x 8 x double> @splice_nxv8f64_offset_negone(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
; CHECK-LABEL: splice_nxv8f64_offset_negone: ; CHECK-LABEL: splice_nxv8f64_offset_negone:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: vslideup.vi v8, v16, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -1) %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -1)
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
define <vscale x 8 x double> @splice_nxv8f64_offset_min(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { define <vscale x 8 x double> @splice_nxv8f64_offset_min(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
; CHECK-LABEL: splice_nxv8f64_offset_min: ; CHECK-LABEL: splice_nxv8f64_offset_min:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -16 ; CHECK-NEXT: addi a0, a0, -16
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: vslideup.vi v8, v16, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -16) %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -16)
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 { define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
; CHECK-LABEL: splice_nxv8f64_offset_max: ; CHECK-LABEL: splice_nxv8f64_offset_max:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -15 ; CHECK-NEXT: addi a0, a0, -15
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 15 ; CHECK-NEXT: vslidedown.vi v8, v8, 15
; CHECK-NEXT: vsetvli a1, zero, e64, m8, tu, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 15) %res = call <vscale x 8 x double> @llvm.experimental.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 15)
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
attributes #0 = { vscale_range(2,2) } attributes #0 = { vscale_range(2,2) }

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i8> @intrinsic_vslidedown_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i8> @intrinsic_vslidedown_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i8> @intrinsic_vslidedown_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x i8> @intrinsic_vslidedown_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 32 x i8> @intrinsic_vslidedown_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i16> @intrinsic_vslidedown_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i16> @intrinsic_vslidedown_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i16> @intrinsic_vslidedown_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i16> @intrinsic_vslidedown_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x i16> @intrinsic_vslidedown_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i32> @intrinsic_vslidedown_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i32> @intrinsic_vslidedown_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i32> @intrinsic_vslidedown_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i32> @intrinsic_vslidedown_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i64> @intrinsic_vslidedown_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i64> @intrinsic_vslidedown_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i64> @intrinsic_vslidedown_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x half> @intrinsic_vslidedown_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x half> @intrinsic_vslidedown_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x half> @intrinsic_vslidedown_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x half> @intrinsic_vslidedown_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x half> @intrinsic_vslidedown_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x float> @intrinsic_vslidedown_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x float> @intrinsic_vslidedown_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x float> @intrinsic_vslidedown_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x float> @intrinsic_vslidedown_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x double> @intrinsic_vslidedown_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x double> @intrinsic_vslidedown_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x double> @intrinsic_vslidedown_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i8> @intrinsic_vslidedown_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i8> @intrinsic_vslidedown_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i8> @intrinsic_vslidedown_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x i8> @intrinsic_vslidedown_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 32 x i8> @intrinsic_vslidedown_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i16> @intrinsic_vslidedown_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i16> @intrinsic_vslidedown_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i16> @intrinsic_vslidedown_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i16> @intrinsic_vslidedown_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x i16> @intrinsic_vslidedown_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i32> @intrinsic_vslidedown_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i32> @intrinsic_vslidedown_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i32> @intrinsic_vslidedown_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i32> @intrinsic_vslidedown_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i64> @intrinsic_vslidedown_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i64> @intrinsic_vslidedown_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i64> @intrinsic_vslidedown_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x half> @intrinsic_vslidedown_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x half> @intrinsic_vslidedown_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x half> @intrinsic_vslidedown_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x half> @intrinsic_vslidedown_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x half> @intrinsic_vslidedown_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x float> @intrinsic_vslidedown_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x float> @intrinsic_vslidedown_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x float> @intrinsic_vslidedown_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x float> @intrinsic_vslidedown_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x double> @intrinsic_vslidedown_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: vslidedown.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: vslidedown.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x double> @intrinsic_vslidedown_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: vslidedown.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: vslidedown.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x double> @intrinsic_vslidedown_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: vslidedown.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: vslidedown.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i8> @intrinsic_vslideup_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i8> @intrinsic_vslideup_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i8> @intrinsic_vslideup_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x i8> @intrinsic_vslideup_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
i32); i32,
i32
);
define <vscale x 32 x i8> @intrinsic_vslideup_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32, i32,
Show All 15 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i16> @intrinsic_vslideup_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i16> @intrinsic_vslideup_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i16> @intrinsic_vslideup_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i16> @intrinsic_vslideup_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x i16> @intrinsic_vslideup_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i32> @intrinsic_vslideup_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i32> @intrinsic_vslideup_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i32> @intrinsic_vslideup_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x i32> @intrinsic_vslideup_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x i64> @intrinsic_vslideup_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x i64> @intrinsic_vslideup_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x i64> @intrinsic_vslideup_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x half> @intrinsic_vslideup_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x half> @intrinsic_vslideup_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x half> @intrinsic_vslideup_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x half> @intrinsic_vslideup_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
i32); i32,
i32
);
define <vscale x 16 x half> @intrinsic_vslideup_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, i32 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i32, i32,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x float> @intrinsic_vslideup_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x float> @intrinsic_vslideup_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x float> @intrinsic_vslideup_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
i32); i32,
i32
);
define <vscale x 8 x float> @intrinsic_vslideup_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i32, i32,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 1 x double> @intrinsic_vslideup_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 2 x double> @intrinsic_vslideup_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
i32); i32,
i32
);
define <vscale x 4 x double> @intrinsic_vslideup_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 %2, i32 %2,
i32 %3) i32 %3,
i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i32, i32,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
i32 %4, i32 0) i32 %4, i32 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i32 9, i32 9,
i32 %2) i32 %2,
i32 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+experimental-zvfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8( declare <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.mask.nxv1i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i8> @intrinsic_vslideup_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8( declare <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.mask.nxv2i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vslideup.nxv2i8(
<vscale x 2 x i8> %0, <vscale x 2 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
define <vscale x 2 x i8> @intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i8> @intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i8> @intrinsic_vslideup_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8( declare <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.mask.nxv4i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8( %a = call <vscale x 4 x i8> @llvm.riscv.vslideup.nxv4i8(
<vscale x 4 x i8> %0, <vscale x 4 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
define <vscale x 4 x i8> @intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i8> @intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i8> @intrinsic_vslideup_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.mask.nxv8i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vslideup.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
define <vscale x 8 x i8> @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x i8> @intrinsic_vslideup_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8( declare <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.mask.nxv16i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8( %a = call <vscale x 16 x i8> @llvm.riscv.vslideup.nxv16i8(
<vscale x 16 x i8> %0, <vscale x 16 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
define <vscale x 16 x i8> @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i8> @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
i64); i64,
i64
);
define <vscale x 32 x i8> @intrinsic_vslideup_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8( declare <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64, i64,
Show All 15 Lines %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.mask.nxv32i8(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8( %a = call <vscale x 32 x i8> @llvm.riscv.vslideup.nxv32i8(
<vscale x 32 x i8> %0, <vscale x 32 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
define <vscale x 32 x i8> @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind { define <vscale x 32 x i8> @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i16> @intrinsic_vslideup_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16( declare <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.mask.nxv1i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16( %a = call <vscale x 1 x i16> @llvm.riscv.vslideup.nxv1i16(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
define <vscale x 1 x i16> @intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i16> @intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i16> @intrinsic_vslideup_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16( declare <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.mask.nxv2i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16( %a = call <vscale x 2 x i16> @llvm.riscv.vslideup.nxv2i16(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
define <vscale x 2 x i16> @intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i16> @intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i16> @intrinsic_vslideup_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.mask.nxv4i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vslideup.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
define <vscale x 4 x i16> @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i16> @intrinsic_vslideup_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16( declare <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.mask.nxv8i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16( %a = call <vscale x 8 x i16> @llvm.riscv.vslideup.nxv8i16(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
define <vscale x 8 x i16> @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i16> @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x i16> @intrinsic_vslideup_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16( declare <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.mask.nxv16i16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16( %a = call <vscale x 16 x i16> @llvm.riscv.vslideup.nxv16i16(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
define <vscale x 16 x i16> @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x i16> @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i32> @intrinsic_vslideup_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32( declare <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.mask.nxv1i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32( %a = call <vscale x 1 x i32> @llvm.riscv.vslideup.nxv1i32(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
define <vscale x 1 x i32> @intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i32> @intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i32> @intrinsic_vslideup_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.mask.nxv2i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vslideup.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
define <vscale x 2 x i32> @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i32> @intrinsic_vslideup_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32( declare <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.mask.nxv4i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32( %a = call <vscale x 4 x i32> @llvm.riscv.vslideup.nxv4i32(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
define <vscale x 4 x i32> @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i32> @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x i32> @intrinsic_vslideup_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32( declare <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.mask.nxv8i32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32( %a = call <vscale x 8 x i32> @llvm.riscv.vslideup.nxv8i32(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
define <vscale x 8 x i32> @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x i32> @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x i64> @intrinsic_vslideup_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.mask.nxv1i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vslideup.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
define <vscale x 1 x i64> @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x i64> @intrinsic_vslideup_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64( declare <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.mask.nxv2i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64( %a = call <vscale x 2 x i64> @llvm.riscv.vslideup.nxv2i64(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
define <vscale x 2 x i64> @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x i64> @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x i64> @intrinsic_vslideup_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64( declare <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.mask.nxv4i64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64( %a = call <vscale x 4 x i64> @llvm.riscv.vslideup.nxv4i64(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
define <vscale x 4 x i64> @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i64> @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x half> @intrinsic_vslideup_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x half> @llvm.riscv.vslideup.mask.nxv1f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vslideup.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
define <vscale x 1 x half> @intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x half> @intrinsic_vslideup_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x half> @llvm.riscv.vslideup.mask.nxv2f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vslideup.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
define <vscale x 2 x half> @intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x half> @intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x half> @intrinsic_vslideup_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x half> @llvm.riscv.vslideup.mask.nxv4f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vslideup.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
define <vscale x 4 x half> @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x half> @intrinsic_vslideup_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x half> @llvm.riscv.vslideup.mask.nxv8f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vslideup.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
define <vscale x 8 x half> @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x half> @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
i64); i64,
i64
);
define <vscale x 16 x half> @intrinsic_vslideup_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
i64, i64,
Show All 15 Lines %a = call <vscale x 16 x half> @llvm.riscv.vslideup.mask.nxv16f16(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vslideup.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
define <vscale x 16 x half> @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind { define <vscale x 16 x half> @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x float> @intrinsic_vslideup_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x float> @llvm.riscv.vslideup.mask.nxv1f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vslideup.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
define <vscale x 1 x float> @intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x float> @intrinsic_vslideup_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x float> @llvm.riscv.vslideup.mask.nxv2f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vslideup.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
define <vscale x 2 x float> @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x float> @intrinsic_vslideup_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x float> @llvm.riscv.vslideup.mask.nxv4f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vslideup.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
define <vscale x 4 x float> @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x float> @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
i64); i64,
i64
);
define <vscale x 8 x float> @intrinsic_vslideup_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, i64 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
i64, i64,
Show All 15 Lines %a = call <vscale x 8 x float> @llvm.riscv.vslideup.mask.nxv8f32(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vslideup.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
define <vscale x 8 x float> @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind { define <vscale x 8 x float> @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
Show All 9 Linesentry:
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 1 x double> @intrinsic_vslideup_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 1 x double> @llvm.riscv.vslideup.mask.nxv1f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: vslideup.vi v8, v9, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vslideup.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
define <vscale x 1 x double> @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
Show All 9 Linesentry:
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 2 x double> @intrinsic_vslideup_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 2 x double> @llvm.riscv.vslideup.mask.nxv2f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: vslideup.vi v8, v10, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vslideup.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
define <vscale x 2 x double> @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind { define <vscale x 2 x double> @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
Show All 9 Linesentry:
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
i64); i64,
i64
);
define <vscale x 4 x double> @intrinsic_vslideup_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: vslideup.vx v8, v12, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 %2, i64 %2,
i64 %3) i64 %3,
i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
i64, i64,
Show All 15 Lines %a = call <vscale x 4 x double> @llvm.riscv.vslideup.mask.nxv4f64(
i64 %4, i64 0) i64 %4, i64 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: vslideup.vi v8, v12, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vslideup.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
i64 9, i64 9,
i64 %2) i64 %2,
i64 1)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
define <vscale x 4 x double> @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x double> @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
Show All 12 Lines