[RISCV] Avoid pointer element type access for masked atomicrmw intrinsics

[nikic]

Summary

I'm trying to remove this pointer element type access as part of opaque pointer work, but am having a hard time understanding what the RISCV atomicrmw lowering is doing.

Is it correct to always use an i32 MVT for the masked.atomicrmw.*.i32 intrinsics? From my reading of the code, the expansion will access this size, but I'm not very confident in that reading...

[jrtc27]

I believe this is true; the "real" width is dealt with as part of the mask argument to the intrinsic, and as part of the IR expansion the input value for the RMW is shifted to the right position in the aligned i32. Looking at an i16 fetch+add the intrinsic gets an i32*.

[asb]

I think it's always correct as well. The minimum width for atomic memory operations on RISC-V is 32-bits, but of course to do operations on smaller types you can use lr.w/sc.w and manipulate the loaded value or sometimes use one of the amo* operations with appropriately modified parameters for an equivalent result.

[jyknight]

Looks right to me, too.

[jrtc27]

I suppose I should formally accept this

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::riscv_masked_atomicrmw_xchg_i32:
   case Intrinsic::riscv_masked_atomicrmw_add_i32:
   case Intrinsic::riscv_masked_atomicrmw_sub_i32:
   case Intrinsic::riscv_masked_atomicrmw_nand_i32:
   case Intrinsic::riscv_masked_atomicrmw_max_i32:
   case Intrinsic::riscv_masked_atomicrmw_min_i32:
   case Intrinsic::riscv_masked_atomicrmw_umax_i32:
   case Intrinsic::riscv_masked_atomicrmw_umin_i32:
-  case Intrinsic::riscv_masked_cmpxchg_i32: {
-    PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
+  case Intrinsic::riscv_masked_cmpxchg_i32:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
-    Info.memVT = MVT::getVT(PtrTy->getPointerElementType());
+    Info.memVT = MVT::i32;
     Info.ptrVal = I.getArgOperand(0);
     Info.offset = 0;
     Info.align = Align(4);
     Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore |
                  MachineMemOperand::MOVolatile;
     return true;
-  }
   case Intrinsic::riscv_masked_strided_load:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.ptrVal = I.getArgOperand(1);
     Info.memVT = getValueType(DL, I.getType()->getScalarType());
     Info.align = Align(DL.getTypeSizeInBits(I.getType()->getScalarType()) / 8);
     Info.size = MemoryLocation::UnknownSize;
     Info.flags |= MachineMemOperand::MOLoad;
     return true;