[RISCV] Decouple Zve* extensions.

[jacquesguan]

Summary

According to the v spec, there is no include relationship or dependency among the Zve* extensions. For exmaple, we do not need to implement Zve64x for Zve64f, these two are indepedent extensions. This patch decouple all Zve* extensions.

[eopXD]

Not sure if this simplifies things. Users and the compiler can use the macro __riscv_v_elen and __riscv_v_elen_fp to do things to the vector-related target feature.

Other than that I don't hold any strong objection to this refactoring.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

753

Now we need to check if multiple Zve extensions are specified at the same time?

[jacquesguan]

In D118225#3272071, @eopXD wrote:

Not sure if this simplifies things. Users and the compiler can use the macro __riscv_v_elen and __riscv_v_elen_fp to do things to the vector-related target feature.

Other than that I don't hold any strong objection to this refactoring.

This patch is similar with https://reviews.llvm.org/D117854. I think these five Zve* extensions are independent, we do not need to implement Zve32x for Zve64x, even all instructions of Zve32x is subset of instructions of Zve64x, same with other dependencies.
Current implemention of Zve* with depedency make some unclear. For example, in clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c, the error message shows that the buitin only needs Zve32x or V extension to be enable. But actually, if we just implement Zve64x, these builtins should work as well. These error messages is kind of confusing if we make Zve* extensions has depedent relationship.

[jacquesguan]

Address comment.

llvm/lib/Support/RISCVISAInfo.cpp

753

Done

[jacquesguan]

Update code

[kito-cheng]

Discussion on riscv-v-spec : https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867, although v-spec and isa-spec still not clearly describe that, but seems ISA folks prefer having those implication relationship between those zve* and v extensions.

clang/lib/Basic/Targets/RISCV.cpp

 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (MinVLen) {
     Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
     Builder.defineMacro("__riscv_v_elen", Twine(MaxELen));
     Builder.defineMacro("__riscv_v_elen_fp", Twine(MaxELenFp));
   }
 
   if (ISAInfo->hasExtension("c"))
     Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("zve32f") ||
+      ISAInfo->hasExtension("zve64x") || ISAInfo->hasExtension("zve64f") ||
+      ISAInfo->hasExtension("zve64d") || ISAInfo->hasExtension("v"))
     Builder.defineMacro("__riscv_vector");
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
 #define BUILTIN(ID, TYPE, ATTRS)                                               \
   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
     {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},

clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64V %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64V %s
 // RUN: not %clang_cc1 -triple riscv64 -emit-llvm-only %s 2>&1 | FileCheck %s --check-prefix=CHECK-RV64-ERR 
 
 // CHECK-RV64V-LABEL: @test(
 // CHECK-RV64V-NEXT:  entry:
 // CHECK-RV64V-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
 // CHECK-RV64V-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 // CHECK-RV64V-NEXT:    ret i32 [[CONV]]
 //
 
-// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x', 'V'
+// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x', 'Zve32f', 'Zve64x', 'Zve64f', 'Zve64d', 'V'
 
 int test() {
   return __builtin_rvv_vsetvli(1, 0, 0);
 }

clang/test/Preprocessor/riscv-target-features.c

 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ifdzve64d1p0 -x c -E -dM %s -o - \
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
 // CHECK-ZVE64D-EXT: __riscv_v_elen 64
 // CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64
 // CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64D-EXT: __riscv_vector 1
-// CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64D-EXT: __riscv_zve64d 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve64f 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ifzve64f1p0 -x c -E -dM %s -o - \
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
 // CHECK-ZVE64F-EXT: __riscv_v_elen 64
 // CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32
 // CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64F-EXT: __riscv_vector 1
-// CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE64F-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64F-EXT: __riscv_zve64f 1000000{{$}}
-// CHECK-ZVE64F-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izve64x1p0 -x c -E -dM %s -o - \
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
 // CHECK-ZVE64X-EXT: __riscv_v_elen 64
 // CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0
 // CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64X-EXT: __riscv_vector 1
-// CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64X-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ifzve32f1p0 -x c -E -dM %s -o - \
 // RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
 // CHECK-ZVE32F-EXT: __riscv_v_elen 32
 // CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32
 // CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32F-EXT: __riscv_vector 1
 // CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE32F-EXT: __riscv_zve32x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izve32x1p0 -x c -E -dM %s -o - \
 // RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
 // CHECK-ZVE32X-EXT: __riscv_v_elen 32
 // CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}}

clang/utils/TableGen/RISCVVEmitter.cpp

 //===- RISCVVEmitter.cpp - Generate riscv_vector.h for use with clang -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void RVVEmitter::createBuiltins(raw_ostream &OS) {
   std::vector<std::unique_ptr<RVVIntrinsic>> Defs;
   createRVVIntrinsics(Defs);
 
   // Map to keep track of which builtin names have already been emitted.
   StringMap<RVVIntrinsic *> BuiltinMap;
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-        "ATTRS, \"zve32x|v\")\n";
+        "ATTRS, \"zve32x|zve32f|zve64x|zve64f|zve64d|v\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
     auto P =
         BuiltinMap.insert(std::make_pair(Def->getBuiltinName(), Def.get()));
     if (!P.second) {
       // Verify that this would have produced the same builtin definition.
       if (P.first->second->hasAutoDef() != Def->hasAutoDef()) {
         PrintFatalError("Builtin with same name has different hasAutoDef");

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISCV Arch String Parser --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 
 Error RISCVISAInfo::checkDependency() {
   bool IsRv32 = XLen == 32;
   bool HasE = Exts.count("e") != 0;
   bool HasD = Exts.count("d") != 0;
   bool HasF = Exts.count("f") != 0;
   bool HasZve32x = Exts.count("zve32x") != 0;
   bool HasZve32f = Exts.count("zve32f") != 0;
+  bool HasZve64x = Exts.count("zve64x") != 0;
+  bool HasZve64f = Exts.count("zve64f") != 0;
   bool HasZve64d = Exts.count("zve64d") != 0;
+  bool HasZve = HasZve32x || HasZve32f || HasZve64x || HasZve64f || HasZve64d;
+  bool HasZvef = HasZve32f || HasZve64f || HasZve64d;
   bool HasV = Exts.count("v") != 0;
-  bool HasVector = HasZve32x || HasV;
+  bool HasVector = HasZve || HasV;
   bool HasZvl = MinVLen != 0;
 
   if (HasE && !IsRv32)
     return createStringError(
         errc::invalid_argument,
         "standard user-level extension 'e' requires 'rv32'");
 
   // It's illegal to specify the 'd' (double-precision floating point)
   // extension without also specifying the 'f' (single precision
   // floating-point) extension.
   // TODO: This has been removed in later specs, which specify that D implies F
   if (HasD && !HasF)
     return createStringError(errc::invalid_argument,
                              "d requires f extension to also be specified");
 
   // FIXME: Consider Zfinx in the future
-  if (HasZve32f && !HasF)
+  if (HasZvef && !HasF)
     return createStringError(
         errc::invalid_argument,
-        "zve32f requires f extension to also be specified");
+        "zve*f requires f extension to also be specified");
 
   // FIXME: Consider Zdinx in the future
   if (HasZve64d && !HasD)
     return createStringError(
         errc::invalid_argument,
         "zve64d requires d extension to also be specified");
 
   if (HasZvl && !HasVector)
     return createStringError(
         errc::invalid_argument,
         "zvl*b requires v or zve* extension to also be specified");
 
+  // Could not implement multiple Zve* extensions.
+  if (HasZve32x + HasZve32f + HasZve64x + HasZve64f + HasZve64d > 1)
+    return createStringError(
+        errc::invalid_argument,
+        "It is illegal to specify multiple zve* extensions");
+
   // Could not implement Zve* extension and the V extension at the same time.
-  if (HasZve32x && HasV)
+  if (HasZve && HasV)
     return createStringError(
         errc::invalid_argument,
         "It is illegal to specify the v extension with zve* extensions");
 
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   return Error::success();
 }
 
 static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
-static const char *ImpliedExtsZve64d[] = {"zve64f"};
-static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
-static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
-static const char *ImpliedExtsZve32f[] = {"zve32x"};
+static const char *ImpliedExtsZve64d[] = {"zvl64b"};
+static const char *ImpliedExtsZve64f[] = {"zvl64b"};
+static const char *ImpliedExtsZve64x[] = {"zvl64b"};
+static const char *ImpliedExtsZve32f[] = {"zvl32b"};
 static const char *ImpliedExtsZve32x[] = {"zvl32b"};
 static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
 static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
 static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
 static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"};
 static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"};
 static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"};
 static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};

llvm/lib/Target/RISCV/RISCV.td

: SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
                        "'Zve32x' (Vector Extensions for Embedded Processors "
                        "with maximal 32 EEW)",
                        [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve32f
     : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
                        "'Zve32f' (Vector Extensions for Embedded Processors "
                        "with maximal 32 EEW and F extension)",
-                       [FeatureStdExtZve32x]>;
+                       [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve64x
     : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
                        "'Zve64x' (Vector Extensions for Embedded Processors "
-                       "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+                       "with maximal 64 EEW)", [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64f
     : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
                        "'Zve64f' (Vector Extensions for Embedded Processors "
                        "with maximal 64 EEW and F extension)",
-                       [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+                       [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64d
     : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
                        "'Zve64d' (Vector Extensions for Embedded Processors "
                        "with maximal 64 EEW, F and D extension)",
-                       [FeatureStdExtZve64f]>;
+                       [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtV
     : SubtargetFeature<"v", "HasStdExtV", "true",
                        "'V' (Vector Extension for Application Processors)",
                        [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>;
 
 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
       AssemblerPredicate<

llvm/lib/Target/RISCV/RISCVSubtarget.h

 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
   bool isRegisterReservedByUser(Register i) const {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasZve() const {
+    return HasStdExtZve32x || HasStdExtZve32f || HasStdExtZve64x ||
+           HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZve64() const {
+    return HasStdExtZve64x || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZvef() const {
+    return HasStdExtZve32f || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZved() const { return HasStdExtZve64d; }
+  bool hasVInstructions() const { return HasStdExtV || hasZve(); }
+  bool hasVInstructionsI64() const { return HasStdExtV || hasZve64(); }
   bool hasVInstructionsF16() const {
-    return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh;
+    return HasStdExtZfh && (HasStdExtV || hasZvef());
   }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const {
-    return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+    return HasStdExtV || (hasZvef() && HasStdExtF);
   }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const {
-    return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+    return HasStdExtV || (hasZved() && HasStdExtD);
   }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
   unsigned getMaxInterleaveFactor() const {
     return hasVInstructions() ? MaxInterleaveFactor : 1;
   }
 
 protected:

llvm/test/MC/RISCV/attribute-arch.s

 
 .attribute arch, "rv32ivzvl65536b"
 # CHECK: attribute      5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32izve32x"
 # CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32ifzve32f"
-# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zvl32b1p0"
 
 .attribute arch, "rv32izve64x"
-# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifzve64f"
-# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_zve64f1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifdzve64d"
-# CHECK: attribute      5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_d2p0_zve64d1p0_zvl32b1p0_zvl64b1p0"
 
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute      5, "rv32i2p0_zba1p0"
 
 .attribute arch, "rv32izbb1p0"
 # CHECK: attribute      5, "rv32i2p0_zbb1p0"