[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

[craig.topper]

Summary

Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.

[liaolucy]

llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp

11

W0 is typo?

95

select_cc also generates beq, I'm not sure should handle it?

[craig.topper]

llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp

11

Copy and pasted from AArch64. I'll fix. Thanks

95

This pass runs after register allocation so select_cc will already have been expanded into control flow before we here. I think all the test changes started as select_cc.

[craig.topper]

Fix copy/paste mistake

[asb]

LGTM. It feels like this could perhaps be made target-independent with some additional hooks - a companion to or modification to isConstantPhysReg that indicates what the constant value is, and using analyzeBranchPredicate. Though extending it in some of the ways suggested in the TODOs would be more difficult, and as the pass itself as quite simple, the code added in terms of target hooks / interface modifications could quickly become larger than the pass itself.

[craig.topper]

In D118160#3292913, @asb wrote:

LGTM. It feels like this could perhaps be made target-independent with some additional hooks - a companion to or modification to isConstantPhysReg that indicates what the constant value is, and using analyzeBranchPredicate. Though extending it in some of the ways suggested in the TODOs would be more difficult, and as the pass itself as quite simple, the code added in terms of target hooks / interface modifications could quickly become larger than the pass itself.

I might look at this in the future. I started with the simpler version AArch64 started with so I didn't look as much at its current version which handles multiple branches, and constants. As noted in the TODOs, constants for RISCV will be harder. If the constant doesn't fit in an ADDI we might get luck and they'll be CSEd together. Then we would just need to check for register equality/inequality.

llvm/lib/Target/RISCV/CMakeLists.txt

add_llvm_target(RISCVCodeGen
   RISCVInsertVSETVLI.cpp
   RISCVInstrInfo.cpp
   RISCVInstructionSelector.cpp
   RISCVISelDAGToDAG.cpp
   RISCVISelLowering.cpp
   RISCVLegalizerInfo.cpp
   RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
+  RISCVRedundantCopyElimination.cpp
   RISCVRegisterBankInfo.cpp
   RISCVRegisterInfo.cpp
   RISCVSExtWRemoval.cpp
   RISCVSubtarget.cpp
   RISCVTargetMachine.cpp
   RISCVTargetObjectFile.cpp
   RISCVTargetTransformInfo.cpp
 

llvm/lib/Target/RISCV/RISCV.h

 //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 void initializeRISCVExpandPseudoPass(PassRegistry &);
 
 FunctionPass *createRISCVExpandAtomicPseudoPass();
 void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
 
 FunctionPass *createRISCVInsertVSETVLIPass();
 void initializeRISCVInsertVSETVLIPass(PassRegistry &);
 
+FunctionPass *createRISCVRedundantCopyEliminationPass();
+void initializeRISCVRedundantCopyEliminationPass(PassRegistry&);
+
 InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
                                                     RISCVSubtarget &,
                                                     RISCVRegisterBankInfo &);
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp

+//=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISCV ------=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass removes unnecessary zero copies in BBs that are targets of
+// beqz/bnez instructions. For instance, the copy instruction in the code below
+// can be removed because the beqz jumps to BB#2 when W0 is zero.
+//  BB#1:
+//    beqz %A0, <BB#2>
+//  BB#2:
+//    %A0 = COPY %X0
+// This pass should be run after register allocation.
+//
+// This pass is based on the earliest versions of
+// AArch64RedundantCopyElimination.
+//
+// FIXME: Support compares with constants other than zero? This is harder to
+// do on RISC-V since branches can't have immediates.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-copyelim"
+
+STATISTIC(NumCopiesRemoved, "Number of copies removed.");
+
+namespace {
+class RISCVRedundantCopyElimination : public MachineFunctionPass {
+  const MachineRegisterInfo *MRI;
+  const TargetRegisterInfo *TRI;
+
+public:
+  static char ID;
+  RISCVRedundantCopyElimination() : MachineFunctionPass(ID) {
+    initializeRISCVRedundantCopyEliminationPass(
+        *PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::NoVRegs);
+  }
+
+  StringRef getPassName() const override {
+    return "RISCV Redundant Copy Elimination";
+  }
+
+private:
+  bool optimizeBlock(MachineBasicBlock &MBB);
+};
+
+} // end anonymous namespace
+
+char RISCVRedundantCopyElimination::ID = 0;
+
+INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
+                "RISCV redundant copy elimination pass", false, false)
+
+static bool guaranteesZeroRegInBlock(const MachineInstr &MI,
+                                     const MachineBasicBlock &MBB) {
+  unsigned Opc = MI.getOpcode();
+  if (Opc == RISCV::BEQ && MI.getOperand(1).getReg() == RISCV::X0 &&
+      &MBB == MI.getOperand(2).getMBB())
+    return true;
+  if (Opc == RISCV::BNE && MI.getOperand(1).getReg() == RISCV::X0 &&
+      &MBB != MI.getOperand(2).getMBB())
+    return true;
+
+  return false;
+}
+
+bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
+  // Check if the current basic block has a single predecessor.
+  if (MBB.pred_size() != 1)
+    return false;
+
+  // Check if the predecessor has two successors, implying the block ends in a
+  // conditional branch.
+  MachineBasicBlock *PredMBB = *MBB.pred_begin();
+  if (PredMBB->succ_size() != 2)
+    return false;
+
+  MachineBasicBlock::iterator CondBr = PredMBB->getLastNonDebugInstr();
+  if (CondBr == PredMBB->end())
+    return false;
+
+  while (true) {
+    // If we run out of terminators, give up.
+    if (!CondBr->isTerminator())
+      return false;
+    // If we found a branch with X0, stop searching and try to remove copies.
+    // TODO: Handle multiple branches with different registers.
+    if (guaranteesZeroRegInBlock(*CondBr, MBB))
+      break;
+    // If we reached the beginning of the basic block, give up.
+    if (CondBr == PredMBB->begin())
+      return false;
+    --CondBr;
+  }
+
+  Register TargetReg = CondBr->getOperand(0).getReg();
+  if (!TargetReg)
+    return false;
+
+  bool Changed = false;
+  MachineBasicBlock::iterator LastChange = MBB.begin();
+  // Remove redundant Copy instructions unless TargetReg is modified.
+  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
+    MachineInstr *MI = &*I;
+    ++I;
+    if (MI->isCopy() && MI->getOperand(0).isReg() &&
+        MI->getOperand(1).isReg()) {
+      Register DefReg = MI->getOperand(0).getReg();
+      Register SrcReg = MI->getOperand(1).getReg();
+
+      if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) &&
+          TargetReg == DefReg) {
+        LLVM_DEBUG(dbgs() << "Remove redundant Copy : ");
+        LLVM_DEBUG(MI->print(dbgs()));
+
+        MI->eraseFromParent();
+        Changed = true;
+        LastChange = I;
+        ++NumCopiesRemoved;
+        continue;
+      }
+    }
+
+    if (MI->modifiesRegister(TargetReg, TRI))
+      break;
+  }
+
+  if (!Changed)
+    return false;
+
+  // Otherwise, we have to fixup the use-def chain, starting with the
+  // BEQ/BNE. Conservatively mark as much as we can live.
+  CondBr->clearRegisterKills(TargetReg, TRI);
+
+  // Add newly used reg to the block's live-in list if it isn't there already.
+  if (!MBB.isLiveIn(TargetReg))
+    MBB.addLiveIn(TargetReg);
+
+  // Clear any kills of TargetReg between CondBr and the last removed COPY.
+  for (MachineInstr &MMI : make_range(MBB.begin(), LastChange))
+    MMI.clearRegisterKills(TargetReg, TRI);
+
+  return true;
+}
+
+bool RISCVRedundantCopyElimination::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(MF.getFunction()))
+    return false;
+
+  TRI = MF.getSubtarget().getRegisterInfo();
+  MRI = &MF.getRegInfo();
+
+  bool Changed = false;
+  for (MachineBasicBlock &MBB : MF)
+    Changed |= optimizeBlock(MBB);
+
+  return Changed;
+}
+
+FunctionPass *llvm::createRISCVRedundantCopyEliminationPass() {
+  return new RISCVRedundantCopyElimination();
+}

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
+static cl::opt<bool> EnableRedundantCopyElimination(
+    "riscv-enable-copyelim",
+    cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
+    cl::Hidden);
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
   auto *PR = PassRegistry::getPassRegistry();
   initializeGlobalISel(*PR);
   initializeRISCVGatherScatterLoweringPass(*PR);
   initializeRISCVMergeBaseOffsetOptPass(*PR);
   initializeRISCVSExtWRemovalPass(*PR);
public:
   bool addLegalizeMachineIR() override;
   bool addRegBankSelect() override;
   bool addGlobalInstructionSelect() override;
   void addPreEmitPass() override;
   void addPreEmitPass2() override;
   void addPreSched2() override;
   void addMachineSSAOptimization() override;
   void addPreRegAlloc() override;
+  void addPostRegAlloc() override;
 };
 } // namespace
 
 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new RISCVPassConfig(*this, PM);
 }
 
 void RISCVPassConfig::addIRPasses() {
if (TM->getTargetTriple().getArch() == Triple::riscv64)
     addPass(createRISCVSExtWRemovalPass());
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
   if (TM->getOptLevel() != CodeGenOpt::None)
     addPass(createRISCVMergeBaseOffsetOptPass());
   addPass(createRISCVInsertVSETVLIPass());
 }
+
+void RISCVPassConfig::addPostRegAlloc() {
+  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+    addPass(createRISCVRedundantCopyEliminationPass());
+}

llvm/test/CodeGen/RISCV/double-convert.ll

; RV64I-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_d_sat(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_w_d_sat:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB3_2
-; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB3_2:
+; RV32IFD-NEXT:    beqz a0, .LBB3_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT:  .LBB3_2: # %start
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_w_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB3_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB3_2:
+; RV64IFD-NEXT:    beqz a0, .LBB3_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB3_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_d_sat(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_wu_d_sat:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB6_2
-; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB6_2:
+; RV32IFD-NEXT:    beqz a0, .LBB6_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT:  .LBB6_2: # %start
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_wu_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB6_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB6_2:
+; RV64IFD-NEXT:    beqz a0, .LBB6_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB6_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

 ; RV32IFD-NEXT:  .LBB12_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB12_7
 ; RV32IFD-NEXT:    j .LBB12_8
 ;
 ; RV64IFD-LABEL: fcvt_l_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB12_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB12_2:
+; RV64IFD-NEXT:    beqz a0, .LBB12_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB12_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -48
 ; RV32I-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 36(sp) # 4-byte Folded Spill

 ; RV32IFD-NEXT:  .LBB14_8: # %start
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB14_5
 ; RV32IFD-NEXT:    j .LBB14_6
 ;
 ; RV64IFD-LABEL: fcvt_lu_d_sat:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB14_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB14_2:
+; RV64IFD-NEXT:    beqz a0, .LBB14_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB14_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_d_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %1 = fptosi double %a to i16
   ret i16 %1
 }
 
 define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_w_s_sat_i16:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB26_2
-; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB26_2:
+; RV32IFD-NEXT:    beqz a0, .LBB26_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI26_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI26_0)(a0)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI26_1)
 ; RV32IFD-NEXT:    fld ft1, %lo(.LCPI26_1)(a0)
 ; RV32IFD-NEXT:    fmax.d ft0, fa0, ft0
 ; RV32IFD-NEXT:    fmin.d ft0, ft0, ft1
 ; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB26_2: # %start
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_w_s_sat_i16:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB26_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB26_2:
+; RV64IFD-NEXT:    beqz a0, .LBB26_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI26_0)
 ; RV64IFD-NEXT:    fld ft0, %lo(.LCPI26_0)(a0)
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI26_1)
 ; RV64IFD-NEXT:    fld ft1, %lo(.LCPI26_1)(a0)
 ; RV64IFD-NEXT:    fmax.d ft0, fa0, ft0
 ; RV64IFD-NEXT:    fmin.d ft0, ft0, ft1
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT:  .LBB26_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %1 = fptosi double %a to i8
   ret i8 %1
 }
 
 define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
 ; RV32IFD-LABEL: fcvt_w_s_sat_i8:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB30_2
-; RV32IFD-NEXT:  # %bb.1: # %start
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB30_2:
+; RV32IFD-NEXT:    beqz a0, .LBB30_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI30_0)
 ; RV32IFD-NEXT:    fld ft0, %lo(.LCPI30_0)(a0)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI30_1)
 ; RV32IFD-NEXT:    fld ft1, %lo(.LCPI30_1)(a0)
 ; RV32IFD-NEXT:    fmax.d ft0, fa0, ft0
 ; RV32IFD-NEXT:    fmin.d ft0, ft0, ft1
 ; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB30_2: # %start
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_w_s_sat_i8:
 ; RV64IFD:       # %bb.0: # %start
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB30_2
-; RV64IFD-NEXT:  # %bb.1: # %start
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB30_2:
+; RV64IFD-NEXT:    beqz a0, .LBB30_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI30_0)
 ; RV64IFD-NEXT:    fld ft0, %lo(.LCPI30_0)(a0)
 ; RV64IFD-NEXT:    lui a0, %hi(.LCPI30_1)
 ; RV64IFD-NEXT:    fld ft1, %lo(.LCPI30_1)(a0)
 ; RV64IFD-NEXT:    fmax.d ft0, fa0, ft0
 ; RV64IFD-NEXT:    fmin.d ft0, ft0, ft1
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT:  .LBB30_2: # %start
 ; RV64IFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32d | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64d | FileCheck -check-prefix=RV64IFD %s
 
 define signext i32 @test_floor_si32(double %x) {
 ; RV32IFD-LABEL: test_floor_si32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB0_2
+; RV32IFD-NEXT:    beqz a0, .LBB0_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB0_2:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rdn
+; RV32IFD-NEXT:  .LBB0_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_floor_si32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB0_2
+; RV64IFD-NEXT:    beqz a0, .LBB0_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB0_2:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rdn
+; RV64IFD-NEXT:  .LBB0_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_floor_si64:

 ; RV32IFD-NEXT:  .LBB1_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB1_7
 ; RV32IFD-NEXT:    j .LBB1_8
 ;
 ; RV64IFD-LABEL: test_floor_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB1_2
+; RV64IFD-NEXT:    beqz a0, .LBB1_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB1_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rdn
+; RV64IFD-NEXT:  .LBB1_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(double %x) {
 ; RV32IFD-LABEL: test_floor_ui32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB2_2
+; RV32IFD-NEXT:    beqz a0, .LBB2_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB2_2:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
+; RV32IFD-NEXT:  .LBB2_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_floor_ui32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB2_2
+; RV64IFD-NEXT:    beqz a0, .LBB2_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB2_2:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rdn
+; RV64IFD-NEXT:  .LBB2_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_floor_ui64:

 ; RV32IFD-NEXT:  .LBB3_8:
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB3_5
 ; RV32IFD-NEXT:    j .LBB3_6
 ;
 ; RV64IFD-LABEL: test_floor_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB3_2
+; RV64IFD-NEXT:    beqz a0, .LBB3_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB3_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rdn
+; RV64IFD-NEXT:  .LBB3_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.floor.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(double %x) {
 ; RV32IFD-LABEL: test_ceil_si32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB4_2
+; RV32IFD-NEXT:    beqz a0, .LBB4_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB4_2:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rup
+; RV32IFD-NEXT:  .LBB4_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_ceil_si32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB4_2
+; RV64IFD-NEXT:    beqz a0, .LBB4_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rup
+; RV64IFD-NEXT:  .LBB4_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_ceil_si64:

 ; RV32IFD-NEXT:  .LBB5_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB5_7
 ; RV32IFD-NEXT:    j .LBB5_8
 ;
 ; RV64IFD-LABEL: test_ceil_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB5_2
+; RV64IFD-NEXT:    beqz a0, .LBB5_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB5_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rup
+; RV64IFD-NEXT:  .LBB5_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(double %x) {
 ; RV32IFD-LABEL: test_ceil_ui32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB6_2
+; RV32IFD-NEXT:    beqz a0, .LBB6_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB6_2:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rup
+; RV32IFD-NEXT:  .LBB6_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_ceil_ui32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB6_2
+; RV64IFD-NEXT:    beqz a0, .LBB6_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB6_2:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rup
+; RV64IFD-NEXT:  .LBB6_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_ceil_ui64:

 ; RV32IFD-NEXT:  .LBB7_8:
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB7_5
 ; RV32IFD-NEXT:    j .LBB7_6
 ;
 ; RV64IFD-LABEL: test_ceil_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB7_2
+; RV64IFD-NEXT:    beqz a0, .LBB7_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB7_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rup
+; RV64IFD-NEXT:  .LBB7_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.ceil.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(double %x) {
 ; RV32IFD-LABEL: test_trunc_si32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB8_2
+; RV32IFD-NEXT:    beqz a0, .LBB8_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB8_2:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT:  .LBB8_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_trunc_si32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB8_2
+; RV64IFD-NEXT:    beqz a0, .LBB8_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB8_2:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB8_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_trunc_si64:

 ; RV32IFD-NEXT:  .LBB9_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB9_7
 ; RV32IFD-NEXT:    j .LBB9_8
 ;
 ; RV64IFD-LABEL: test_trunc_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB9_2
+; RV64IFD-NEXT:    beqz a0, .LBB9_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB9_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB9_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(double %x) {
 ; RV32IFD-LABEL: test_trunc_ui32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB10_2
+; RV32IFD-NEXT:    beqz a0, .LBB10_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB10_2:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT:  .LBB10_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_trunc_ui32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB10_2
+; RV64IFD-NEXT:    beqz a0, .LBB10_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB10_2:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB10_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_trunc_ui64:

 ; RV32IFD-NEXT:  .LBB11_8:
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB11_5
 ; RV32IFD-NEXT:    j .LBB11_6
 ;
 ; RV64IFD-LABEL: test_trunc_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB11_2
+; RV64IFD-NEXT:    beqz a0, .LBB11_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB11_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
+; RV64IFD-NEXT:  .LBB11_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.trunc.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(double %x) {
 ; RV32IFD-LABEL: test_round_si32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB12_2
+; RV32IFD-NEXT:    beqz a0, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB12_2:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rmm
+; RV32IFD-NEXT:  .LBB12_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_round_si32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB12_2
+; RV64IFD-NEXT:    beqz a0, .LBB12_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB12_2:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rmm
+; RV64IFD-NEXT:  .LBB12_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_round_si64:

 ; RV32IFD-NEXT:  .LBB13_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB13_7
 ; RV32IFD-NEXT:    j .LBB13_8
 ;
 ; RV64IFD-LABEL: test_round_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB13_2
+; RV64IFD-NEXT:    beqz a0, .LBB13_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB13_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rmm
+; RV64IFD-NEXT:  .LBB13_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(double %x) {
 ; RV32IFD-LABEL: test_round_ui32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB14_2
+; RV32IFD-NEXT:    beqz a0, .LBB14_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB14_2:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
+; RV32IFD-NEXT:  .LBB14_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_round_ui32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB14_2
+; RV64IFD-NEXT:    beqz a0, .LBB14_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB14_2:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rmm
+; RV64IFD-NEXT:  .LBB14_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_round_ui64:

 ; RV32IFD-NEXT:  .LBB15_8:
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB15_5
 ; RV32IFD-NEXT:    j .LBB15_6
 ;
 ; RV64IFD-LABEL: test_round_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB15_2
+; RV64IFD-NEXT:    beqz a0, .LBB15_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB15_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rmm
+; RV64IFD-NEXT:  .LBB15_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.round.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(double %x) {
 ; RV32IFD-LABEL: test_roundeven_si32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB16_2
+; RV32IFD-NEXT:    beqz a0, .LBB16_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB16_2:
 ; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rne
+; RV32IFD-NEXT:  .LBB16_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_roundeven_si32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB16_2
+; RV64IFD-NEXT:    beqz a0, .LBB16_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB16_2:
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rne
+; RV64IFD-NEXT:  .LBB16_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(double %x) nounwind {
 ; RV32IFD-LABEL: test_roundeven_si64:

 ; RV32IFD-NEXT:  .LBB17_12:
 ; RV32IFD-NEXT:    addi a1, a4, -1
 ; RV32IFD-NEXT:    beqz a2, .LBB17_7
 ; RV32IFD-NEXT:    j .LBB17_8
 ;
 ; RV64IFD-LABEL: test_roundeven_si64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB17_2
+; RV64IFD-NEXT:    beqz a0, .LBB17_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB17_2:
 ; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rne
+; RV64IFD-NEXT:  .LBB17_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(double %x) {
 ; RV32IFD-LABEL: test_roundeven_ui32:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    bnez a0, .LBB18_2
+; RV32IFD-NEXT:    beqz a0, .LBB18_2
 ; RV32IFD-NEXT:  # %bb.1:
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB18_2:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rne
+; RV32IFD-NEXT:  .LBB18_2:
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: test_roundeven_ui32:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB18_2
+; RV64IFD-NEXT:    beqz a0, .LBB18_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB18_2:
 ; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rne
+; RV64IFD-NEXT:  .LBB18_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(double %x) nounwind {
 ; RV32IFD-LABEL: test_roundeven_ui64:

 ; RV32IFD-NEXT:  .LBB19_8:
 ; RV32IFD-NEXT:    li a1, 0
 ; RV32IFD-NEXT:    beqz a4, .LBB19_5
 ; RV32IFD-NEXT:    j .LBB19_6
 ;
 ; RV64IFD-LABEL: test_roundeven_ui64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    bnez a0, .LBB19_2
+; RV64IFD-NEXT:    beqz a0, .LBB19_2
 ; RV64IFD-NEXT:  # %bb.1:
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB19_2:
 ; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rne
+; RV64IFD-NEXT:  .LBB19_2:
 ; RV64IFD-NEXT:    ret
   %a = call double @llvm.roundeven.f64(double %x)
   %b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
   ret i64 %b
 }
 
 declare double @llvm.floor.f64(double)
 declare double @llvm.ceil.f64(double)
 declare double @llvm.trunc.f64(double)
 declare double @llvm.round.f64(double)
 declare double @llvm.roundeven.f64(double)
 declare i32 @llvm.fptosi.sat.i32.f64(double)
 declare i64 @llvm.fptosi.sat.i64.f64(double)
 declare i32 @llvm.fptoui.sat.i32.f64(double)
 declare i64 @llvm.fptoui.sat.i64.f64(double)

llvm/test/CodeGen/RISCV/float-convert.ll

; RV64I-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_s_sat(float %a) nounwind {
 ; RV32IF-LABEL: fcvt_w_s_sat:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB1_2
-; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB1_2:
+; RV32IF-NEXT:    beqz a0, .LBB1_2
+; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
+; RV32IF-NEXT:  .LBB1_2: # %start
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_w_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB1_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB1_2:
+; RV64IF-NEXT:    beqz a0, .LBB1_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB1_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_s_sat(float %a) nounwind {
 ; RV32IF-LABEL: fcvt_wu_s_sat:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB4_2
-; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB4_2:
+; RV32IF-NEXT:    beqz a0, .LBB4_2
+; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT:  .LBB4_2: # %start
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB4_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB4_2:
+; RV64IF-NEXT:    beqz a0, .LBB4_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB4_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:  .LBB12_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB12_7
 ; RV32IF-NEXT:    j .LBB12_8
 ;
 ; RV64IF-LABEL: fcvt_l_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB12_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB12_2:
+; RV64IF-NEXT:    beqz a0, .LBB12_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB12_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

 ; RV32IF-NEXT:  .LBB14_8: # %start
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB14_5
 ; RV32IF-NEXT:    j .LBB14_6
 ;
 ; RV64IF-LABEL: fcvt_lu_s_sat:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB14_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB14_2:
+; RV64IF-NEXT:    beqz a0, .LBB14_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB14_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_s_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %1 = fptosi float %a to i16
   ret i16 %1
 }
 
 define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
 ; RV32IF-LABEL: fcvt_w_s_sat_i16:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB24_2
-; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB24_2:
+; RV32IF-NEXT:    beqz a0, .LBB24_2
+; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI24_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI24_0)(a0)
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI24_1)
 ; RV32IF-NEXT:    flw ft1, %lo(.LCPI24_1)(a0)
 ; RV32IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV32IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT:  .LBB24_2: # %start
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_w_s_sat_i16:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB24_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB24_2:
+; RV64IF-NEXT:    beqz a0, .LBB24_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI24_0)
 ; RV64IF-NEXT:    flw ft0, %lo(.LCPI24_0)(a0)
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI24_1)
 ; RV64IF-NEXT:    flw ft1, %lo(.LCPI24_1)(a0)
 ; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT:  .LBB24_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %1 = fptosi float %a to i8
   ret i8 %1
 }
 
 define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
 ; RV32IF-LABEL: fcvt_w_s_sat_i8:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB28_2
-; RV32IF-NEXT:  # %bb.1: # %start
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB28_2:
+; RV32IF-NEXT:    beqz a0, .LBB28_2
+; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI28_0)
 ; RV32IF-NEXT:    flw ft0, %lo(.LCPI28_0)(a0)
 ; RV32IF-NEXT:    lui a0, %hi(.LCPI28_1)
 ; RV32IF-NEXT:    flw ft1, %lo(.LCPI28_1)(a0)
 ; RV32IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV32IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT:  .LBB28_2: # %start
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_w_s_sat_i8:
 ; RV64IF:       # %bb.0: # %start
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB28_2
-; RV64IF-NEXT:  # %bb.1: # %start
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB28_2:
+; RV64IF-NEXT:    beqz a0, .LBB28_2
+; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI28_0)
 ; RV64IF-NEXT:    flw ft0, %lo(.LCPI28_0)(a0)
 ; RV64IF-NEXT:    lui a0, %hi(.LCPI28_1)
 ; RV64IF-NEXT:    flw ft1, %lo(.LCPI28_1)(a0)
 ; RV64IF-NEXT:    fmax.s ft0, fa0, ft0
 ; RV64IF-NEXT:    fmin.s ft0, ft0, ft1
 ; RV64IF-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT:  .LBB28_2: # %start
 ; RV64IF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
 
 define signext i32 @test_floor_si32(float %x) {
 ; RV32IF-LABEL: test_floor_si32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB0_2
+; RV32IF-NEXT:    beqz a0, .LBB0_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB0_2:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rdn
+; RV32IF-NEXT:  .LBB0_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_si32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB0_2
+; RV64IF-NEXT:    beqz a0, .LBB0_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB0_2:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rdn
+; RV64IF-NEXT:  .LBB0_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_si64:

 ; RV32IF-NEXT:  .LBB1_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB1_7
 ; RV32IF-NEXT:    j .LBB1_8
 ;
 ; RV64IF-LABEL: test_floor_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB1_2
+; RV64IF-NEXT:    beqz a0, .LBB1_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
+; RV64IF-NEXT:  .LBB1_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(float %x) {
 ; RV32IF-LABEL: test_floor_ui32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB2_2
+; RV32IF-NEXT:    beqz a0, .LBB2_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rdn
+; RV32IF-NEXT:  .LBB2_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB2_2
+; RV64IF-NEXT:    beqz a0, .LBB2_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB2_2:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rdn
+; RV64IF-NEXT:  .LBB2_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:

 ; RV32IF-NEXT:  .LBB3_8:
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB3_5
 ; RV32IF-NEXT:    j .LBB3_6
 ;
 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB3_2
+; RV64IF-NEXT:    beqz a0, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
+; RV64IF-NEXT:  .LBB3_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.floor.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(float %x) {
 ; RV32IF-LABEL: test_ceil_si32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB4_2
+; RV32IF-NEXT:    beqz a0, .LBB4_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rup
+; RV32IF-NEXT:  .LBB4_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_si32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB4_2
+; RV64IF-NEXT:    beqz a0, .LBB4_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB4_2:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rup
+; RV64IF-NEXT:  .LBB4_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_si64:

 ; RV32IF-NEXT:  .LBB5_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB5_7
 ; RV32IF-NEXT:    j .LBB5_8
 ;
 ; RV64IF-LABEL: test_ceil_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB5_2
+; RV64IF-NEXT:    beqz a0, .LBB5_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
+; RV64IF-NEXT:  .LBB5_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(float %x) {
 ; RV32IF-LABEL: test_ceil_ui32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB6_2
+; RV32IF-NEXT:    beqz a0, .LBB6_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB6_2:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rup
+; RV32IF-NEXT:  .LBB6_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB6_2
+; RV64IF-NEXT:    beqz a0, .LBB6_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB6_2:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rup
+; RV64IF-NEXT:  .LBB6_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:

 ; RV32IF-NEXT:  .LBB7_8:
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB7_5
 ; RV32IF-NEXT:    j .LBB7_6
 ;
 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB7_2
+; RV64IF-NEXT:    beqz a0, .LBB7_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
+; RV64IF-NEXT:  .LBB7_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.ceil.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(float %x) {
 ; RV32IF-LABEL: test_trunc_si32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB8_2
+; RV32IF-NEXT:    beqz a0, .LBB8_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB8_2:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rtz
+; RV32IF-NEXT:  .LBB8_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_si32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB8_2
+; RV64IF-NEXT:    beqz a0, .LBB8_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB8_2:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB8_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_si64:

 ; RV32IF-NEXT:  .LBB9_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB9_7
 ; RV32IF-NEXT:    j .LBB9_8
 ;
 ; RV64IF-LABEL: test_trunc_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB9_2
+; RV64IF-NEXT:    beqz a0, .LBB9_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB9_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(float %x) {
 ; RV32IF-LABEL: test_trunc_ui32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB10_2
+; RV32IF-NEXT:    beqz a0, .LBB10_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB10_2:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT:  .LBB10_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB10_2
+; RV64IF-NEXT:    beqz a0, .LBB10_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB10_2:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB10_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:

 ; RV32IF-NEXT:  .LBB11_8:
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB11_5
 ; RV32IF-NEXT:    j .LBB11_6
 ;
 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB11_2
+; RV64IF-NEXT:    beqz a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
+; RV64IF-NEXT:  .LBB11_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.trunc.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(float %x) {
 ; RV32IF-LABEL: test_round_si32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB12_2
+; RV32IF-NEXT:    beqz a0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB12_2:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rmm
+; RV32IF-NEXT:  .LBB12_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_si32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB12_2
+; RV64IF-NEXT:    beqz a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB12_2:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rmm
+; RV64IF-NEXT:  .LBB12_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_si64:

 ; RV32IF-NEXT:  .LBB13_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB13_7
 ; RV32IF-NEXT:    j .LBB13_8
 ;
 ; RV64IF-LABEL: test_round_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB13_2
+; RV64IF-NEXT:    beqz a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
+; RV64IF-NEXT:  .LBB13_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(float %x) {
 ; RV32IF-LABEL: test_round_ui32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB14_2
+; RV32IF-NEXT:    beqz a0, .LBB14_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB14_2:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rmm
+; RV32IF-NEXT:  .LBB14_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB14_2
+; RV64IF-NEXT:    beqz a0, .LBB14_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB14_2:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rmm
+; RV64IF-NEXT:  .LBB14_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:

 ; RV32IF-NEXT:  .LBB15_8:
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB15_5
 ; RV32IF-NEXT:    j .LBB15_6
 ;
 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB15_2
+; RV64IF-NEXT:    beqz a0, .LBB15_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB15_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
+; RV64IF-NEXT:  .LBB15_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.round.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(float %x) {
 ; RV32IF-LABEL: test_roundeven_si32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB16_2
+; RV32IF-NEXT:    beqz a0, .LBB16_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB16_2:
 ; RV32IF-NEXT:    fcvt.w.s a0, fa0, rne
+; RV32IF-NEXT:  .LBB16_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_si32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB16_2
+; RV64IF-NEXT:    beqz a0, .LBB16_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB16_2:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rne
+; RV64IF-NEXT:  .LBB16_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_si64:

 ; RV32IF-NEXT:  .LBB17_12:
 ; RV32IF-NEXT:    addi a1, a4, -1
 ; RV32IF-NEXT:    beqz a2, .LBB17_7
 ; RV32IF-NEXT:    j .LBB17_8
 ;
 ; RV64IF-LABEL: test_roundeven_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB17_2
+; RV64IF-NEXT:    beqz a0, .LBB17_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB17_2:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
+; RV64IF-NEXT:  .LBB17_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(float %x) {
 ; RV32IF-LABEL: test_roundeven_ui32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    bnez a0, .LBB18_2
+; RV32IF-NEXT:    beqz a0, .LBB18_2
 ; RV32IF-NEXT:  # %bb.1:
-; RV32IF-NEXT:    li a0, 0
-; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB18_2:
 ; RV32IF-NEXT:    fcvt.wu.s a0, fa0, rne
+; RV32IF-NEXT:  .LBB18_2:
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB18_2
+; RV64IF-NEXT:    beqz a0, .LBB18_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB18_2:
 ; RV64IF-NEXT:    fcvt.wu.s a0, fa0, rne
+; RV64IF-NEXT:  .LBB18_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:

 ; RV32IF-NEXT:  .LBB19_8:
 ; RV32IF-NEXT:    li a1, 0
 ; RV32IF-NEXT:    beqz a4, .LBB19_5
 ; RV32IF-NEXT:    j .LBB19_6
 ;
 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    bnez a0, .LBB19_2
+; RV64IF-NEXT:    beqz a0, .LBB19_2
 ; RV64IF-NEXT:  # %bb.1:
-; RV64IF-NEXT:    li a0, 0
-; RV64IF-NEXT:    ret
-; RV64IF-NEXT:  .LBB19_2:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
+; RV64IF-NEXT:  .LBB19_2:
 ; RV64IF-NEXT:    ret
   %a = call float @llvm.roundeven.f32(float %x)
   %b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
   ret i64 %b
 }
 
 declare float @llvm.floor.f32(float)
 declare float @llvm.ceil.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.round.f32(float)
 declare float @llvm.roundeven.f32(float)
 declare i32 @llvm.fptosi.sat.i32.f32(float)
 declare i64 @llvm.fptosi.sat.i64.f32(float)
 declare i32 @llvm.fptoui.sat.i32.f32(float)
 declare i64 @llvm.fptoui.sat.i64.f32(float)

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IFD-LABEL: stest_f64i32:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft0
-; RV32IFD-NEXT:    bnez a0, .LBB0_2
-; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    addi sp, sp, 16
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB0_2:
+; RV32IFD-NEXT:    beqz a0, .LBB0_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB0_2: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: stest_f64i32:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
 ; RV64IFD-NEXT:    lui a1, 524288

 ; RV32IFD-LABEL: ustest_f64i32:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft0
-; RV32IFD-NEXT:    bnez a0, .LBB2_2
-; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    addi sp, sp, 16
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB2_2:
+; RV32IFD-NEXT:    beqz a0, .LBB2_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB2_2: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: ustest_f64i32:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
 ; RV64IFD-NEXT:    li a1, -1
entry:
   ret i32 %conv6
 }
 
 define i32 @stest_f32i32(float %x) {
 ; RV32-LABEL: stest_f32i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    fmv.w.x ft0, a0
 ; RV32-NEXT:    feq.s a0, ft0, ft0
-; RV32-NEXT:    bnez a0, .LBB3_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB3_2:
+; RV32-NEXT:    beqz a0, .LBB3_2
+; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32-NEXT:  .LBB3_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f32i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64-NEXT:    lui a1, 524288
 ; RV64-NEXT:    addiw a2, a1, -1
entry:
   ret i32 %conv6
 }
 
 define i32 @ustest_f32i32(float %x) {
 ; RV32-LABEL: ustest_f32i32:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    fmv.w.x ft0, a0
 ; RV32-NEXT:    feq.s a0, ft0, ft0
-; RV32-NEXT:    bnez a0, .LBB5_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB5_2:
+; RV32-NEXT:    beqz a0, .LBB5_2
+; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT:  .LBB5_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i32:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64-NEXT:    li a1, -1
 ; RV64-NEXT:    srli a1, a1, 32

 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
 ;
 ; RV64IFD-LABEL: stest_f64i64:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    feq.d a0, ft0, ft0
-; RV64IFD-NEXT:    bnez a0, .LBB18_2
-; RV64IFD-NEXT:  # %bb.1: # %entry
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB18_2:
+; RV64IFD-NEXT:    beqz a0, .LBB18_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT:  .LBB18_2: # %entry
 ; RV64IFD-NEXT:    ret
 entry:
   %conv = fptosi double %x to i128
   %0 = icmp slt i128 %conv, 9223372036854775807
   %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807
   %1 = icmp sgt i128 %spec.store.select, -9223372036854775808
   %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808
   %conv6 = trunc i128 %spec.store.select7 to i64

 ; RV32-NEXT:    or a1, a1, a0
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    beqz a1, .LBB19_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:  .LBB19_5: # %entry
 ; RV32-NEXT:    bnez a0, .LBB19_7
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    j .LBB19_8
 ; RV32-NEXT:  .LBB19_7:
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
 ; RV32-NEXT:  .LBB19_8: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32

 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    beqz a4, .LBB20_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:  .LBB20_5: # %entry
 ; RV32-NEXT:    bnez a1, .LBB20_9
 ; RV32-NEXT:  # %bb.6: # %entry
 ; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    li a3, 1
 ; RV32-NEXT:    bnez a2, .LBB20_10
 ; RV32-NEXT:  .LBB20_7:
 ; RV32-NEXT:    snez a4, a3
 ; RV32-NEXT:    bnez a1, .LBB20_11
 ; RV32-NEXT:  .LBB20_8:
 ; RV32-NEXT:    snez a5, a0

 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f32i64:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    feq.s a0, ft0, ft0
-; RV64-NEXT:    bnez a0, .LBB21_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    li a0, 0
-; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB21_2:
+; RV64-NEXT:    beqz a0, .LBB21_2
+; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64-NEXT:  .LBB21_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %conv = fptosi float %x to i128
   %0 = icmp slt i128 %conv, 9223372036854775807
   %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807
   %1 = icmp sgt i128 %spec.store.select, -9223372036854775808
   %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808
   %conv6 = trunc i128 %spec.store.select7 to i64

 ; RV32-NEXT:    or a1, a1, a0
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    beqz a1, .LBB22_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:  .LBB22_5: # %entry
 ; RV32-NEXT:    bnez a0, .LBB22_7
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    j .LBB22_8
 ; RV32-NEXT:  .LBB22_7:
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
 ; RV32-NEXT:  .LBB22_8: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32

 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    beqz a4, .LBB23_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:  .LBB23_5: # %entry
 ; RV32-NEXT:    bnez a1, .LBB23_9
 ; RV32-NEXT:  # %bb.6: # %entry
 ; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    li a3, 1
 ; RV32-NEXT:    bnez a2, .LBB23_10
 ; RV32-NEXT:  .LBB23_7:
 ; RV32-NEXT:    snez a4, a3
 ; RV32-NEXT:    bnez a1, .LBB23_11
 ; RV32-NEXT:  .LBB23_8:
 ; RV32-NEXT:    snez a5, a0

 ; RV32-NEXT:    or a1, a1, a0
 ; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    beqz a1, .LBB25_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:  .LBB25_5: # %entry
 ; RV32-NEXT:    bnez a0, .LBB25_7
 ; RV32-NEXT:  # %bb.6: # %entry
-; RV32-NEXT:    li a0, 0
 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    j .LBB25_8
 ; RV32-NEXT:  .LBB25_7:
 ; RV32-NEXT:    lw a1, 12(sp)
 ; RV32-NEXT:    lw a0, 8(sp)
 ; RV32-NEXT:  .LBB25_8: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32

 ; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    beqz a4, .LBB26_5
 ; RV32-NEXT:  # %bb.4: # %entry
 ; RV32-NEXT:    mv a1, a0
 ; RV32-NEXT:  .LBB26_5: # %entry
 ; RV32-NEXT:    bnez a1, .LBB26_9
 ; RV32-NEXT:  # %bb.6: # %entry
 ; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    li a1, 0
 ; RV32-NEXT:    li a2, 0
 ; RV32-NEXT:    li a3, 1
 ; RV32-NEXT:    bnez a2, .LBB26_10
 ; RV32-NEXT:  .LBB26_7:
 ; RV32-NEXT:    snez a4, a3
 ; RV32-NEXT:    bnez a1, .LBB26_11
 ; RV32-NEXT:  .LBB26_8:
 ; RV32-NEXT:    snez a5, a0

 ; RV32IFD-LABEL: stest_f64i32_mm:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft0
-; RV32IFD-NEXT:    bnez a0, .LBB27_2
-; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    addi sp, sp, 16
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB27_2:
+; RV32IFD-NEXT:    beqz a0, .LBB27_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB27_2: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: stest_f64i32_mm:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
 ; RV64IFD-NEXT:    lui a1, 524288

 ; RV32IFD-LABEL: ustest_f64i32_mm:
 ; RV32IFD:       # %bb.0: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    .cfi_def_cfa_offset 16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft0
-; RV32IFD-NEXT:    bnez a0, .LBB29_2
-; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    li a0, 0
-; RV32IFD-NEXT:    addi sp, sp, 16
-; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB29_2:
+; RV32IFD-NEXT:    beqz a0, .LBB29_2
+; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT:  .LBB29_2: # %entry
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: ustest_f64i32_mm:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
 ; RV64IFD-NEXT:    li a1, -1
entry:
   ret i32 %conv6
 }
 
 define i32 @stest_f32i32_mm(float %x) {
 ; RV32-LABEL: stest_f32i32_mm:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    fmv.w.x ft0, a0
 ; RV32-NEXT:    feq.s a0, ft0, ft0
-; RV32-NEXT:    bnez a0, .LBB30_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB30_2:
+; RV32-NEXT:    beqz a0, .LBB30_2
+; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32-NEXT:  .LBB30_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stest_f32i32_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64-NEXT:    lui a1, 524288
 ; RV64-NEXT:    addiw a2, a1, -1
entry:
   ret i32 %conv6
 }
 
 define i32 @ustest_f32i32_mm(float %x) {
 ; RV32-LABEL: ustest_f32i32_mm:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    fmv.w.x ft0, a0
 ; RV32-NEXT:    feq.s a0, ft0, ft0
-; RV32-NEXT:    bnez a0, .LBB32_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    li a0, 0
-; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB32_2:
+; RV32-NEXT:    beqz a0, .LBB32_2
+; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT:  .LBB32_2: # %entry
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: ustest_f32i32_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
 ; RV64-NEXT:    li a1, -1
 ; RV64-NEXT:    srli a1, a1, 32

 ; RV64IF-NEXT:    mv a0, a4
 ; RV64IF-NEXT:    bne a1, a2, .LBB45_8
 ; RV64IF-NEXT:    j .LBB45_9
 ;
 ; RV64IFD-LABEL: stest_f64i64_mm:
 ; RV64IFD:       # %bb.0: # %entry
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    feq.d a0, ft0, ft0
-; RV64IFD-NEXT:    bnez a0, .LBB45_2
-; RV64IFD-NEXT:  # %bb.1: # %entry
-; RV64IFD-NEXT:    li a0, 0
-; RV64IFD-NEXT:    ret
-; RV64IFD-NEXT:  .LBB45_2:
+; RV64IFD-NEXT:    beqz a0, .LBB45_2
+; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT:  .LBB45_2: # %entry
 ; RV64IFD-NEXT:    ret
 entry:
   %conv = fptosi double %x to i128
   %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
   %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
   %conv6 = trunc i128 %spec.store.select7 to i64
   ret i64 %conv6
 }

 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:    bne a6, a2, .LBB48_17
 ; RV32-NEXT:    j .LBB48_18
 ;
 ; RV64-LABEL: stest_f32i64_mm:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    fmv.w.x ft0, a0
 ; RV64-NEXT:    feq.s a0, ft0, ft0
-; RV64-NEXT:    bnez a0, .LBB48_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    li a0, 0
-; RV64-NEXT:    ret
-; RV64-NEXT:  .LBB48_2:
+; RV64-NEXT:    beqz a0, .LBB48_2
+; RV64-NEXT:  # %bb.1:
 ; RV64-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64-NEXT:  .LBB48_2: # %entry
 ; RV64-NEXT:    ret
 entry:
   %conv = fptosi float %x to i128
   %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)
   %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)
   %conv6 = trunc i128 %spec.store.select7 to i64
   ret i64 %conv6
 }

llvm/test/CodeGen/RISCV/half-convert.ll

; RV64I-NEXT:    ret
   ret i16 %1
 }
 
 define i16 @fcvt_si_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_si_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IZFH-NEXT:    bnez a0, .LBB1_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB1_2:
+; RV32IZFH-NEXT:    beqz a0, .LBB1_2
+; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV32IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
 ; RV32IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT:  .LBB1_2: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_si_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IZFH-NEXT:    bnez a0, .LBB1_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB1_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB1_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV64IZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
 ; RV64IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT:  .LBB1_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_si_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT:    bnez a0, .LBB1_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB1_2:
+; RV32IDZFH-NEXT:    beqz a0, .LBB1_2
+; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV32IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
 ; RV32IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT:  .LBB1_2: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_si_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT:    bnez a0, .LBB1_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB1_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB1_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI1_0)(a0)
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV64IDZFH-NEXT:    flw ft2, %lo(.LCPI1_1)(a0)
 ; RV64IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT:  .LBB1_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_si_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB5_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB5_2:
+; RV32IZFH-NEXT:    beqz a0, .LBB5_2
+; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT:  .LBB5_2: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_w_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB5_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB5_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB5_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB5_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT:    bnez a0, .LBB5_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB5_2:
+; RV32IDZFH-NEXT:    beqz a0, .LBB5_2
+; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT:  .LBB5_2: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT:    bnez a0, .LBB5_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB5_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB5_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV64IDZFH-NEXT:  .LBB5_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB8_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB8_2:
+; RV32IZFH-NEXT:    beqz a0, .LBB8_2
+; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT:  .LBB8_2: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_wu_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB8_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB8_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB8_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB8_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT:    bnez a0, .LBB8_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB8_2:
+; RV32IDZFH-NEXT:    beqz a0, .LBB8_2
+; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT:  .LBB8_2: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT:    bnez a0, .LBB8_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB8_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB8_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV64IDZFH-NEXT:  .LBB8_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill

 ; RV32IZFH-NEXT:  .LBB10_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB10_7
 ; RV32IZFH-NEXT:    j .LBB10_8
 ;
 ; RV64IZFH-LABEL: fcvt_l_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB10_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB10_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB10_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB10_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_l_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill

 ; RV32IDZFH-NEXT:  .LBB10_12:
 ; RV32IDZFH-NEXT:    addi a1, a4, -1
 ; RV32IDZFH-NEXT:    beqz a2, .LBB10_7
 ; RV32IDZFH-NEXT:    j .LBB10_8
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT:    bnez a0, .LBB10_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB10_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB10_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
+; RV64IDZFH-NEXT:  .LBB10_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_l_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

 ; RV32IZFH-NEXT:  .LBB12_8: # %start
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB12_5
 ; RV32IZFH-NEXT:    j .LBB12_6
 ;
 ; RV64IZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB12_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB12_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB12_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB12_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill

 ; RV32IDZFH-NEXT:  .LBB12_8: # %start
 ; RV32IDZFH-NEXT:    li a1, 0
 ; RV32IDZFH-NEXT:    beqz a4, .LBB12_5
 ; RV32IDZFH-NEXT:    j .LBB12_6
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h_sat:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT:    bnez a0, .LBB12_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB12_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB12_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
+; RV64IDZFH-NEXT:  .LBB12_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_lu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   ret i16 %1
 }
 
 define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IZFH-NEXT:    bnez a0, .LBB32_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB32_2:
+; RV32IZFH-NEXT:    beqz a0, .LBB32_2
+; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI32_0)
 ; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI32_1)
 ; RV32IZFH-NEXT:    flw ft2, %lo(.LCPI32_1)(a0)
 ; RV32IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT:  .LBB32_2: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IZFH-NEXT:    bnez a0, .LBB32_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB32_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB32_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI32_0)
 ; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI32_1)
 ; RV64IZFH-NEXT:    flw ft2, %lo(.LCPI32_1)(a0)
 ; RV64IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT:  .LBB32_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT:    bnez a0, .LBB32_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB32_2:
+; RV32IDZFH-NEXT:    beqz a0, .LBB32_2
+; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI32_0)
 ; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI32_1)
 ; RV32IDZFH-NEXT:    flw ft2, %lo(.LCPI32_1)(a0)
 ; RV32IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT:  .LBB32_2: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT:    bnez a0, .LBB32_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB32_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB32_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI32_0)
 ; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI32_0)(a0)
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI32_1)
 ; RV64IDZFH-NEXT:    flw ft2, %lo(.LCPI32_1)(a0)
 ; RV64IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT:  .LBB32_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
; RV64I-NEXT:    ret
   ret i8 %1
 }
 
 define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IZFH-NEXT:    bnez a0, .LBB36_2
-; RV32IZFH-NEXT:  # %bb.1: # %start
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB36_2:
+; RV32IZFH-NEXT:    beqz a0, .LBB36_2
+; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI36_0)
 ; RV32IZFH-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI36_1)
 ; RV32IZFH-NEXT:    flw ft2, %lo(.LCPI36_1)(a0)
 ; RV32IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT:  .LBB36_2: # %start
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV64IZFH:       # %bb.0: # %start
 ; RV64IZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IZFH-NEXT:    bnez a0, .LBB36_2
-; RV64IZFH-NEXT:  # %bb.1: # %start
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB36_2:
+; RV64IZFH-NEXT:    beqz a0, .LBB36_2
+; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI36_0)
 ; RV64IZFH-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
 ; RV64IZFH-NEXT:    lui a0, %hi(.LCPI36_1)
 ; RV64IZFH-NEXT:    flw ft2, %lo(.LCPI36_1)(a0)
 ; RV64IZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT:  .LBB36_2: # %start
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV32IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT:    bnez a0, .LBB36_2
-; RV32IDZFH-NEXT:  # %bb.1: # %start
-; RV32IDZFH-NEXT:    li a0, 0
-; RV32IDZFH-NEXT:    ret
-; RV32IDZFH-NEXT:  .LBB36_2:
+; RV32IDZFH-NEXT:    beqz a0, .LBB36_2
+; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI36_0)
 ; RV32IDZFH-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI36_1)
 ; RV32IDZFH-NEXT:    flw ft2, %lo(.LCPI36_1)(a0)
 ; RV32IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV32IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV32IDZFH-NEXT:    fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT:  .LBB36_2: # %start
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.s.h ft0, fa0
 ; RV64IDZFH-NEXT:    feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT:    bnez a0, .LBB36_2
-; RV64IDZFH-NEXT:  # %bb.1: # %start
-; RV64IDZFH-NEXT:    li a0, 0
-; RV64IDZFH-NEXT:    ret
-; RV64IDZFH-NEXT:  .LBB36_2:
+; RV64IDZFH-NEXT:    beqz a0, .LBB36_2
+; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI36_0)
 ; RV64IDZFH-NEXT:    flw ft1, %lo(.LCPI36_0)(a0)
 ; RV64IDZFH-NEXT:    lui a0, %hi(.LCPI36_1)
 ; RV64IDZFH-NEXT:    flw ft2, %lo(.LCPI36_1)(a0)
 ; RV64IDZFH-NEXT:    fmax.s ft0, ft0, ft1
 ; RV64IDZFH-NEXT:    fmin.s ft0, ft0, ft2
 ; RV64IDZFH-NEXT:    fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT:  .LBB36_2: # %start
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=RV64IZFH %s
 
 define signext i32 @test_floor_si32(half %x) {
 ; RV32IZFH-LABEL: test_floor_si32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB0_2
+; RV32IZFH-NEXT:    beqz a0, .LBB0_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB0_2:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
+; RV32IZFH-NEXT:  .LBB0_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB0_2
+; RV64IZFH-NEXT:    beqz a0, .LBB0_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB0_2:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
+; RV64IZFH-NEXT:  .LBB0_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_si64:

 ; RV32IZFH-NEXT:  .LBB1_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB1_7
 ; RV32IZFH-NEXT:    j .LBB1_8
 ;
 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB1_2
+; RV64IZFH-NEXT:    beqz a0, .LBB1_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB1_2:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
+; RV64IZFH-NEXT:  .LBB1_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB2_2
+; RV32IZFH-NEXT:    beqz a0, .LBB2_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB2_2:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
+; RV32IZFH-NEXT:  .LBB2_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB2_2
+; RV64IZFH-NEXT:    beqz a0, .LBB2_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB2_2:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
+; RV64IZFH-NEXT:  .LBB2_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:

 ; RV32IZFH-NEXT:  .LBB3_8:
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB3_5
 ; RV32IZFH-NEXT:    j .LBB3_6
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB3_2
+; RV64IZFH-NEXT:    beqz a0, .LBB3_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB3_2:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
+; RV64IZFH-NEXT:  .LBB3_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB4_2
+; RV32IZFH-NEXT:    beqz a0, .LBB4_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB4_2:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
+; RV32IZFH-NEXT:  .LBB4_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB4_2
+; RV64IZFH-NEXT:    beqz a0, .LBB4_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB4_2:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rup
+; RV64IZFH-NEXT:  .LBB4_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_si64:

 ; RV32IZFH-NEXT:  .LBB5_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB5_7
 ; RV32IZFH-NEXT:    j .LBB5_8
 ;
 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB5_2
+; RV64IZFH-NEXT:    beqz a0, .LBB5_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB5_2:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
+; RV64IZFH-NEXT:  .LBB5_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB6_2
+; RV32IZFH-NEXT:    beqz a0, .LBB6_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB6_2:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
+; RV32IZFH-NEXT:  .LBB6_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB6_2
+; RV64IZFH-NEXT:    beqz a0, .LBB6_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB6_2:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
+; RV64IZFH-NEXT:  .LBB6_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:

 ; RV32IZFH-NEXT:  .LBB7_8:
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB7_5
 ; RV32IZFH-NEXT:    j .LBB7_6
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB7_2
+; RV64IZFH-NEXT:    beqz a0, .LBB7_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB7_2:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
+; RV64IZFH-NEXT:  .LBB7_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB8_2
+; RV32IZFH-NEXT:    beqz a0, .LBB8_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB8_2:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT:  .LBB8_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB8_2
+; RV64IZFH-NEXT:    beqz a0, .LBB8_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB8_2:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB8_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_si64:

 ; RV32IZFH-NEXT:  .LBB9_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB9_7
 ; RV32IZFH-NEXT:    j .LBB9_8
 ;
 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB9_2
+; RV64IZFH-NEXT:    beqz a0, .LBB9_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB9_2:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB9_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB10_2
+; RV32IZFH-NEXT:    beqz a0, .LBB10_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB10_2:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT:  .LBB10_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB10_2
+; RV64IZFH-NEXT:    beqz a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB10_2:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB10_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:

 ; RV32IZFH-NEXT:  .LBB11_8:
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB11_5
 ; RV32IZFH-NEXT:    j .LBB11_6
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB11_2
+; RV64IZFH-NEXT:    beqz a0, .LBB11_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB11_2:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT:  .LBB11_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
 ; RV32IZFH-LABEL: test_round_si32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB12_2
+; RV32IZFH-NEXT:    beqz a0, .LBB12_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB12_2:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
+; RV32IZFH-NEXT:  .LBB12_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB12_2
+; RV64IZFH-NEXT:    beqz a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB12_2:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
+; RV64IZFH-NEXT:  .LBB12_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_si64:

 ; RV32IZFH-NEXT:  .LBB13_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB13_7
 ; RV32IZFH-NEXT:    j .LBB13_8
 ;
 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB13_2
+; RV64IZFH-NEXT:    beqz a0, .LBB13_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB13_2:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
+; RV64IZFH-NEXT:  .LBB13_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
 ; RV32IZFH-LABEL: test_round_ui32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB14_2
+; RV32IZFH-NEXT:    beqz a0, .LBB14_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB14_2:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
+; RV32IZFH-NEXT:  .LBB14_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB14_2
+; RV64IZFH-NEXT:    beqz a0, .LBB14_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB14_2:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
+; RV64IZFH-NEXT:  .LBB14_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:

 ; RV32IZFH-NEXT:  .LBB15_8:
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB15_5
 ; RV32IZFH-NEXT:    j .LBB15_6
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB15_2
+; RV64IZFH-NEXT:    beqz a0, .LBB15_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB15_2:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
+; RV64IZFH-NEXT:  .LBB15_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB16_2
+; RV32IZFH-NEXT:    beqz a0, .LBB16_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB16_2:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
+; RV32IZFH-NEXT:  .LBB16_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB16_2
+; RV64IZFH-NEXT:    beqz a0, .LBB16_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB16_2:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rne
+; RV64IZFH-NEXT:  .LBB16_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_si64:

 ; RV32IZFH-NEXT:  .LBB17_12:
 ; RV32IZFH-NEXT:    addi a1, a4, -1
 ; RV32IZFH-NEXT:    beqz a2, .LBB17_7
 ; RV32IZFH-NEXT:    j .LBB17_8
 ;
 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB17_2
+; RV64IZFH-NEXT:    beqz a0, .LBB17_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB17_2:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
+; RV64IZFH-NEXT:  .LBB17_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui32:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV32IZFH-NEXT:    bnez a0, .LBB18_2
+; RV32IZFH-NEXT:    beqz a0, .LBB18_2
 ; RV32IZFH-NEXT:  # %bb.1:
-; RV32IZFH-NEXT:    li a0, 0
-; RV32IZFH-NEXT:    ret
-; RV32IZFH-NEXT:  .LBB18_2:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
+; RV32IZFH-NEXT:  .LBB18_2:
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui32:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB18_2
+; RV64IZFH-NEXT:    beqz a0, .LBB18_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB18_2:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
+; RV64IZFH-NEXT:  .LBB18_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:

 ; RV32IZFH-NEXT:  .LBB19_8:
 ; RV32IZFH-NEXT:    li a1, 0
 ; RV32IZFH-NEXT:    beqz a4, .LBB19_5
 ; RV32IZFH-NEXT:    j .LBB19_6
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    feq.h a0, fa0, fa0
-; RV64IZFH-NEXT:    bnez a0, .LBB19_2
+; RV64IZFH-NEXT:    beqz a0, .LBB19_2
 ; RV64IZFH-NEXT:  # %bb.1:
-; RV64IZFH-NEXT:    li a0, 0
-; RV64IZFH-NEXT:    ret
-; RV64IZFH-NEXT:  .LBB19_2:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
+; RV64IZFH-NEXT:  .LBB19_2:
 ; RV64IZFH-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 declare half @llvm.floor.f16(half)
 declare half @llvm.ceil.f16(half)
 declare half @llvm.trunc.f16(half)
 declare half @llvm.round.f16(half)
 declare half @llvm.roundeven.f16(half)
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 declare i64 @llvm.fptoui.sat.i64.f16(half)

llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a0, %hi(bytes)
 ; RV32I-NEXT:    lbu a1, %lo(bytes)(a0)
 ; RV32I-NEXT:    addi a0, a0, %lo(bytes)
 ; RV32I-NEXT:    lbu a0, 1(a0)
 ; RV32I-NEXT:    xori a1, a1, 136
 ; RV32I-NEXT:    xori a0, a0, 7
 ; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    bnez a0, .LBB0_2
-; RV32I-NEXT:  # %bb.1: # %if.end
-; RV32I-NEXT:    li a0, 0
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB0_2: # %if.then
+; RV32I-NEXT:    beqz a0, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:  .LBB0_2: # %if.end
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1
   %cmp = icmp eq i8 %0, -120
   %1 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 1), align 1
   %cmp3 = icmp eq i8 %1, 7
   %or.cond = and i1 %cmp, %cmp3
   br i1 %or.cond, label %if.end, label %if.then

 ; RV32I-NEXT:    lhu a1, %lo(shorts)(a0)
 ; RV32I-NEXT:    addi a0, a0, %lo(shorts)
 ; RV32I-NEXT:    lhu a0, 2(a0)
 ; RV32I-NEXT:    lui a2, 16
 ; RV32I-NEXT:    addi a2, a2, -120
 ; RV32I-NEXT:    xor a1, a1, a2
 ; RV32I-NEXT:    xori a0, a0, 7
 ; RV32I-NEXT:    or a0, a1, a0
-; RV32I-NEXT:    bnez a0, .LBB1_2
-; RV32I-NEXT:  # %bb.1: # %if.end
-; RV32I-NEXT:    li a0, 0
-; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB1_2: # %if.then
+; RV32I-NEXT:    beqz a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.then
 ; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:  .LBB1_2: # %if.end
 ; RV32I-NEXT:    ret
 entry:
   %0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2
   %cmp = icmp eq i16 %0, -120
   %1 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 1), align 2
   %cmp3 = icmp eq i16 %1, 7
   %or.cond = and i1 %cmp, %cmp3
   br i1 %or.cond, label %if.end, label %if.then
 
 if.then:
   ret i32 1
 
 if.end:
   ret i32 0
 }