[RISCV] Update Privileged spec to version-20211203: Removed the N extension

[tangxingxin1008]

Summary

Removed the following CSRs:
    - USTATUS, UIE, UTVEC
    - USCRATCH, UEPC, UCAUSE, UTVAL, UIP
Removed the following instruction:
    - URET

Signed-off-by: eric.tang <[e-mail]>

[RISCV] Update Privileged spec to version-20211203: Support Sinval Extention

Support Sinval Extention, Version 1.0

Add Supervisor Memory-Management Instructions:
    - SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR
Add Hypervisor Memory-Management Instructions:
    - HFENCE.VVMA, HFENCE.GVMA, HINVAL.VVMA, HINVAL.GVMA

Signed-off-by: eric.tang <[e-mail]>

[RISCV] Update Privileged spec to version-20211203: Support Hypervisor Extention

Support Hypervisor Extention, Version 1.0

Add the following instructions:
    - HLV.B HLV.BU
    - HLV.H HLV.HU HLVX.HU
    - HLV.W HLV.WU HLVX.WU
    - HLV.D
    - HSV.B HSV.H HSV.W HSV.D

Hypervisor CSRs has been updated.

Signed-off-by: eric.tang <[e-mail]>

[tangxingxin1008]

Sorry, I will recommit these patches

llvm/lib/Target/RISCV/RISCVISelLowering.h

 
 namespace llvm {
 class RISCVSubtarget;
 struct RISCVRegisterInfo;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
-  URET_FLAG,
   SRET_FLAG,
   MRET_FLAG,
   CALL,
   /// Select with condition operator - This selects between a true value and
   /// a false value (ops #3 and #4) based on the boolean result of comparing
   /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
   /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
   /// The lhs and rhs are XLenVT integers. The true and false values can be

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerFormalArguments(
   if (Func.hasFnAttribute("interrupt")) {
     if (!Func.arg_empty())
       report_fatal_error(
         "Functions with the interrupt attribute cannot have arguments!");
 
     StringRef Kind =
       MF.getFunction().getFnAttribute("interrupt").getValueAsString();
 
-    if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
+    if (!(Kind == "supervisor" || Kind == "machine"))
       report_fatal_error(
         "Function interrupt attribute argument not supported!");
   }
 
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
   // Used with vargs to acumulate store chains.
if (Func.hasFnAttribute("interrupt")) {
     if (!Func.getReturnType()->isVoidTy())
       report_fatal_error(
           "Functions with the interrupt attribute must have void return type!");
 
     MachineFunction &MF = DAG.getMachineFunction();
     StringRef Kind =
       MF.getFunction().getFnAttribute("interrupt").getValueAsString();
 
-    if (Kind == "user")
-      RetOpc = RISCVISD::URET_FLAG;
-    else if (Kind == "supervisor")
+    if (Kind == "supervisor")
       RetOpc = RISCVISD::SRET_FLAG;
     else
       RetOpc = RISCVISD::MRET_FLAG;
   }
 
   return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
 }
 

 #define NODE_NAME_CASE(NODE)                                                   \
   case RISCVISD::NODE:                                                         \
     return "RISCVISD::" #NODE;
   // clang-format off
   switch ((RISCVISD::NodeType)Opcode) {
   case RISCVISD::FIRST_NUMBER:
     break;
   NODE_NAME_CASE(RET_FLAG)
-  NODE_NAME_CASE(URET_FLAG)
   NODE_NAME_CASE(SRET_FLAG)
   NODE_NAME_CASE(MRET_FLAG)
   NODE_NAME_CASE(CALL)
   NODE_NAME_CASE(SELECT_CC)
   NODE_NAME_CASE(BR_CC)
   NODE_NAME_CASE(BuildPairF64)
   NODE_NAME_CASE(SplitF64)
   NODE_NAME_CASE(TAIL)

llvm/lib/Target/RISCV/RISCVInstrInfo.td

def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 // Target-dependent nodes.
 def riscv_call      : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
                              [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                               SDNPVariadic]>;
 def riscv_ret_flag  : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone,
-                             [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_selectcc  : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>;
 def riscv_brcc      : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC,
                              [SDNPHasChain]>;
 def riscv_tail      : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
+def immzero : Operand<XLenVT>,
+              ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
+  let ParserMatchClass = ImmZeroAsmOperand;
+}
+
 def uimm2 : Operand<XLenVT> {
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_UIMM2";
   let OperandNamespace = "RISCVOp";
 }
 
 def uimm3 : Operand<XLenVT> {
class BranchCC_rri<bits<3> funct3, string opcodestr>
     : RVInstB<funct3, OPC_BRANCH, (outs),
               (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
               opcodestr, "$rs1, $rs2, $imm12">,
       Sched<[WriteJmp, ReadJmp, ReadJmp]> {
   let isBranch = 1;
   let isTerminator = 1;
 }
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class Load_ri<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
               opcodestr, "$rd, ${imm12}(${rs1})">;
 
+class HLoad_ri<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstI<0b100, OPC_SYSTEM, (outs GPR:$rd), (ins GPR:$rs1, immzero:$imm2),
+              opcodestr, "$rd, ${imm2}(${rs1})"> {
+  bits<2> imm2;
+  let Inst{31-25} = funct7;
+  let Inst{24-23} = imm2;
+  let Inst{22-20} = funct3;
+}
+}
+
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class Store_rri<bits<3> funct3, string opcodestr>
     : RVInstS<funct3, OPC_STORE, (outs),
               (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
               opcodestr, "$rs2, ${imm12}(${rs1})">;
 
+class HStore_ri<bits<7> funct7, string opcodestr>
+    : RVInstR<funct7, 0b100, OPC_SYSTEM, (outs),
+              (ins GPR:$rs2, GPR:$rs1, immzero:$imm5),
+               opcodestr, "$rs2, ${imm5}(${rs1})">, Sched<[]> {
+  bits<5> imm5;
+  let Inst{11-7} = imm5;
+}
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class ALU_ri<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
               opcodestr, "$rd, $rs1, $imm12">,
       Sched<[WriteIALU, ReadIALU]>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class Shift_ri<bits<5> imm11_7, bits<3> funct3, string opcodestr>
def SRAW  : ALUW_rr<0b0100000, 0b101, "sraw">,
             Sched<[WriteShiftReg32, ReadShiftReg32, ReadShiftReg32]>;
 } // Predicates = [IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Privileged instructions
 //===----------------------------------------------------------------------===//
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
-def URET : Priv<"uret", 0b0000000>, Sched<[]> {
-  let rd = 0;
-  let rs1 = 0;
-  let rs2 = 0b00010;
-}
-
 def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = 0b00010;
 }
 
 def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = 0b00010;
 }
 } // isBarrier = 1, isReturn = 1, isTerminator = 1
 
 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = 0b00101;
 }
 
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 , rd = 0 in {
 def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
                          (ins GPR:$rs1, GPR:$rs2),
-                         "sfence.vma", "$rs1, $rs2">, Sched<[]> {
-  let rd = 0;
+                         "sfence.vma", "$rs1, $rs2">, Sched<[]>;
+def SINVAL_VMA : RVInstR<0b0001011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "sinval.vma", "$rs1, $rs2">, Sched<[]>;
+
+def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> {
+  let rs1 = 0;
+  let rs2 = 0;
+}
+
+def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
+  let rs1 = 0;
+  let rs2 = 0b00001;
+}
+
+def HFENCE_VVMA : RVInstR<0b0010001, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hfence.vvma", "$rs1, $rs2">, Sched<[]>;
+
+def HFENCE_GVMA : RVInstR<0b0110001, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hfence.gvma", "$rs1, $rs2">, Sched<[]>;
+
+def HINVAL_VVMA : RVInstR<0b0010011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hinval.vvma", "$rs1, $rs2">, Sched<[]>;
+
+def HINVAL_GVMA : RVInstR<0b0110011, 0b000, OPC_SYSTEM, (outs),
+                         (ins GPR:$rs1, GPR:$rs2),
+                         "hinval.gvma", "$rs1, $rs2">, Sched<[]>;
+}
+
+def HLV_B : HLoad_ri<0b0110000, 0b000, "hlv.b">;
+def HLV_BU : HLoad_ri<0b0110000, 0b001, "hlv.bu">;
+def HLV_H : HLoad_ri<0b0110010, 0b000, "hlv.h">;
+def HLV_HU : HLoad_ri<0b0110010, 0b001, "hlv.hu">;
+def HLVX_HU : HLoad_ri<0b0110010, 0b011, "hlvx.hu">;
+def HLV_W : HLoad_ri<0b0110100, 0b000, "hlv.w">;
+def HLVX_WU : HLoad_ri<0b0110100, 0b011, "hlvx.wu">;
+let Predicates = [IsRV64] in {
+def HLV_WU : HLoad_ri<0b0110100, 0b001, "hlv.wu">;
+def HLV_D : HLoad_ri<0b0110110, 0b000, "hlv.d">;
+}
+
+def HSV_B : HStore_ri<0b0110001, "hsv.b">;
+def HSV_H : HStore_ri<0b0110011, "hsv.h">;
+def HSV_W : HStore_ri<0b0110101, "hsv.w">;
+let Predicates = [IsRV64] in
+def HSV_D : HStore_ri<0b0110111, "hsv.d">;
+
+let EmitPriority = 0 in {
+def : InstAlias<"hlv.b $rd, (${rs1})", (HLV_B GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.bu $rd, (${rs1})", (HLV_BU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.h $rd, (${rs1})", (HLV_H GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.hu $rd, (${rs1})", (HLV_HU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlvx.hu $rd, (${rs1})", (HLVX_HU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.w $rd, (${rs1})", (HLV_W GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.wu $rd, (${rs1})", (HLV_WU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlvx.wu $rd, (${rs1})", (HLVX_WU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hlv.d $rd, (${rs1})", (HLV_D GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"hsv.b $rs2, (${rs1})", (HSV_B GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"hsv.h $rs2, (${rs1})", (HSV_H GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"hsv.w $rs2, (${rs1})", (HSV_W GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"hsv.d $rs2, (${rs1})", (HSV_D GPR:$rs2, GPR:$rs1, 0)>;
 }
 
 //===----------------------------------------------------------------------===//
 // Debug instructions
 //===----------------------------------------------------------------------===//
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
 def DRET : Priv<"dret", 0b0111101>, Sched<[]> {

 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 }
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
+def : InstAlias<"hfence.gvma",     (HFENCE_GVMA      X0, X0)>;
+def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
+
 let EmitPriority = 0 in {
 def : InstAlias<"lb $rd, (${rs1})",
                 (LB  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lh $rd, (${rs1})",
                 (LH  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lw $rd, (${rs1})",
                 (LW  GPR:$rd, GPR:$rs1, 0)>;
 def : InstAlias<"lbu $rd, (${rs1})",

 let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in
 def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []> {
   let AsmString = "call\t$func";
 }
 
 def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
 def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
-def : Pat<(riscv_uret_flag), (URET X0, X0)>;
 def : Pat<(riscv_sret_flag), (SRET X0, X0)>;
 def : Pat<(riscv_mret_flag), (MRET X0, X0)>;
 
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                 [(riscv_call GPRJALR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

def simm6nonzero : Operand<XLenVT>,
   let MCOperandPredicate = [{
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return (Imm != 0) && isInt<6>(Imm);
     return MCOp.isBareSymbolRef();
   }];
 }
 
-def immzero : Operand<XLenVT>,
-              ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
-  let ParserMatchClass = ImmZeroAsmOperand;
-}
-
 def CLUIImmAsmOperand : AsmOperandClass {
   let Name = "CLUIImm";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = !strconcat("Invalid", Name);
 }
 
 
 // c_lui_imm checks the immediate range is in [1, 31] or [0xfffe0, 0xfffff].

llvm/lib/Target/RISCV/RISCVSystemOperands.td

def lookupSysRegByDeprecatedName : SearchIndex {
   let Key = [ "DeprecatedName" ];
 }
 
 // The following CSR encodings match those given in Tables 2.2,
 // 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
 
 //===----------------------------------------------------------------------===//
-// User Trap Setup
-//===----------------------------------------------------------------------===//
-def : SysReg<"ustatus", 0x000>;
-def : SysReg<"uie", 0x004>;
-def : SysReg<"utvec", 0x005>;
-
-//===----------------------------------------------------------------------===//
-// User Trap Handling
-//===----------------------------------------------------------------------===//
-def : SysReg<"uscratch", 0x040>;
-def : SysReg<"uepc", 0x041>;
-def : SysReg<"ucause", 0x042>;
-let DeprecatedName = "ubadaddr" in
-def : SysReg<"utval", 0x043>;
-def : SysReg<"uip", 0x044>;
-
-//===----------------------------------------------------------------------===//
 // User Floating-Point CSRs
 //===----------------------------------------------------------------------===//
 
 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
 def SysRegFRM    : SysReg<"frm", 0x002>;
 def SysRegFCSR   : SysReg<"fcsr", 0x003>;
 
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll

 ; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s
 ; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s
 
 ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
-define i32 @isr_user(i8 %n) #0 {
+define i32 @isr_supervisor(i8 %n) #0 {
   ret i32 0
 }
 
-attributes #0 = { "interrupt"="user" }
+attributes #0 = { "interrupt"="supervisor" }

llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll

 ; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s
 ; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s
 
 ; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
-define i32 @isr1_user() #0 {
+define i32 @isr1_supervisor() #0 {
   ret i32 0
 }
 
 
-attributes #0 = { "interrupt"="user" }
+attributes #0 = { "interrupt"="supervisor" }

llvm/test/CodeGen/RISCV/interrupt-attr.ll

 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
 
 ;
 ; Checking for special return instructions (uret, sret, mret).
 ;
-define void @foo_user() #0 {
-; CHECK-LABEL: foo_user:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    uret
-  ret void
-}
 
-define void @foo_supervisor() #1 {
+define void @foo_supervisor() #0 {
 ; CHECK-LABEL: foo_supervisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sret
   ret void
 }
 
-define void @foo_machine() #2 {
+define void @foo_machine() #1 {
 ; CHECK-LABEL: foo_machine:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mret
   ret void
 }
 
 ;
 ; Checking all Caller saved registers (arguments and temps)
 ; and FP registers are all saved when the handler calls another function.
 ;
 ; extern int otherfoo();
 ;
 ; __attribute__((interrupt)) void foo_with_call() {
 ;   otherfoo();
 ; }
 ;
 
 declare i32 @otherfoo(...)
-define void @foo_with_call() #2 {
+define void @foo_with_call() #1 {
 ;
 ; CHECK-RV32-LABEL: foo_with_call:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    addi sp, sp, -64
 ; CHECK-RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    mret
   %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
   ret void
 }
 
 ;
 ; Additionally check frame pointer and return address are properly saved.
 ;
-define void @foo_fp_with_call() #3 {
+define void @foo_fp_with_call() #2 {
 ;
 ; CHECK-RV32-LABEL: foo_fp_with_call:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    addi sp, sp, -80
 ; CHECK-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t0, 72(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t1, 68(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t2, 64(sp) # 4-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    fld fs10, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld fs11, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    addi sp, sp, 400
 ; CHECK-RV64-FD-NEXT:    mret
   %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
   ret void
 }
 
-attributes #0 = { nounwind "interrupt"="user" }
-attributes #1 = { nounwind "interrupt"="supervisor" }
-attributes #2 = { nounwind  "interrupt"="machine" }
-attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" }
+attributes #0 = { nounwind "interrupt"="supervisor" }
+attributes #1 = { nounwind "interrupt"="machine" }
+attributes #2 = { nounwind "interrupt"="machine" "frame-pointer"="all" }

llvm/test/CodeGen/RISCV/saverestore.ll

 ; RV64I-FP-SR:         tail __riscv_restore_2
   %sp = call i8* @llvm.stacksave()
   %addr = alloca i8, i32 %n
   call void @notdead(i8* %addr)
   call void @llvm.stackrestore(i8* %sp)
   ret void
 }
 
-; Check that functions with interrupt attribute do not use save/restore code
-
-declare i32 @foo(...)
-define void @interrupt() nounwind "interrupt"="user" {
-; RV32I-LABEL: interrupt:
-; RV32I-NOT:     call t0, __riscv_save
-; RV32I-NOT:     tail __riscv_restore
-;
-; RV64I-LABEL: interrupt:
-; RV64I-NOT:     call t0, __riscv_save
-; RV64I-NOT:     tail __riscv_restore
-;
-; RV32I-SR-LABEL: interrupt:
-; RV32I-SR-NOT:     call t0, __riscv_save
-; RV32I-SR-NOT:     tail __riscv_restore
-;
-; RV64I-SR-LABEL: interrupt:
-; RV64I-SR-NOT:     call t0, __riscv_save
-; RV64I-SR-NOT:     tail __riscv_restore
-;
-; RV32I-FP-SR-LABEL: interrupt:
-; RV32I-FP-SR-NOT:     call t0, __riscv_save
-; RV32I-FP-SR-NOT:     tail __riscv_restore
-;
-; RV64I-FP-SR-LABEL: interrupt:
-; RV64I-FP-SR-NOT:     call t0, __riscv_save
-; RV64I-FP-SR-NOT:     tail __riscv_restore
-  %call = call i32 bitcast (i32 (...)* @foo to i32 ()*)()
-  ret void
-}

llvm/test/MC/RISCV/deprecated-csr-names.s

 # CHECK-INST-ALIAS: csrw mtval, zero
 # name
 csrw mbadaddr, zero
 # uimm12
 csrrw zero, 0x343, zero
 
 # CHECK-WARN: warning: 'mbadaddr' is a deprecated alias for 'mtval'
 
-# ubadaddr
-# name
-# CHECK-INST: csrrw zero, utval, zero
-# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
-# CHECK-INST-ALIAS: csrw utval, zero
-# uimm12
-# CHECK-INST: csrrw zero, utval, zero
-# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
-# CHECK-INST-ALIAS: csrw utval, zero
-# name
-csrw ubadaddr, zero
-# uimm12
-csrrw zero, 0x043, zero
-
-# CHECK-WARN: warning: 'ubadaddr' is a deprecated alias for 'utval'
-
 # sptbr
 # name
 # CHECK-INST: csrrw zero, satp, zero
 # CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
 # CHECK-INST-ALIAS: csrw satp, zero
 # uimm12
 # CHECK-INST: csrrw zero, satp, zero
 # CHECK-ENC: encoding: [0x73,0x10,0x00,0x18]
 # CHECK-INST-ALIAS: csrw satp, zero
 # name
 csrw sptbr, zero
 # uimm12
 csrrw zero, 0x180, zero
 
 # CHECK-WARN: warning: 'sptbr' is a deprecated alias for 'satp'

llvm/test/MC/RISCV/priv-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: hlv.b a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x60]
+hlv.b   a0, (a1)
+
+# CHECK-INST: hlv.bu a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x60]
+hlv.bu  a0, (a1)
+
+# CHECK-INST: hlv.h a1, 0(a2)
+# CHECK: encoding: [0xf3,0x45,0x06,0x64]
+hlv.h   a1, (a2)
+
+# CHECK-INST: hlv.hu a1, 0(a1)
+# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
+hlv.hu  a1, (a1)
+
+# CHECK-INST: hlvx.hu a1, 0(a2)
+# CHECK: encoding: [0xf3,0x45,0x36,0x64]
+hlvx.hu a1, (a2)
+
+# CHECK-INST: hlv.w a2, 0(a2)
+# CHECK: encoding: [0x73,0x46,0x06,0x68]
+hlv.w   a2, (a2)
+
+# CHECK-INST: hlvx.wu a2, 0(a3)
+# CHECK: encoding: [0x73,0xc6,0x36,0x68]
+hlvx.wu a2, (a3)
+
+# CHECK-INST: hsv.b a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
+hsv.b   a0, (a1)
+
+# CHECK-INST: hsv.h a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
+hsv.h   a0, (a1)
+
+# CHECK-INST: hsv.w a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6a] 
+hsv.w   a0, (a1)

llvm/test/MC/RISCV/priv-invalid.s

-# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
 
 mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
 
 sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
 
 sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sinval.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+
+sinval.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.w.inval 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hlv.b a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.b a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.bu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlv.bu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlv.h a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.h a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.hu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlv.hu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlvx.hu a0, 0x10 # CHECK: :[[@LINE]]:13: error: immediate must be zero
+
+hlvx.hu a0, 1(a1) # CHECK: :[[@LINE]]:13: error: immediate must be zero
+
+hlv.w a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.w a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.wu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlv.wu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero
+
+hlv.d a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hlv.d a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.b a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.b a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.h a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.h a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.w a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.w a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.d a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero
+
+hsv.d a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero

llvm/test/MC/RISCV/priv-rv64-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: hlv.wu a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+hlv.wu   a0, (a1)
+
+# CHECK-INST: hlv.wu a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x68]
+hlv.wu   a0, 0(a1)
+
+# CHECK-INST: hlv.d a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x6c]
+hlv.d  a0, (a1)
+
+# CHECK-INST: hsv.d a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6e]
+hsv.d   a0, (a1)

llvm/test/MC/RISCV/priv-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: uret
-# CHECK: encoding: [0x73,0x00,0x20,0x00]
-uret
-
 # CHECK-INST: sret
 # CHECK: encoding: [0x73,0x00,0x20,0x10]
 sret
 
 # CHECK-INST: mret
 # CHECK: encoding: [0x73,0x00,0x20,0x30]
 mret
 
 # CHECK-INST: wfi
 # CHECK: encoding: [0x73,0x00,0x50,0x10]
 wfi
 
 # CHECK-INST: sfence.vma zero, zero
 # CHECK: encoding: [0x73,0x00,0x00,0x12]
 sfence.vma zero, zero
 
 # CHECK-INST: sfence.vma a0, a1
 # CHECK: encoding: [0x73,0x00,0xb5,0x12]
 sfence.vma a0, a1
+
+# CHECK-INST: sinval.vma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x16]
+sinval.vma zero, zero
+
+# CHECK-INST: sinval.vma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x16]
+sinval.vma a0, a1
+
+# CHECK-INST: sfence.w.inval
+# CHECK: encoding: [0x73,0x00,0x00,0x18]
+sfence.w.inval
+
+# CHECK-INST: sfence.inval.ir
+# CHECK: encoding: [0x73,0x00,0x10,0x18]
+sfence.inval.ir
+
+# CHECK-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma zero, zero
+
+# CHECK-INST: hfence.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x22]
+hfence.vvma a0, a1
+
+# CHECK-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma zero, zero
+
+# CHECK-INST: hfence.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x62]
+hfence.gvma a0, a1
+
+# CHECK-INST: hinval.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x26]
+hinval.vvma zero, zero
+
+# CHECK-INST: hinval.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x26]
+hinval.vvma a0, a1
+
+# CHECK-INST: hinval.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x66]
+hinval.gvma zero, zero
+
+# CHECK-INST: hinval.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x66]
+hinval.gvma a0, a1
+
+# CHECK-INST: hlv.b a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x05,0x60]
+hlv.b   a0, 0(a1)
+
+# CHECK-INST: hlv.bu a0, 0(a1)
+# CHECK: encoding: [0x73,0xc5,0x15,0x60]
+hlv.bu  a0, 0(a1)
+
+# CHECK-INST: hlv.h a1, 0(a2)
+# CHECK: encoding: [0xf3,0x45,0x06,0x64]
+hlv.h   a1, 0(a2)
+
+# CHECK-INST: hlv.hu a1, 0(a1)
+# CHECK: encoding: [0xf3,0xc5,0x15,0x64]
+hlv.hu  a1, 0(a1)
+
+# CHECK-INST: hlvx.hu a1, 0(a2)
+# CHECK: encoding: [0xf3,0x45,0x36,0x64]
+hlvx.hu a1, 0(a2)
+
+# CHECK-INST: hlv.w a2, 0(a2)
+# CHECK: encoding: [0x73,0x46,0x06,0x68]
+hlv.w   a2, 0(a2)
+
+# CHECK-INST: hlvx.wu a2, 0(a3)
+# CHECK: encoding: [0x73,0xc6,0x36,0x68]
+hlvx.wu a2, 0(a3)
+
+# CHECK-INST: hsv.b a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x62]
+hsv.b   a0, 0(a1)
+
+# CHECK-INST: hsv.h a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x66]
+hsv.h   a0, 0(a1)
+
+# CHECK-INST: hsv.w a0, 0(a1)
+# CHECK: encoding: [0x73,0xc0,0xa5,0x6a]
+hsv.w   a0, 0(a1)

llvm/test/MC/RISCV/rv32e-valid.s

 unimp
 
 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 csrrw t0, 0xfff, t1
 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
 csrrs s0, 0x001, a5
-# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
-csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
-csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 csrrsi t2, 0xfff, 31
 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
 csrrci t1, 0x140, 5

llvm/test/MC/RISCV/rv32i-valid.s

 # CHECK-ASM: encoding: [0x73,0x94,0x14,0x00]
 csrrw s0, !0, s1
 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 # CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
 csrrs s3, 0x001, s5
-# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
-# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
-csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
-# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
-csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 # CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff]
 csrrsi t2, 0xfff, 31
 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
 # CHECK-ASM: encoding: [0x73,0xf3,0x02,0x14]
 csrrci t1, 0x140, 5

llvm/test/MC/RISCV/rvi-aliases-valid.s

 csrrc t0, 0x140, 0x11
 
 # CHECK-S-OBJ-NOALIAS: sfence.vma zero, zero
 # CHECK-S-OBJ: sfence.vma
 sfence.vma
 # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero
 # CHECK-S-OBJ: sfence.vma a0
 sfence.vma a0
+# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero
+# CHECK-S-OBJ: hfence.gvma
+hfence.gvma
+# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero
+# CHECK-S-OBJ: hfence.gvma a0
+hfence.gvma a0
 
 # The following aliases are accepted as input but the canonical form
 # of the instruction will always be printed.
 # CHECK-S-OBJ-NOALIAS: addi a2, a3, 4
 # CHECK-S-OBJ: addi a2, a3, 4
 add a2, a3, 4
 # CHECK-S-OBJ-NOALIAS: andi a2, a3, 4
 # CHECK-S-OBJ: andi a2, a3, 4

llvm/test/MC/RISCV/user-csr-names.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 #
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
 ##################################
-# User Trap Setup
-##################################
-
-# ustatus
-# name
-# CHECK-INST: csrrs t1, ustatus, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x00]
-# CHECK-INST-ALIAS: csrr t1, ustatus
-# uimm12
-# CHECK-INST: csrrs t2, ustatus, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x00]
-# CHECK-INST-ALIAS: csrr t2, ustatus
-csrrs t1, ustatus, zero
-# uimm12
-csrrs t2, 0x000, zero
-
-# uie
-# name
-# CHECK-INST: csrrs t1, uie, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x00]
-# CHECK-INST-ALIAS: csrr t1, uie
-# uimm12
-# CHECK-INST: csrrs t2, uie, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x00]
-# CHECK-INST-ALIAS: csrr t2, uie
-# name
-csrrs t1, uie, zero
-# uimm12
-csrrs t2, 0x004, zero
-
-# utvec
-# name
-# CHECK-INST: csrrs t1, utvec, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x50,0x00]
-# CHECK-INST-ALIAS: csrr t1, utvec
-# uimm12
-# CHECK-INST: csrrs t2, utvec, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0x00]
-# CHECK-INST-ALIAS: csrr t2, utvec
-# name
-csrrs t1, utvec, zero
-# uimm12
-csrrs t2, 0x005, zero
-
-##################################
-# User Trap Handling
-##################################
-
-# uscratch
-# name
-# CHECK-INST: csrrs t1, uscratch, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x04]
-# CHECK-INST-ALIAS: csrr t1, uscratch
-# uimm12
-# CHECK-INST: csrrs t2, uscratch, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x04]
-# CHECK-INST-ALIAS: csrr t2, uscratch
-# name
-csrrs t1, uscratch, zero
-# uimm12
-csrrs t2, 0x040, zero
-
-# uepc
-# name
-# CHECK-INST: csrrs t1, uepc, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x10,0x04]
-# CHECK-INST-ALIAS: csrr t1, uepc
-# uimm12
-# CHECK-INST: csrrs t2, uepc, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0x04]
-# CHECK-INST-ALIAS: csrr t2, uepc
-# name
-csrrs t1, uepc, zero
-# uimm12
-csrrs t2, 0x041, zero
-
-# ucause
-# name
-# CHECK-INST: csrrs t1, ucause, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x20,0x04]
-# CHECK-INST-ALIAS: csrr t1, ucause
-# uimm12
-# CHECK-INST: csrrs t2, ucause, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0x04]
-# CHECK-INST-ALIAS: csrr t2, ucause
-# name
-csrrs t1, ucause, zero
-# uimm12
-csrrs t2, 0x042, zero
-
-# utval
-# name
-# CHECK-INST: csrrs t1, utval, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x30,0x04]
-# CHECK-INST-ALIAS: csrr t1, utval
-# uimm12
-# CHECK-INST: csrrs t2, utval, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x04]
-# CHECK-INST-ALIAS: csrr t2, utval
-# name
-csrrs t1, utval, zero
-# uimm12
-csrrs t2, 0x043, zero
-
-# uip
-# name
-# CHECK-INST: csrrs t1, uip, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x04]
-# CHECK-INST-ALIAS: csrr t1, uip
-# uimm12
-# CHECK-INST: csrrs t2, uip, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x04]
-# CHECK-INST-ALIAS: csrr t2, uip
-#name
-csrrs t1, uip, zero
-# uimm12
-csrrs t2, 0x044, zero
-
-##################################
 # User Floating Pont CSRs
 ##################################
 # Tests in rvf-user-mode-csr.s
 
 ##################################
 # User Counter and Timers
 ##################################