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Differential D117518

[RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask BUILD_VECTORs.
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Authored by craig.topper on Jan 17 2022, 3:21 PM.

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Reviewers
frasercrmck
rogfer01
arcbbb
khchen
kito-cheng
Commits
rG4060b81e76e6: [RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask…
Summary

We may not be allowed to use vXiXLen vectors. Consult ELEN to
determine what is allowed. This will become even more important
when Zve32 is added.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 17 2022, 3:21 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 17 2022, 3:21 PM
craig.topper requested review of this revision.Jan 17 2022, 3:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 17 2022, 3:21 PM
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craig.topper updated this revision to Diff 400659.Jan 17 2022, 3:28 PM

Use Subtarget method directly. Will need to fold Zve into that function in a later patch.

Harbormaster completed remote builds in B143878: Diff 400659.Jan 17 2022, 4:07 PM
arcbbb accepted this revision.Jan 19 2022, 1:29 AM

LGTM. Thanks!

This revision is now accepted and ready to land.Jan 19 2022, 1:29 AM
frasercrmck accepted this revision.Jan 19 2022, 2:25 AM

LGTM too, cheers

This revision was landed with ongoing or failed builds.Jan 19 2022, 10:48 AM
Closed by commit rG4060b81e76e6: [RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG4060b81e76e6: [RISCV] Obey -riscv-v-fixed-length-vector-elen-max when lowering mask….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
CodeGen/
RISCV/
rvv/
1751 lines

Diff 401335

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,923 Lines • ▼ Show 20 Lines if (VT.getVectorElementType() == MVT::i1) {
// bits and XLEN. // bits and XLEN.
// First, determine the most appropriate scalar integer type to use. This // First, determine the most appropriate scalar integer type to use. This
// is at most XLenVT, but may be shrunk to a smaller vector element type // is at most XLenVT, but may be shrunk to a smaller vector element type
// according to the size of the final vector - use i8 chunks rather than // according to the size of the final vector - use i8 chunks rather than
// XLenVT if we're producing a v8i1. This results in more consistent // XLenVT if we're producing a v8i1. This results in more consistent
// codegen across RV32 and RV64. // codegen across RV32 and RV64.
unsigned NumViaIntegerBits = unsigned NumViaIntegerBits =
std::min(std::max(NumElts, 8u), Subtarget.getXLen()); std::min(std::max(NumElts, 8u), Subtarget.getXLen());
NumViaIntegerBits = std::min(NumViaIntegerBits,
Subtarget.getMaxELENForFixedLengthVectors());
if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
// If we have to use more than one INSERT_VECTOR_ELT then this // If we have to use more than one INSERT_VECTOR_ELT then this
// optimization is likely to increase code size; avoid peforming it in // optimization is likely to increase code size; avoid peforming it in
// such a case. We can use a load from a constant pool in this case. // such a case. We can use a load from a constant pool in this case.
if (DAG.shouldOptForSize() && NumElts > NumViaIntegerBits) if (DAG.shouldOptForSize() && NumElts > NumViaIntegerBits)
return SDValue(); return SDValue();
// Now we can create our integer vector type. Note that it may be larger // Now we can create our integer vector type. Note that it may be larger
// than the resulting mask type: v4i1 would use v1i8 as its integer type. // than the resulting mask type: v4i1 would use v1i8 as its integer type.
▲ Show 20 Lines • Show All 8,713 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX1 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX1
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX1 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX1
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX2 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX2
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX2 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX2
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX4 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX4
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX4 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=4 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX4
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,RV32-LMULMAX8
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-LMULMAX8
; Test with ELEN limited
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN32
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN16
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=16 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN16
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32-ELEN,RV32-ELEN8
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64-ELEN,RV64-ELEN8
define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) { define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) {
; CHECK-LABEL: buildvec_mask_nonconst_v1i1: ; CHECK-LABEL: buildvec_mask_nonconst_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v1i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: andi a0, a0, 1
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.v.x v8, a0
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v1i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: andi a0, a0, 1
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.v.x v8, a0
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v1i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: andi a0, a0, 1
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.v.x v8, a0
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v1i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: andi a0, a0, 1
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.v.x v8, a0
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v1i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: andi a0, a0, 1
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.v.x v8, a0
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v1i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: andi a0, a0, 1
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.v.x v8, a0
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: ret
%1 = insertelement <1 x i1> undef, i1 %x, i32 0 %1 = insertelement <1 x i1> undef, i1 %x, i32 0
ret <1 x i1> %1 ret <1 x i1> %1
} }
define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize { define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize {
; CHECK-LABEL: buildvec_mask_optsize_nonconst_v1i1: ; CHECK-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 1 ; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: andi a0, a0, 1
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.v.x v8, a0
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: andi a0, a0, 1
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.v.x v8, a0
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: andi a0, a0, 1
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.v.x v8, a0
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: andi a0, a0, 1
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.v.x v8, a0
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: andi a0, a0, 1
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.v.x v8, a0
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v1i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: andi a0, a0, 1
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.v.x v8, a0
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: ret
%1 = insertelement <1 x i1> undef, i1 %x, i32 0 %1 = insertelement <1 x i1> undef, i1 %x, i32 0
ret <1 x i1> %1 ret <1 x i1> %1
} }
define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) { define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v2i1: ; CHECK-LABEL: buildvec_mask_nonconst_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v2i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.v.x v8, a1
; RV32-ELEN32-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
; RV32-ELEN32-NEXT: vmv.s.x v8, a0
; RV32-ELEN32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v2i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.v.x v8, a1
; RV64-ELEN32-NEXT: vsetvli zero, zero, e8, mf4, tu, mu
; RV64-ELEN32-NEXT: vmv.s.x v8, a0
; RV64-ELEN32-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v2i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.v.x v8, a1
; RV32-ELEN16-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v2i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.v.x v8, a1
; RV64-ELEN16-NEXT: vsetvli zero, zero, e8, mf2, tu, mu
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v2i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.v.x v8, a1
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v2i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.v.x v8, a1
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: ret
%1 = insertelement <2 x i1> undef, i1 %x, i32 0 %1 = insertelement <2 x i1> undef, i1 %x, i32 0
%2 = insertelement <2 x i1> %1, i1 %y, i32 1 %2 = insertelement <2 x i1> %1, i1 %y, i32 1
ret <2 x i1> %2 ret <2 x i1> %2
} }
; FIXME: optsize isn't smaller than the code above ; FIXME: optsize isn't smaller than the code above
define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize { define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize {
; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1: ; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: sb a0, 14(sp) ; CHECK-NEXT: sb a0, 14(sp)
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: addi a0, sp, 14 ; CHECK-NEXT: addi a0, sp, 14
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a1, 15(sp)
; RV32-ELEN32-NEXT: sb a0, 14(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 14
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a1, 15(sp)
; RV64-ELEN32-NEXT: sb a0, 14(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 14
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a1, 15(sp)
; RV32-ELEN16-NEXT: sb a0, 14(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 14
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a1, 15(sp)
; RV64-ELEN16-NEXT: sb a0, 14(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 2, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 14
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a1, 15(sp)
; RV32-ELEN8-NEXT: sb a0, 14(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 14
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v2i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a1, 15(sp)
; RV64-ELEN8-NEXT: sb a0, 14(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 14
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <2 x i1> undef, i1 %x, i32 0 %1 = insertelement <2 x i1> undef, i1 %x, i32 0
%2 = insertelement <2 x i1> %1, i1 %y, i32 1 %2 = insertelement <2 x i1> %1, i1 %y, i32 1
ret <2 x i1> %2 ret <2 x i1> %2
} }
define <3 x i1> @buildvec_mask_v1i1() { define <3 x i1> @buildvec_mask_v1i1() {
; CHECK-LABEL: buildvec_mask_v1i1: ; CHECK-LABEL: buildvec_mask_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 2 ; CHECK-NEXT: li a0, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v1i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 2
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v1i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 2
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v1i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 2
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v1i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 2
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v1i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 2
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v1i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 2
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: ret
ret <3 x i1> <i1 0, i1 1, i1 0> ret <3 x i1> <i1 0, i1 1, i1 0>
} }
define <3 x i1> @buildvec_mask_optsize_v1i1() optsize { define <3 x i1> @buildvec_mask_optsize_v1i1() optsize {
; CHECK-LABEL: buildvec_mask_optsize_v1i1: ; CHECK-LABEL: buildvec_mask_optsize_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 2 ; CHECK-NEXT: li a0, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_v1i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 2
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_v1i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 2
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_v1i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 2
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_v1i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 2
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_v1i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 2
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_v1i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 2
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: ret
ret <3 x i1> <i1 0, i1 1, i1 0> ret <3 x i1> <i1 0, i1 1, i1 0>
} }
define <4 x i1> @buildvec_mask_v4i1() { define <4 x i1> @buildvec_mask_v4i1() {
; CHECK-LABEL: buildvec_mask_v4i1: ; CHECK-LABEL: buildvec_mask_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 6 ; CHECK-NEXT: li a0, 6
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v4i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 6
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v4i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 6
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v4i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 6
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v4i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 6
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v4i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 6
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v4i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 6
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: ret
ret <4 x i1> <i1 0, i1 1, i1 1, i1 0> ret <4 x i1> <i1 0, i1 1, i1 1, i1 0>
} }
define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) { define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v4i1: ; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 3 ; CHECK-NEXT: li a2, 3
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a2 ; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a2, 3
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a2
; RV32-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.v.x v8, a1
; RV32-ELEN32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a2, 3
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a2
; RV64-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.v.x v8, a1
; RV64-ELEN32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a2, 3
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a2
; RV32-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.v.x v8, a1
; RV32-ELEN16-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a2, 3
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a2
; RV64-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.v.x v8, a1
; RV64-ELEN16-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a2, 3
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a2
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.v.x v8, a1
; RV32-ELEN8-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a2, 3
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a2
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.v.x v8, a1
; RV64-ELEN8-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 %x, i32 0 %1 = insertelement <4 x i1> undef, i1 %x, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1 %2 = insertelement <4 x i1> %1, i1 %x, i32 1
%3 = insertelement <4 x i1> %2, i1 %y, i32 2 %3 = insertelement <4 x i1> %2, i1 %y, i32 2
%4 = insertelement <4 x i1> %3, i1 %y, i32 3 %4 = insertelement <4 x i1> %3, i1 %y, i32 3
ret <4 x i1> %4 ret <4 x i1> %4
} }
; FIXME: optsize isn't smaller than the code above ; FIXME: optsize isn't smaller than the code above
define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize { define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize {
; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1: ; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: sb a1, 14(sp) ; CHECK-NEXT: sb a1, 14(sp)
; CHECK-NEXT: sb a0, 13(sp) ; CHECK-NEXT: sb a0, 13(sp)
; CHECK-NEXT: sb a0, 12(sp) ; CHECK-NEXT: sb a0, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12 ; CHECK-NEXT: addi a0, sp, 12
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a1, 15(sp)
; RV32-ELEN32-NEXT: sb a1, 14(sp)
; RV32-ELEN32-NEXT: sb a0, 13(sp)
; RV32-ELEN32-NEXT: sb a0, 12(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 12
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a1, 15(sp)
; RV64-ELEN32-NEXT: sb a1, 14(sp)
; RV64-ELEN32-NEXT: sb a0, 13(sp)
; RV64-ELEN32-NEXT: sb a0, 12(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 12
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a1, 15(sp)
; RV32-ELEN16-NEXT: sb a1, 14(sp)
; RV32-ELEN16-NEXT: sb a0, 13(sp)
; RV32-ELEN16-NEXT: sb a0, 12(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 12
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a1, 15(sp)
; RV64-ELEN16-NEXT: sb a1, 14(sp)
; RV64-ELEN16-NEXT: sb a0, 13(sp)
; RV64-ELEN16-NEXT: sb a0, 12(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 12
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a1, 15(sp)
; RV32-ELEN8-NEXT: sb a1, 14(sp)
; RV32-ELEN8-NEXT: sb a0, 13(sp)
; RV32-ELEN8-NEXT: sb a0, 12(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 12
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v4i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a1, 15(sp)
; RV64-ELEN8-NEXT: sb a1, 14(sp)
; RV64-ELEN8-NEXT: sb a0, 13(sp)
; RV64-ELEN8-NEXT: sb a0, 12(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 12
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 %x, i32 0 %1 = insertelement <4 x i1> undef, i1 %x, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1 %2 = insertelement <4 x i1> %1, i1 %x, i32 1
%3 = insertelement <4 x i1> %2, i1 %y, i32 2 %3 = insertelement <4 x i1> %2, i1 %y, i32 2
%4 = insertelement <4 x i1> %3, i1 %y, i32 3 %4 = insertelement <4 x i1> %3, i1 %y, i32 3
ret <4 x i1> %4 ret <4 x i1> %4
} }
define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) { define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2: ; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: sb a1, 15(sp) ; CHECK-NEXT: sb a1, 15(sp)
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sb a1, 14(sp) ; CHECK-NEXT: sb a1, 14(sp)
; CHECK-NEXT: sb a0, 13(sp) ; CHECK-NEXT: sb a0, 13(sp)
; CHECK-NEXT: sb zero, 12(sp) ; CHECK-NEXT: sb zero, 12(sp)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 12 ; CHECK-NEXT: addi a0, sp, 12
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a1, 15(sp)
; RV32-ELEN32-NEXT: li a1, 1
; RV32-ELEN32-NEXT: sb a1, 14(sp)
; RV32-ELEN32-NEXT: sb a0, 13(sp)
; RV32-ELEN32-NEXT: sb zero, 12(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 12
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a1, 15(sp)
; RV64-ELEN32-NEXT: li a1, 1
; RV64-ELEN32-NEXT: sb a1, 14(sp)
; RV64-ELEN32-NEXT: sb a0, 13(sp)
; RV64-ELEN32-NEXT: sb zero, 12(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 12
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a1, 15(sp)
; RV32-ELEN16-NEXT: li a1, 1
; RV32-ELEN16-NEXT: sb a1, 14(sp)
; RV32-ELEN16-NEXT: sb a0, 13(sp)
; RV32-ELEN16-NEXT: sb zero, 12(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 12
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a1, 15(sp)
; RV64-ELEN16-NEXT: li a1, 1
; RV64-ELEN16-NEXT: sb a1, 14(sp)
; RV64-ELEN16-NEXT: sb a0, 13(sp)
; RV64-ELEN16-NEXT: sb zero, 12(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 12
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a1, 15(sp)
; RV32-ELEN8-NEXT: li a1, 1
; RV32-ELEN8-NEXT: sb a1, 14(sp)
; RV32-ELEN8-NEXT: sb a0, 13(sp)
; RV32-ELEN8-NEXT: sb zero, 12(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 12
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v4i1_2:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a1, 15(sp)
; RV64-ELEN8-NEXT: li a1, 1
; RV64-ELEN8-NEXT: sb a1, 14(sp)
; RV64-ELEN8-NEXT: sb a0, 13(sp)
; RV64-ELEN8-NEXT: sb zero, 12(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 12
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <4 x i1> undef, i1 0, i32 0 %1 = insertelement <4 x i1> undef, i1 0, i32 0
%2 = insertelement <4 x i1> %1, i1 %x, i32 1 %2 = insertelement <4 x i1> %1, i1 %x, i32 1
%3 = insertelement <4 x i1> %2, i1 1, i32 2 %3 = insertelement <4 x i1> %2, i1 1, i32 2
%4 = insertelement <4 x i1> %3, i1 %y, i32 3 %4 = insertelement <4 x i1> %3, i1 %y, i32 3
ret <4 x i1> %4 ret <4 x i1> %4
} }
define <8 x i1> @buildvec_mask_v8i1() { define <8 x i1> @buildvec_mask_v8i1() {
; CHECK-LABEL: buildvec_mask_v8i1: ; CHECK-LABEL: buildvec_mask_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 182 ; CHECK-NEXT: li a0, 182
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v8i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 182
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v8i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 182
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v8i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 182
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v8i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 182
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v8i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 182
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v8i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 182
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: ret
ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
} }
define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) { define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v8i1: ; CHECK-LABEL: buildvec_mask_nonconst_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 19 ; CHECK-NEXT: li a2, 19
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; CHECK-NEXT: vmv.s.x v0, a2 ; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a2, 19
; RV32-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a2
; RV32-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN32-NEXT: vmv.v.x v8, a1
; RV32-ELEN32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a2, 19
; RV64-ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a2
; RV64-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN32-NEXT: vmv.v.x v8, a1
; RV64-ELEN32-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a2, 19
; RV32-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a2
; RV32-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: vmv.v.x v8, a1
; RV32-ELEN16-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a2, 19
; RV64-ELEN16-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a2
; RV64-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: vmv.v.x v8, a1
; RV64-ELEN16-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a2, 19
; RV32-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v0, a2
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.v.x v8, a1
; RV32-ELEN8-NEXT: vmerge.vxm v8, v8, a0, v0
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a2, 19
; RV64-ELEN8-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v0, a2
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.v.x v8, a1
; RV64-ELEN8-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0 %1 = insertelement <8 x i1> undef, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 %y, i32 2 %3 = insertelement <8 x i1> %2, i1 %y, i32 2
%4 = insertelement <8 x i1> %3, i1 %y, i32 3 %4 = insertelement <8 x i1> %3, i1 %y, i32 3
%5 = insertelement <8 x i1> %4, i1 %x, i32 4 %5 = insertelement <8 x i1> %4, i1 %x, i32 4
%6 = insertelement <8 x i1> %5, i1 %y, i32 5 %6 = insertelement <8 x i1> %5, i1 %y, i32 5
%7 = insertelement <8 x i1> %6, i1 %y, i32 6 %7 = insertelement <8 x i1> %6, i1 %y, i32 6
%8 = insertelement <8 x i1> %7, i1 %y, i32 7 %8 = insertelement <8 x i1> %7, i1 %y, i32 7
Show All 16 Lines
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a2, 15(sp)
; RV32-ELEN32-NEXT: sb zero, 14(sp)
; RV32-ELEN32-NEXT: sb a3, 13(sp)
; RV32-ELEN32-NEXT: sb a0, 12(sp)
; RV32-ELEN32-NEXT: sb a1, 11(sp)
; RV32-ELEN32-NEXT: li a1, 1
; RV32-ELEN32-NEXT: sb a1, 10(sp)
; RV32-ELEN32-NEXT: sb a0, 9(sp)
; RV32-ELEN32-NEXT: sb a0, 8(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 8
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a2, 15(sp)
; RV64-ELEN32-NEXT: sb zero, 14(sp)
; RV64-ELEN32-NEXT: sb a3, 13(sp)
; RV64-ELEN32-NEXT: sb a0, 12(sp)
; RV64-ELEN32-NEXT: sb a1, 11(sp)
; RV64-ELEN32-NEXT: li a1, 1
; RV64-ELEN32-NEXT: sb a1, 10(sp)
; RV64-ELEN32-NEXT: sb a0, 9(sp)
; RV64-ELEN32-NEXT: sb a0, 8(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 8
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a2, 15(sp)
; RV32-ELEN16-NEXT: sb zero, 14(sp)
; RV32-ELEN16-NEXT: sb a3, 13(sp)
; RV32-ELEN16-NEXT: sb a0, 12(sp)
; RV32-ELEN16-NEXT: sb a1, 11(sp)
; RV32-ELEN16-NEXT: li a1, 1
; RV32-ELEN16-NEXT: sb a1, 10(sp)
; RV32-ELEN16-NEXT: sb a0, 9(sp)
; RV32-ELEN16-NEXT: sb a0, 8(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 8
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a2, 15(sp)
; RV64-ELEN16-NEXT: sb zero, 14(sp)
; RV64-ELEN16-NEXT: sb a3, 13(sp)
; RV64-ELEN16-NEXT: sb a0, 12(sp)
; RV64-ELEN16-NEXT: sb a1, 11(sp)
; RV64-ELEN16-NEXT: li a1, 1
; RV64-ELEN16-NEXT: sb a1, 10(sp)
; RV64-ELEN16-NEXT: sb a0, 9(sp)
; RV64-ELEN16-NEXT: sb a0, 8(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 8
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a2, 15(sp)
; RV32-ELEN8-NEXT: sb zero, 14(sp)
; RV32-ELEN8-NEXT: sb a3, 13(sp)
; RV32-ELEN8-NEXT: sb a0, 12(sp)
; RV32-ELEN8-NEXT: sb a1, 11(sp)
; RV32-ELEN8-NEXT: li a1, 1
; RV32-ELEN8-NEXT: sb a1, 10(sp)
; RV32-ELEN8-NEXT: sb a0, 9(sp)
; RV32-ELEN8-NEXT: sb a0, 8(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 8
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v8i1_2:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a2, 15(sp)
; RV64-ELEN8-NEXT: sb zero, 14(sp)
; RV64-ELEN8-NEXT: sb a3, 13(sp)
; RV64-ELEN8-NEXT: sb a0, 12(sp)
; RV64-ELEN8-NEXT: sb a1, 11(sp)
; RV64-ELEN8-NEXT: li a1, 1
; RV64-ELEN8-NEXT: sb a1, 10(sp)
; RV64-ELEN8-NEXT: sb a0, 9(sp)
; RV64-ELEN8-NEXT: sb a0, 8(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 8
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0 %1 = insertelement <8 x i1> undef, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 1, i32 2 %3 = insertelement <8 x i1> %2, i1 1, i32 2
%4 = insertelement <8 x i1> %3, i1 %y, i32 3 %4 = insertelement <8 x i1> %3, i1 %y, i32 3
%5 = insertelement <8 x i1> %4, i1 %x, i32 4 %5 = insertelement <8 x i1> %4, i1 %x, i32 4
%6 = insertelement <8 x i1> %5, i1 %w, i32 5 %6 = insertelement <8 x i1> %5, i1 %w, i32 5
%7 = insertelement <8 x i1> %6, i1 0, i32 6 %7 = insertelement <8 x i1> %6, i1 0, i32 6
%8 = insertelement <8 x i1> %7, i1 %z, i32 7 %8 = insertelement <8 x i1> %7, i1 %z, i32 7
Show All 16 Lines
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a2, 15(sp)
; RV32-ELEN32-NEXT: sb zero, 14(sp)
; RV32-ELEN32-NEXT: sb a3, 13(sp)
; RV32-ELEN32-NEXT: sb a0, 12(sp)
; RV32-ELEN32-NEXT: sb a1, 11(sp)
; RV32-ELEN32-NEXT: li a1, 1
; RV32-ELEN32-NEXT: sb a1, 10(sp)
; RV32-ELEN32-NEXT: sb a0, 9(sp)
; RV32-ELEN32-NEXT: sb a0, 8(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 8
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a2, 15(sp)
; RV64-ELEN32-NEXT: sb zero, 14(sp)
; RV64-ELEN32-NEXT: sb a3, 13(sp)
; RV64-ELEN32-NEXT: sb a0, 12(sp)
; RV64-ELEN32-NEXT: sb a1, 11(sp)
; RV64-ELEN32-NEXT: li a1, 1
; RV64-ELEN32-NEXT: sb a1, 10(sp)
; RV64-ELEN32-NEXT: sb a0, 9(sp)
; RV64-ELEN32-NEXT: sb a0, 8(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 8
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a2, 15(sp)
; RV32-ELEN16-NEXT: sb zero, 14(sp)
; RV32-ELEN16-NEXT: sb a3, 13(sp)
; RV32-ELEN16-NEXT: sb a0, 12(sp)
; RV32-ELEN16-NEXT: sb a1, 11(sp)
; RV32-ELEN16-NEXT: li a1, 1
; RV32-ELEN16-NEXT: sb a1, 10(sp)
; RV32-ELEN16-NEXT: sb a0, 9(sp)
; RV32-ELEN16-NEXT: sb a0, 8(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 8
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a2, 15(sp)
; RV64-ELEN16-NEXT: sb zero, 14(sp)
; RV64-ELEN16-NEXT: sb a3, 13(sp)
; RV64-ELEN16-NEXT: sb a0, 12(sp)
; RV64-ELEN16-NEXT: sb a1, 11(sp)
; RV64-ELEN16-NEXT: li a1, 1
; RV64-ELEN16-NEXT: sb a1, 10(sp)
; RV64-ELEN16-NEXT: sb a0, 9(sp)
; RV64-ELEN16-NEXT: sb a0, 8(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 8
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a2, 15(sp)
; RV32-ELEN8-NEXT: sb zero, 14(sp)
; RV32-ELEN8-NEXT: sb a3, 13(sp)
; RV32-ELEN8-NEXT: sb a0, 12(sp)
; RV32-ELEN8-NEXT: sb a1, 11(sp)
; RV32-ELEN8-NEXT: li a1, 1
; RV32-ELEN8-NEXT: sb a1, 10(sp)
; RV32-ELEN8-NEXT: sb a0, 9(sp)
; RV32-ELEN8-NEXT: sb a0, 8(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 8
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v8i1_2:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a2, 15(sp)
; RV64-ELEN8-NEXT: sb zero, 14(sp)
; RV64-ELEN8-NEXT: sb a3, 13(sp)
; RV64-ELEN8-NEXT: sb a0, 12(sp)
; RV64-ELEN8-NEXT: sb a1, 11(sp)
; RV64-ELEN8-NEXT: li a1, 1
; RV64-ELEN8-NEXT: sb a1, 10(sp)
; RV64-ELEN8-NEXT: sb a0, 9(sp)
; RV64-ELEN8-NEXT: sb a0, 8(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 8
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0 %1 = insertelement <8 x i1> undef, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 1, i32 2 %3 = insertelement <8 x i1> %2, i1 1, i32 2
%4 = insertelement <8 x i1> %3, i1 %y, i32 3 %4 = insertelement <8 x i1> %3, i1 %y, i32 3
%5 = insertelement <8 x i1> %4, i1 %x, i32 4 %5 = insertelement <8 x i1> %4, i1 %x, i32 4
%6 = insertelement <8 x i1> %5, i1 %w, i32 5 %6 = insertelement <8 x i1> %5, i1 %w, i32 5
%7 = insertelement <8 x i1> %6, i1 0, i32 6 %7 = insertelement <8 x i1> %6, i1 0, i32 6
%8 = insertelement <8 x i1> %7, i1 %z, i32 7 %8 = insertelement <8 x i1> %7, i1 %z, i32 7
Show All 15 Lines
; CHECK-NEXT: sb a0, 8(sp) ; CHECK-NEXT: sb a0, 8(sp)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: addi sp, sp, -16
; RV32-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN32-NEXT: sb a1, 15(sp)
; RV32-ELEN32-NEXT: sb a1, 14(sp)
; RV32-ELEN32-NEXT: sb a1, 13(sp)
; RV32-ELEN32-NEXT: sb a0, 12(sp)
; RV32-ELEN32-NEXT: sb a1, 11(sp)
; RV32-ELEN32-NEXT: sb a1, 10(sp)
; RV32-ELEN32-NEXT: sb a0, 9(sp)
; RV32-ELEN32-NEXT: sb a0, 8(sp)
; RV32-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN32-NEXT: addi a0, sp, 8
; RV32-ELEN32-NEXT: vle8.v v8, (a0)
; RV32-ELEN32-NEXT: vand.vi v8, v8, 1
; RV32-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN32-NEXT: addi sp, sp, 16
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: addi sp, sp, -16
; RV64-ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN32-NEXT: sb a1, 15(sp)
; RV64-ELEN32-NEXT: sb a1, 14(sp)
; RV64-ELEN32-NEXT: sb a1, 13(sp)
; RV64-ELEN32-NEXT: sb a0, 12(sp)
; RV64-ELEN32-NEXT: sb a1, 11(sp)
; RV64-ELEN32-NEXT: sb a1, 10(sp)
; RV64-ELEN32-NEXT: sb a0, 9(sp)
; RV64-ELEN32-NEXT: sb a0, 8(sp)
; RV64-ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN32-NEXT: addi a0, sp, 8
; RV64-ELEN32-NEXT: vle8.v v8, (a0)
; RV64-ELEN32-NEXT: vand.vi v8, v8, 1
; RV64-ELEN32-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN32-NEXT: addi sp, sp, 16
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: addi sp, sp, -16
; RV32-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN16-NEXT: sb a1, 15(sp)
; RV32-ELEN16-NEXT: sb a1, 14(sp)
; RV32-ELEN16-NEXT: sb a1, 13(sp)
; RV32-ELEN16-NEXT: sb a0, 12(sp)
; RV32-ELEN16-NEXT: sb a1, 11(sp)
; RV32-ELEN16-NEXT: sb a1, 10(sp)
; RV32-ELEN16-NEXT: sb a0, 9(sp)
; RV32-ELEN16-NEXT: sb a0, 8(sp)
; RV32-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ELEN16-NEXT: addi a0, sp, 8
; RV32-ELEN16-NEXT: vle8.v v8, (a0)
; RV32-ELEN16-NEXT: vand.vi v8, v8, 1
; RV32-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN16-NEXT: addi sp, sp, 16
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: addi sp, sp, -16
; RV64-ELEN16-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN16-NEXT: sb a1, 15(sp)
; RV64-ELEN16-NEXT: sb a1, 14(sp)
; RV64-ELEN16-NEXT: sb a1, 13(sp)
; RV64-ELEN16-NEXT: sb a0, 12(sp)
; RV64-ELEN16-NEXT: sb a1, 11(sp)
; RV64-ELEN16-NEXT: sb a1, 10(sp)
; RV64-ELEN16-NEXT: sb a0, 9(sp)
; RV64-ELEN16-NEXT: sb a0, 8(sp)
; RV64-ELEN16-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-ELEN16-NEXT: addi a0, sp, 8
; RV64-ELEN16-NEXT: vle8.v v8, (a0)
; RV64-ELEN16-NEXT: vand.vi v8, v8, 1
; RV64-ELEN16-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN16-NEXT: addi sp, sp, 16
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: addi sp, sp, -16
; RV32-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV32-ELEN8-NEXT: sb a1, 15(sp)
; RV32-ELEN8-NEXT: sb a1, 14(sp)
; RV32-ELEN8-NEXT: sb a1, 13(sp)
; RV32-ELEN8-NEXT: sb a0, 12(sp)
; RV32-ELEN8-NEXT: sb a1, 11(sp)
; RV32-ELEN8-NEXT: sb a1, 10(sp)
; RV32-ELEN8-NEXT: sb a0, 9(sp)
; RV32-ELEN8-NEXT: sb a0, 8(sp)
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: addi a0, sp, 8
; RV32-ELEN8-NEXT: vle8.v v8, (a0)
; RV32-ELEN8-NEXT: vand.vi v8, v8, 1
; RV32-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV32-ELEN8-NEXT: addi sp, sp, 16
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_optsize_nonconst_v8i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: addi sp, sp, -16
; RV64-ELEN8-NEXT: .cfi_def_cfa_offset 16
; RV64-ELEN8-NEXT: sb a1, 15(sp)
; RV64-ELEN8-NEXT: sb a1, 14(sp)
; RV64-ELEN8-NEXT: sb a1, 13(sp)
; RV64-ELEN8-NEXT: sb a0, 12(sp)
; RV64-ELEN8-NEXT: sb a1, 11(sp)
; RV64-ELEN8-NEXT: sb a1, 10(sp)
; RV64-ELEN8-NEXT: sb a0, 9(sp)
; RV64-ELEN8-NEXT: sb a0, 8(sp)
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: addi a0, sp, 8
; RV64-ELEN8-NEXT: vle8.v v8, (a0)
; RV64-ELEN8-NEXT: vand.vi v8, v8, 1
; RV64-ELEN8-NEXT: vmsne.vi v0, v8, 0
; RV64-ELEN8-NEXT: addi sp, sp, 16
; RV64-ELEN8-NEXT: ret
%1 = insertelement <8 x i1> undef, i1 %x, i32 0 %1 = insertelement <8 x i1> undef, i1 %x, i32 0
%2 = insertelement <8 x i1> %1, i1 %x, i32 1 %2 = insertelement <8 x i1> %1, i1 %x, i32 1
%3 = insertelement <8 x i1> %2, i1 %y, i32 2 %3 = insertelement <8 x i1> %2, i1 %y, i32 2
%4 = insertelement <8 x i1> %3, i1 %y, i32 3 %4 = insertelement <8 x i1> %3, i1 %y, i32 3
%5 = insertelement <8 x i1> %4, i1 %x, i32 4 %5 = insertelement <8 x i1> %4, i1 %x, i32 4
%6 = insertelement <8 x i1> %5, i1 %y, i32 5 %6 = insertelement <8 x i1> %5, i1 %y, i32 5
%7 = insertelement <8 x i1> %6, i1 %y, i32 6 %7 = insertelement <8 x i1> %6, i1 %y, i32 6
%8 = insertelement <8 x i1> %7, i1 %y, i32 7 %8 = insertelement <8 x i1> %7, i1 %y, i32 7
ret <8 x i1> %8 ret <8 x i1> %8
} }
define <10 x i1> @buildvec_mask_v10i1() { define <10 x i1> @buildvec_mask_v10i1() {
; CHECK-LABEL: buildvec_mask_v10i1: ; CHECK-LABEL: buildvec_mask_v10i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 949 ; CHECK-NEXT: li a0, 949
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v10i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 949
; RV32-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v10i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 949
; RV64-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v10i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 949
; RV32-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v10i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 949
; RV64-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v10i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 3
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: li a0, 181
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v10i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 3
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: li a0, 181
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: ret
ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1> ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1>
} }
define <16 x i1> @buildvec_mask_v16i1() { define <16 x i1> @buildvec_mask_v16i1() {
; CHECK-RV32-LABEL: buildvec_mask_v16i1: ; CHECK-RV32-LABEL: buildvec_mask_v16i1:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: lui a0, 11 ; CHECK-RV32-NEXT: lui a0, 11
; CHECK-RV32-NEXT: addi a0, a0, 1718 ; CHECK-RV32-NEXT: addi a0, a0, 1718
; CHECK-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-RV32-NEXT: vmv.s.x v0, a0 ; CHECK-RV32-NEXT: vmv.s.x v0, a0
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: buildvec_mask_v16i1: ; CHECK-RV64-LABEL: buildvec_mask_v16i1:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lui a0, 11 ; CHECK-RV64-NEXT: lui a0, 11
; CHECK-RV64-NEXT: addiw a0, a0, 1718 ; CHECK-RV64-NEXT: addiw a0, a0, 1718
; CHECK-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-RV64-NEXT: vmv.s.x v0, a0 ; CHECK-RV64-NEXT: vmv.s.x v0, a0
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v16i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: lui a0, 11
; RV32-ELEN32-NEXT: addi a0, a0, 1718
; RV32-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v16i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: lui a0, 11
; RV64-ELEN32-NEXT: addiw a0, a0, 1718
; RV64-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v16i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: lui a0, 11
; RV32-ELEN16-NEXT: addi a0, a0, 1718
; RV32-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v16i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: lui a0, 11
; RV64-ELEN16-NEXT: addiw a0, a0, 1718
; RV64-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v16i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 182
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vmv.v.v v0, v8
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v16i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 182
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vmv.v.v v0, v8
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: ret
ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
} }
define <16 x i1> @buildvec_mask_v16i1_undefs() { define <16 x i1> @buildvec_mask_v16i1_undefs() {
; CHECK-LABEL: buildvec_mask_v16i1_undefs: ; CHECK-LABEL: buildvec_mask_v16i1_undefs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 1722 ; CHECK-NEXT: li a0, 1722
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vmv.s.x v0, a0 ; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v16i1_undefs:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: li a0, 1722
; RV32-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v16i1_undefs:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: li a0, 1722
; RV64-ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v16i1_undefs:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 1722
; RV32-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v16i1_undefs:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 1722
; RV64-ELEN16-NEXT: vsetivli zero, 1, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v16i1_undefs:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 6
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: li a0, 186
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v16i1_undefs:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 6
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: li a0, 186
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: ret
ret <16 x i1> <i1 undef, i1 1, i1 undef, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef> ret <16 x i1> <i1 undef, i1 1, i1 undef, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>
} }
define <32 x i1> @buildvec_mask_v32i1() { define <32 x i1> @buildvec_mask_v32i1() {
; RV32-LMULMAX1-LABEL: buildvec_mask_v32i1: ; RV32-LMULMAX1-LABEL: buildvec_mask_v32i1:
; RV32-LMULMAX1: # %bb.0: ; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776 ; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; ;
; RV64-LMULMAX8-LABEL: buildvec_mask_v32i1: ; RV64-LMULMAX8-LABEL: buildvec_mask_v32i1:
; RV64-LMULMAX8: # %bb.0: ; RV64-LMULMAX8: # %bb.0:
; RV64-LMULMAX8-NEXT: lui a0, 748384 ; RV64-LMULMAX8-NEXT: lui a0, 748384
; RV64-LMULMAX8-NEXT: addiw a0, a0, 1776 ; RV64-LMULMAX8-NEXT: addiw a0, a0, 1776
; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX8-NEXT: ret ; RV64-LMULMAX8-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v32i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: lui a0, 748384
; RV32-ELEN32-NEXT: addi a0, a0, 1776
; RV32-ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v32i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: lui a0, 748384
; RV64-ELEN32-NEXT: addiw a0, a0, 1776
; RV64-ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v32i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 1776
; RV32-ELEN16-NEXT: vsetivli zero, 2, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: lui a0, 11
; RV32-ELEN16-NEXT: addi a0, a0, 1718
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v32i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 1776
; RV64-ELEN16-NEXT: vsetivli zero, 2, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: lui a0, 11
; RV64-ELEN16-NEXT: addiw a0, a0, 1718
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v32i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 6
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: li a0, 240
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: li a0, 182
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 2
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 3
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v32i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 6
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: li a0, 240
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: li a0, 182
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 2
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 3
; RV64-ELEN8-NEXT: ret
ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
} }
define <64 x i1> @buildvec_mask_v64i1() { define <64 x i1> @buildvec_mask_v64i1() {
; RV32-LMULMAX1-LABEL: buildvec_mask_v64i1: ; RV32-LMULMAX1-LABEL: buildvec_mask_v64i1:
; RV32-LMULMAX1: # %bb.0: ; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776 ; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
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; ;
; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1: ; RV64-LMULMAX8-LABEL: buildvec_mask_v64i1:
; RV64-LMULMAX8: # %bb.0: ; RV64-LMULMAX8: # %bb.0:
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI19_0) ; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI19_0)
; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI19_0)(a0) ; RV64-LMULMAX8-NEXT: ld a0, %lo(.LCPI19_0)(a0)
; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e64, m1, ta, mu ; RV64-LMULMAX8-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0 ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a0
; RV64-LMULMAX8-NEXT: ret ; RV64-LMULMAX8-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v64i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: lui a0, 748388
; RV32-ELEN32-NEXT: addi a0, a0, -1793
; RV32-ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v8, a0
; RV32-ELEN32-NEXT: lui a0, 748384
; RV32-ELEN32-NEXT: addi a0, a0, 1776
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-ELEN32-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v64i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: lui a0, 748388
; RV64-ELEN32-NEXT: addiw a0, a0, -1793
; RV64-ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v8, a0
; RV64-ELEN32-NEXT: lui a0, 748384
; RV64-ELEN32-NEXT: addiw a0, a0, 1776
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV64-ELEN32-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v64i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 1776
; RV32-ELEN16-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v0, a0
; RV32-ELEN16-NEXT: lui a0, 11
; RV32-ELEN16-NEXT: addi a0, a0, 1718
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN16-NEXT: lui a0, 4
; RV32-ELEN16-NEXT: addi a0, a0, -1793
; RV32-ELEN16-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v9, a0
; RV32-ELEN16-NEXT: vsetivli zero, 3, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v9, 2
; RV32-ELEN16-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 3
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v64i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 1776
; RV64-ELEN16-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v0, a0
; RV64-ELEN16-NEXT: lui a0, 11
; RV64-ELEN16-NEXT: addiw a0, a0, 1718
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN16-NEXT: lui a0, 4
; RV64-ELEN16-NEXT: addiw a0, a0, -1793
; RV64-ELEN16-NEXT: vsetivli zero, 4, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v9, a0
; RV64-ELEN16-NEXT: vsetivli zero, 3, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v9, 2
; RV64-ELEN16-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 3
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v64i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 6
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: li a0, 240
; RV32-ELEN8-NEXT: vmv.s.x v0, a0
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: li a0, 182
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 2
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 3
; RV32-ELEN8-NEXT: li a0, 255
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v9, a0
; RV32-ELEN8-NEXT: vsetivli zero, 5, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v9, 4
; RV32-ELEN8-NEXT: li a0, 56
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v9, a0
; RV32-ELEN8-NEXT: vsetivli zero, 6, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v9, 5
; RV32-ELEN8-NEXT: vsetivli zero, 7, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 6
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 7
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v64i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 6
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: li a0, 240
; RV64-ELEN8-NEXT: vmv.s.x v0, a0
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: li a0, 182
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 2
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 3
; RV64-ELEN8-NEXT: li a0, 255
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v9, a0
; RV64-ELEN8-NEXT: vsetivli zero, 5, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v9, 4
; RV64-ELEN8-NEXT: li a0, 56
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v9, a0
; RV64-ELEN8-NEXT: vsetivli zero, 6, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v9, 5
; RV64-ELEN8-NEXT: vsetivli zero, 7, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 6
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 7
; RV64-ELEN8-NEXT: ret
ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
} }
define <128 x i1> @buildvec_mask_v128i1() { define <128 x i1> @buildvec_mask_v128i1() {
; RV32-LMULMAX1-LABEL: buildvec_mask_v128i1: ; RV32-LMULMAX1-LABEL: buildvec_mask_v128i1:
; RV32-LMULMAX1: # %bb.0: ; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776 ; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
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; RV64-LMULMAX8-NEXT: lui a1, %hi(.LCPI20_1) ; RV64-LMULMAX8-NEXT: lui a1, %hi(.LCPI20_1)
; RV64-LMULMAX8-NEXT: ld a1, %lo(.LCPI20_1)(a1) ; RV64-LMULMAX8-NEXT: ld a1, %lo(.LCPI20_1)(a1)
; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; RV64-LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0 ; RV64-LMULMAX8-NEXT: vmv.s.x v8, a0
; RV64-LMULMAX8-NEXT: vmv.s.x v0, a1 ; RV64-LMULMAX8-NEXT: vmv.s.x v0, a1
; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV64-LMULMAX8-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1 ; RV64-LMULMAX8-NEXT: vslideup.vi v0, v8, 1
; RV64-LMULMAX8-NEXT: ret ; RV64-LMULMAX8-NEXT: ret
;
; RV32-ELEN32-LABEL: buildvec_mask_v128i1:
; RV32-ELEN32: # %bb.0:
; RV32-ELEN32-NEXT: lui a0, 748388
; RV32-ELEN32-NEXT: addi a0, a0, -1793
; RV32-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v8, a0
; RV32-ELEN32-NEXT: lui a0, 748384
; RV32-ELEN32-NEXT: addi a0, a0, 1776
; RV32-ELEN32-NEXT: vmv.s.x v0, a0
; RV32-ELEN32-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; RV32-ELEN32-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN32-NEXT: lui a0, 551776
; RV32-ELEN32-NEXT: addi a0, a0, 1776
; RV32-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v8, a0
; RV32-ELEN32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
; RV32-ELEN32-NEXT: vslideup.vi v0, v8, 2
; RV32-ELEN32-NEXT: lui a0, 945060
; RV32-ELEN32-NEXT: addi a0, a0, -1793
; RV32-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-ELEN32-NEXT: vmv.s.x v8, a0
; RV32-ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV32-ELEN32-NEXT: vslideup.vi v0, v8, 3
; RV32-ELEN32-NEXT: ret
;
; RV64-ELEN32-LABEL: buildvec_mask_v128i1:
; RV64-ELEN32: # %bb.0:
; RV64-ELEN32-NEXT: lui a0, 748388
; RV64-ELEN32-NEXT: addiw a0, a0, -1793
; RV64-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v8, a0
; RV64-ELEN32-NEXT: lui a0, 748384
; RV64-ELEN32-NEXT: addiw a0, a0, 1776
; RV64-ELEN32-NEXT: vmv.s.x v0, a0
; RV64-ELEN32-NEXT: vsetivli zero, 2, e32, m1, tu, mu
; RV64-ELEN32-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN32-NEXT: lui a0, 551776
; RV64-ELEN32-NEXT: addiw a0, a0, 1776
; RV64-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v8, a0
; RV64-ELEN32-NEXT: vsetivli zero, 3, e32, m1, tu, mu
; RV64-ELEN32-NEXT: vslideup.vi v0, v8, 2
; RV64-ELEN32-NEXT: lui a0, 945060
; RV64-ELEN32-NEXT: addiw a0, a0, -1793
; RV64-ELEN32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-ELEN32-NEXT: vmv.s.x v8, a0
; RV64-ELEN32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
; RV64-ELEN32-NEXT: vslideup.vi v0, v8, 3
; RV64-ELEN32-NEXT: ret
;
; RV32-ELEN16-LABEL: buildvec_mask_v128i1:
; RV32-ELEN16: # %bb.0:
; RV32-ELEN16-NEXT: li a0, 1776
; RV32-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: lui a0, 11
; RV32-ELEN16-NEXT: addi a0, a0, 1718
; RV32-ELEN16-NEXT: vmv.s.x v9, a0
; RV32-ELEN16-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vmv1r.v v0, v8
; RV32-ELEN16-NEXT: vslideup.vi v0, v9, 1
; RV32-ELEN16-NEXT: lui a0, 4
; RV32-ELEN16-NEXT: addi a0, a0, -1793
; RV32-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v10, a0
; RV32-ELEN16-NEXT: vsetivli zero, 3, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v10, 2
; RV32-ELEN16-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v9, 3
; RV32-ELEN16-NEXT: vsetivli zero, 5, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 4
; RV32-ELEN16-NEXT: lui a0, 8
; RV32-ELEN16-NEXT: addi a0, a0, 1718
; RV32-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 5
; RV32-ELEN16-NEXT: vsetivli zero, 7, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v10, 6
; RV32-ELEN16-NEXT: lui a0, 14
; RV32-ELEN16-NEXT: addi a0, a0, 1722
; RV32-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-ELEN16-NEXT: vmv.s.x v8, a0
; RV32-ELEN16-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; RV32-ELEN16-NEXT: vslideup.vi v0, v8, 7
; RV32-ELEN16-NEXT: ret
;
; RV64-ELEN16-LABEL: buildvec_mask_v128i1:
; RV64-ELEN16: # %bb.0:
; RV64-ELEN16-NEXT: li a0, 1776
; RV64-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: lui a0, 11
; RV64-ELEN16-NEXT: addiw a0, a0, 1718
; RV64-ELEN16-NEXT: vmv.s.x v9, a0
; RV64-ELEN16-NEXT: vsetivli zero, 2, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vmv1r.v v0, v8
; RV64-ELEN16-NEXT: vslideup.vi v0, v9, 1
; RV64-ELEN16-NEXT: lui a0, 4
; RV64-ELEN16-NEXT: addiw a0, a0, -1793
; RV64-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v10, a0
; RV64-ELEN16-NEXT: vsetivli zero, 3, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v10, 2
; RV64-ELEN16-NEXT: vsetivli zero, 4, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v9, 3
; RV64-ELEN16-NEXT: vsetivli zero, 5, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 4
; RV64-ELEN16-NEXT: lui a0, 8
; RV64-ELEN16-NEXT: addiw a0, a0, 1718
; RV64-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: vsetivli zero, 6, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 5
; RV64-ELEN16-NEXT: vsetivli zero, 7, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v10, 6
; RV64-ELEN16-NEXT: lui a0, 14
; RV64-ELEN16-NEXT: addiw a0, a0, 1722
; RV64-ELEN16-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64-ELEN16-NEXT: vmv.s.x v8, a0
; RV64-ELEN16-NEXT: vsetvli zero, zero, e16, m1, tu, mu
; RV64-ELEN16-NEXT: vslideup.vi v0, v8, 7
; RV64-ELEN16-NEXT: ret
;
; RV32-ELEN8-LABEL: buildvec_mask_v128i1:
; RV32-ELEN8: # %bb.0:
; RV32-ELEN8-NEXT: li a0, 6
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: li a0, 240
; RV32-ELEN8-NEXT: vmv.s.x v9, a0
; RV32-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vmv1r.v v0, v9
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV32-ELEN8-NEXT: li a0, 182
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v10, a0
; RV32-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v10, 2
; RV32-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v10, 3
; RV32-ELEN8-NEXT: li a0, 255
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v11, a0
; RV32-ELEN8-NEXT: vsetivli zero, 5, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v11, 4
; RV32-ELEN8-NEXT: li a0, 56
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v12, a0
; RV32-ELEN8-NEXT: vsetivli zero, 6, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v12, 5
; RV32-ELEN8-NEXT: vsetivli zero, 7, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v10, 6
; RV32-ELEN8-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v10, 7
; RV32-ELEN8-NEXT: vsetivli zero, 9, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v9, 8
; RV32-ELEN8-NEXT: vsetivli zero, 10, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 9
; RV32-ELEN8-NEXT: vsetivli zero, 11, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v10, 10
; RV32-ELEN8-NEXT: li a0, 134
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetivli zero, 12, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 11
; RV32-ELEN8-NEXT: vsetivli zero, 13, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v11, 12
; RV32-ELEN8-NEXT: vsetivli zero, 14, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v12, 13
; RV32-ELEN8-NEXT: li a0, 186
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetivli zero, 15, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 14
; RV32-ELEN8-NEXT: li a0, 230
; RV32-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-ELEN8-NEXT: vmv.s.x v8, a0
; RV32-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV32-ELEN8-NEXT: vslideup.vi v0, v8, 15
; RV32-ELEN8-NEXT: ret
;
; RV64-ELEN8-LABEL: buildvec_mask_v128i1:
; RV64-ELEN8: # %bb.0:
; RV64-ELEN8-NEXT: li a0, 6
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: li a0, 240
; RV64-ELEN8-NEXT: vmv.s.x v9, a0
; RV64-ELEN8-NEXT: vsetivli zero, 2, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vmv1r.v v0, v9
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 1
; RV64-ELEN8-NEXT: li a0, 182
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v10, a0
; RV64-ELEN8-NEXT: vsetivli zero, 3, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v10, 2
; RV64-ELEN8-NEXT: vsetivli zero, 4, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v10, 3
; RV64-ELEN8-NEXT: li a0, 255
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v11, a0
; RV64-ELEN8-NEXT: vsetivli zero, 5, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v11, 4
; RV64-ELEN8-NEXT: li a0, 56
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v12, a0
; RV64-ELEN8-NEXT: vsetivli zero, 6, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v12, 5
; RV64-ELEN8-NEXT: vsetivli zero, 7, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v10, 6
; RV64-ELEN8-NEXT: vsetivli zero, 8, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v10, 7
; RV64-ELEN8-NEXT: vsetivli zero, 9, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v9, 8
; RV64-ELEN8-NEXT: vsetivli zero, 10, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 9
; RV64-ELEN8-NEXT: vsetivli zero, 11, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v10, 10
; RV64-ELEN8-NEXT: li a0, 134
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetivli zero, 12, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 11
; RV64-ELEN8-NEXT: vsetivli zero, 13, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v11, 12
; RV64-ELEN8-NEXT: vsetivli zero, 14, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v12, 13
; RV64-ELEN8-NEXT: li a0, 186
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetivli zero, 15, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 14
; RV64-ELEN8-NEXT: li a0, 230
; RV64-ELEN8-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-ELEN8-NEXT: vmv.s.x v8, a0
; RV64-ELEN8-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; RV64-ELEN8-NEXT: vslideup.vi v0, v8, 15
; RV64-ELEN8-NEXT: ret
ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1> ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
} }
define <128 x i1> @buildvec_mask_optsize_v128i1() optsize { define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1: ; RV32-LMULMAX1-LABEL: buildvec_mask_optsize_v128i1:
; RV32-LMULMAX1: # %bb.0: ; RV32-LMULMAX1: # %bb.0:
; RV32-LMULMAX1-NEXT: li a0, 1776 ; RV32-LMULMAX1-NEXT: li a0, 1776
; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; RV32-LMULMAX1-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1: ; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
; RV64-LMULMAX8: # %bb.0: ; RV64-LMULMAX8: # %bb.0:
; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI21_0) ; RV64-LMULMAX8-NEXT: lui a0, %hi(.LCPI21_0)
; RV64-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0) ; RV64-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV64-LMULMAX8-NEXT: li a1, 128 ; RV64-LMULMAX8-NEXT: li a1, 128
; RV64-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; RV64-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; RV64-LMULMAX8-NEXT: vlm.v v0, (a0) ; RV64-LMULMAX8-NEXT: vlm.v v0, (a0)
; RV64-LMULMAX8-NEXT: ret ; RV64-LMULMAX8-NEXT: ret
;
; RV32-ELEN-LABEL: buildvec_mask_optsize_v128i1:
; RV32-ELEN: # %bb.0:
; RV32-ELEN-NEXT: lui a0, %hi(.LCPI21_0)
; RV32-ELEN-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV32-ELEN-NEXT: li a1, 128
; RV32-ELEN-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; RV32-ELEN-NEXT: vlm.v v0, (a0)
; RV32-ELEN-NEXT: ret
;
; RV64-ELEN-LABEL: buildvec_mask_optsize_v128i1:
; RV64-ELEN: # %bb.0:
; RV64-ELEN-NEXT: lui a0, %hi(.LCPI21_0)
; RV64-ELEN-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV64-ELEN-NEXT: li a1, 128
; RV64-ELEN-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; RV64-ELEN-NEXT: vlm.v v0, (a0)
; RV64-ELEN-NEXT: ret
ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1> ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
} }