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Differential D117239

[RISCV] Add basic support for matching shuffles to vslidedown.vi.
ClosedPublic

Authored by craig.topper on Jan 13 2022, 10:42 AM.

Details

Reviewers
frasercrmck
rogfer01
arcbbb
khchen
kito-cheng
Commits
rG2baa1dffd1fb: [RISCV] Add basic support for matching shuffles to vslidedown.vi.
Summary

Specifically the unary shuffle case where the elements being
shifted in are undef. This handles the shuffles produce by expanding
llvm.reduce.mul.

I did not reduce the VL which would increase the number of vsetvlis,
but may improve the execution speed. We'd also want to narrow the
multiplies so we could share vsetvlis between the vslidedown.vi and
the next multiply.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 13 2022, 10:42 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 13 2022, 10:42 AM
craig.topper requested review of this revision.Jan 13 2022, 10:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2022, 10:42 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B143200: Diff 399725.Jan 13 2022, 11:30 AM
frasercrmck accepted this revision.Jan 14 2022, 6:15 AM

LGTM

This revision is now accepted and ready to land.Jan 14 2022, 6:15 AM
This revision was landed with ongoing or failed builds.Jan 14 2022, 9:09 AM
Closed by commit rG2baa1dffd1fb: [RISCV] Add basic support for matching shuffles to vslidedown.vi. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG2baa1dffd1fb: [RISCV] Add basic support for matching shuffles to vslidedown.vi..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
43 lines
test/
CodeGen/
RISCV/
rvv/
20 lines
20 lines
494 lines

Diff 400041

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,291 Lines • ▼ Show 20 Linesstatic SDValue lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL,
if (isOneConstant(VL) && isNullConstant(Scalar)) if (isOneConstant(VL) && isNullConstant(Scalar))
return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT), return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, DAG.getUNDEF(VT),
DAG.getConstant(0, DL, XLenVT), VL); DAG.getConstant(0, DL, XLenVT), VL);
// Otherwise use the more complicated splatting algorithm. // Otherwise use the more complicated splatting algorithm.
return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG); return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG);
} }
// Is the mask a slidedown that shifts in undefs.
static int matchShuffleAsSlideDown(ArrayRef<int> Mask) {
int Size = Mask.size();
// Elements shifted in should be undef.
auto CheckUndefs = [&](int Shift) {
for (int i = Size - Shift; i != Size; ++i)
if (Mask[i] >= 0)
return false;
return true;
};
// Elements should be shifted or undef.
auto MatchShift = [&](int Shift) {
for (int i = 0; i != Size - Shift; ++i)
if (Mask[i] >= 0 && Mask[i] != Shift + i)
return false;
return true;
};
// Try all possible shifts.
for (int Shift = 1; Shift != Size; ++Shift)
if (CheckUndefs(Shift) && MatchShift(Shift))
return Shift;
// No match.
return -1;
}
static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) { const RISCVSubtarget &Subtarget) {
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1); SDValue V2 = Op.getOperand(1);
SDLoc DL(Op); SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
unsigned NumElts = VT.getVectorNumElements(); unsigned NumElts = VT.getVectorNumElements();
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (Lane >= 0) {
assert(Lane < (int)NumElts && "Unexpected lane!"); assert(Lane < (int)NumElts && "Unexpected lane!");
SDValue Gather = SDValue Gather =
DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, V1, DAG.getNode(RISCVISD::VRGATHER_VX_VL, DL, ContainerVT, V1,
DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL); DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL);
return convertFromScalableVector(VT, Gather, DAG, Subtarget); return convertFromScalableVector(VT, Gather, DAG, Subtarget);
} }
} }
// Try to match as a slidedown.
int SlideAmt = matchShuffleAsSlideDown(SVN->getMask());
if (SlideAmt >= 0) {
// TODO: Should we reduce the VL to account for the upper undef elements?
// Requires additional vsetvlis, but might be faster to execute.
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
SDValue SlideDown =
DAG.getNode(RISCVISD::VSLIDEDOWN_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), V1,
DAG.getConstant(SlideAmt, DL, XLenVT),
TrueMask, VL);
return convertFromScalableVector(VT, SlideDown, DAG, Subtarget);
}
// Detect shuffles which can be re-expressed as vector selects; these are // Detect shuffles which can be re-expressed as vector selects; these are
// shuffles in which each element in the destination is taken from an element // shuffles in which each element in the destination is taken from an element
// at the corresponding index in either source vectors. // at the corresponding index in either source vectors.
bool IsSelect = all_of(enumerate(SVN->getMask()), [&](const auto &MaskIdx) { bool IsSelect = all_of(enumerate(SVN->getMask()), [&](const auto &MaskIdx) {
int MaskIndex = MaskIdx.value(); int MaskIndex = MaskIdx.value();
return MaskIndex < 0 || MaskIdx.index() == (unsigned)MaskIndex % NumElts; return MaskIndex < 0 || MaskIdx.index() == (unsigned)MaskIndex % NumElts;
}); });
▲ Show 20 Lines • Show All 8,210 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vlse64.v v10, (a0), zero ; RV64-NEXT: vlse64.v v10, (a0), zero
; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t ; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t
; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5> %s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x half> @slidedown_v4f16(<4 x half> %x) {
; CHECK-LABEL: slidedown_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: ret
%s = shufflevector <4 x half> %x, <4 x half> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 undef>
ret <4 x half> %s
}
define <8 x float> @slidedown_v8f32(<8 x float> %x) {
; CHECK-LABEL: slidedown_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: ret
%s = shufflevector <8 x float> %x, <8 x float> poison, <8 x i32> <i32 3, i32 undef, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %s
}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 535 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, tu, mu
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v8, v9, 3 ; CHECK-NEXT: vrgather.vi v8, v9, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> %shuf = shufflevector <4 x i8> %v, <4 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <8 x i8> %shuf ret <8 x i8> %shuf
} }
define <4 x i16> @slidedown_v4i16(<4 x i16> %x) {
; CHECK-LABEL: slidedown_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 undef>
ret <4 x i16> %s
}
define <8 x i32> @slidedown_v8i32(<8 x i32> %x) {
; CHECK-LABEL: slidedown_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 3
; CHECK-NEXT: ret
%s = shufflevector <8 x i32> %x, <8 x i32> poison, <8 x i32> <i32 3, i32 undef, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i32> %s
}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

Show First 20 Lines • Show All 5,578 Lines • ▼ Show 20 Lines
declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>) declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)
define i8 @vreduce_mul_v4i8(<4 x i8>* %x) { define i8 @vreduce_mul_v4i8(<4 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v4i8: ; CHECK-LABEL: vreduce_mul_v4i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vadd.vi v9, v9, 2 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i8>, <4 x i8>* %x %v = load <4 x i8>, <4 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v8i8(<8 x i8>) declare i8 @llvm.vector.reduce.mul.v8i8(<8 x i8>)
define i8 @vreduce_mul_v8i8(<8 x i8>* %x) { define i8 @vreduce_mul_v8i8(<8 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v8i8: ; CHECK-LABEL: vreduce_mul_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 4
; CHECK-NEXT: vadd.vi v10, v9, 4 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v11, v8, v10 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v11 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vadd.vi v9, v9, 2
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i8>, <8 x i8>* %x %v = load <8 x i8>, <8 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v8i8(<8 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v16i8(<16 x i8>) declare i8 @llvm.vector.reduce.mul.v16i8(<16 x i8>)
define i8 @vreduce_mul_v16i8(<16 x i8>* %x) { define i8 @vreduce_mul_v16i8(<16 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v16i8: ; CHECK-LABEL: vreduce_mul_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vadd.vi v10, v9, 8 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v11, v8, v10 ; CHECK-NEXT: vslidedown.vi v9, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v11 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vadd.vi v10, v9, 4 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vrgather.vv v11, v8, v10 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v11
; CHECK-NEXT: vadd.vi v9, v9, 2
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x i8>, <16 x i8>* %x %v = load <16 x i8>, <16 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v16i8(<16 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v32i8(<32 x i8>) declare i8 @llvm.vector.reduce.mul.v32i8(<32 x i8>)
define i8 @vreduce_mul_v32i8(<32 x i8>* %x) { define i8 @vreduce_mul_v32i8(<32 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v32i8: ; CHECK-LABEL: vreduce_mul_v32i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI253_0) ; CHECK-NEXT: vslidedown.vi v10, v8, 16
; CHECK-NEXT: addi a0, a0, %lo(.LCPI253_0) ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vrgather.vv v12, v8, v10 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vadd.vi v12, v10, 8 ; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v14, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v14
; CHECK-NEXT: vadd.vi v12, v10, 4
; CHECK-NEXT: vrgather.vv v14, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v14
; CHECK-NEXT: vadd.vi v10, v10, 2
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vrgather.vi v10, v8, 1 ; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x i8>, <32 x i8>* %x %v = load <32 x i8>, <32 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v32i8(<32 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v64i8(<64 x i8>) declare i8 @llvm.vector.reduce.mul.v64i8(<64 x i8>)
define i8 @vreduce_mul_v64i8(<64 x i8>* %x) { define i8 @vreduce_mul_v64i8(<64 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v64i8: ; CHECK-LABEL: vreduce_mul_v64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI254_0) ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: addi a0, a0, %lo(.LCPI254_0) ; CHECK-NEXT: vslidedown.vx v12, v8, a0
; CHECK-NEXT: vle8.v v12, (a0) ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: lui a0, %hi(.LCPI254_1) ; CHECK-NEXT: vslidedown.vi v12, v8, 16
; CHECK-NEXT: addi a0, a0, %lo(.LCPI254_1) ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vslidedown.vi v12, v8, 8
; CHECK-NEXT: vrgather.vv v20, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v20 ; CHECK-NEXT: vslidedown.vi v12, v8, 4
; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vadd.vi v16, v12, 8
; CHECK-NEXT: vrgather.vv v20, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v20
; CHECK-NEXT: vadd.vi v16, v12, 4
; CHECK-NEXT: vrgather.vv v20, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v20
; CHECK-NEXT: vadd.vi v12, v12, 2
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vi v12, v8, 1 ; CHECK-NEXT: vrgather.vi v12, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x i8>, <64 x i8>* %x %v = load <64 x i8>, <64 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v64i8(<64 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v128i8(<128 x i8>) declare i8 @llvm.vector.reduce.mul.v128i8(<128 x i8>)
define i8 @vreduce_mul_v128i8(<128 x i8>* %x) { define i8 @vreduce_mul_v128i8(<128 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v128i8: ; CHECK-LABEL: vreduce_mul_v128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI255_0) ; CHECK-NEXT: li a0, 64
; CHECK-NEXT: addi a0, a0, %lo(.LCPI255_0) ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: lui a0, %hi(.LCPI255_1) ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: addi a0, a0, %lo(.LCPI255_1) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: lui a0, %hi(.LCPI255_2)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI255_2)
; CHECK-NEXT: vle8.v v0, (a0)
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v0 ; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vadd.vi v24, v16, 8
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x i8>, <128 x i8>* %x %v = load <128 x i8>, <128 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %v)
ret i8 %red ret i8 %red
} }
declare i8 @llvm.vector.reduce.mul.v256i8(<256 x i8>) declare i8 @llvm.vector.reduce.mul.v256i8(<256 x i8>)
define i8 @vreduce_mul_v256i8(<256 x i8>* %x) { define i8 @vreduce_mul_v256i8(<256 x i8>* %x) {
; CHECK-LABEL: vreduce_mul_v256i8: ; CHECK-LABEL: vreduce_mul_v256i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128 ; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle8.v v16, (a0) ; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI256_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI256_0)
; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: li a0, 64
; CHECK-NEXT: lui a0, %hi(.LCPI256_1) ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: addi a0, a0, %lo(.LCPI256_1) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: lui a0, %hi(.LCPI256_2) ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: addi a0, a0, %lo(.LCPI256_2) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vle8.v v0, (a0) ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v0 ; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vadd.vi v24, v16, 8
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <256 x i8>, <256 x i8>* %x %v = load <256 x i8>, <256 x i8>* %x
%red = call i8 @llvm.vector.reduce.mul.v256i8(<256 x i8> %v) %red = call i8 @llvm.vector.reduce.mul.v256i8(<256 x i8> %v)
ret i8 %red ret i8 %red
} }
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declare i16 @llvm.vector.reduce.mul.v4i16(<4 x i16>) declare i16 @llvm.vector.reduce.mul.v4i16(<4 x i16>)
define i16 @vreduce_mul_v4i16(<4 x i16>* %x) { define i16 @vreduce_mul_v4i16(<4 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v4i16: ; CHECK-LABEL: vreduce_mul_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vadd.vi v9, v9, 2 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i16>, <4 x i16>* %x %v = load <4 x i16>, <4 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %v)
ret i16 %red ret i16 %red
} }
declare i16 @llvm.vector.reduce.mul.v8i16(<8 x i16>) declare i16 @llvm.vector.reduce.mul.v8i16(<8 x i16>)
define i16 @vreduce_mul_v8i16(<8 x i16>* %x) { define i16 @vreduce_mul_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v8i16: ; CHECK-LABEL: vreduce_mul_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 4
; CHECK-NEXT: vadd.vi v10, v9, 4 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v11, v8, v10 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v11 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vadd.vi v9, v9, 2
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i16>, <8 x i16>* %x %v = load <8 x i16>, <8 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v8i16(<8 x i16> %v)
ret i16 %red ret i16 %red
} }
declare i16 @llvm.vector.reduce.mul.v16i16(<16 x i16>) declare i16 @llvm.vector.reduce.mul.v16i16(<16 x i16>)
define i16 @vreduce_mul_v16i16(<16 x i16>* %x) { define i16 @vreduce_mul_v16i16(<16 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v16i16: ; CHECK-LABEL: vreduce_mul_v16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vadd.vi v12, v10, 8 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vv v14, v8, v12 ; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v14 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vadd.vi v12, v10, 4 ; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v14, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v14
; CHECK-NEXT: vadd.vi v10, v10, 2
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vrgather.vi v10, v8, 1 ; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x i16>, <16 x i16>* %x %v = load <16 x i16>, <16 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %v)
ret i16 %red ret i16 %red
} }
declare i16 @llvm.vector.reduce.mul.v32i16(<32 x i16>) declare i16 @llvm.vector.reduce.mul.v32i16(<32 x i16>)
define i16 @vreduce_mul_v32i16(<32 x i16>* %x) { define i16 @vreduce_mul_v32i16(<32 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v32i16: ; CHECK-LABEL: vreduce_mul_v32i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI262_0) ; CHECK-NEXT: vslidedown.vi v12, v8, 16
; CHECK-NEXT: addi a0, a0, %lo(.LCPI262_0) ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vle16.v v12, (a0) ; CHECK-NEXT: vslidedown.vi v12, v8, 8
; CHECK-NEXT: vrgather.vv v16, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vslidedown.vi v12, v8, 4
; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vadd.vi v16, v12, 8 ; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vrgather.vv v20, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v20
; CHECK-NEXT: vadd.vi v16, v12, 4
; CHECK-NEXT: vrgather.vv v20, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v20
; CHECK-NEXT: vadd.vi v12, v12, 2
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vi v12, v8, 1 ; CHECK-NEXT: vrgather.vi v12, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x i16>, <32 x i16>* %x %v = load <32 x i16>, <32 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v32i16(<32 x i16> %v)
ret i16 %red ret i16 %red
} }
declare i16 @llvm.vector.reduce.mul.v64i16(<64 x i16>) declare i16 @llvm.vector.reduce.mul.v64i16(<64 x i16>)
define i16 @vreduce_mul_v64i16(<64 x i16>* %x) { define i16 @vreduce_mul_v64i16(<64 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v64i16: ; CHECK-LABEL: vreduce_mul_v64i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI263_0) ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: addi a0, a0, %lo(.LCPI263_0) ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI263_1) ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: addi a0, a0, %lo(.LCPI263_1) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vrgather.vv v0, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v0 ; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vadd.vi v24, v16, 8
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x i16>, <64 x i16>* %x %v = load <64 x i16>, <64 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> %v)
ret i16 %red ret i16 %red
} }
declare i16 @llvm.vector.reduce.mul.v128i16(<128 x i16>) declare i16 @llvm.vector.reduce.mul.v128i16(<128 x i16>)
define i16 @vreduce_mul_v128i16(<128 x i16>* %x) { define i16 @vreduce_mul_v128i16(<128 x i16>* %x) {
; CHECK-LABEL: vreduce_mul_v128i16: ; CHECK-LABEL: vreduce_mul_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI264_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI264_0)
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI264_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI264_1)
; CHECK-NEXT: vle16.v v0, (a0)
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v0 ; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vadd.vi v24, v16, 8
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x i16>, <128 x i16>* %x %v = load <128 x i16>, <128 x i16>* %x
%red = call i16 @llvm.vector.reduce.mul.v128i16(<128 x i16> %v) %red = call i16 @llvm.vector.reduce.mul.v128i16(<128 x i16> %v)
ret i16 %red ret i16 %red
} }
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declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>) declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)
define i32 @vreduce_mul_v4i32(<4 x i32>* %x) { define i32 @vreduce_mul_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: vreduce_mul_v4i32: ; CHECK-LABEL: vreduce_mul_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: vslidedown.vi v9, v8, 2
; CHECK-NEXT: vadd.vi v9, v9, 2 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: vmul.vv v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x i32>, <4 x i32>* %x %v = load <4 x i32>, <4 x i32>* %x
%red = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %v) %red = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %v)
ret i32 %red ret i32 %red
} }
declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>) declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>)
define i32 @vreduce_mul_v8i32(<8 x i32>* %x) { define i32 @vreduce_mul_v8i32(<8 x i32>* %x) {
; CHECK-LABEL: vreduce_mul_v8i32: ; CHECK-LABEL: vreduce_mul_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vslidedown.vi v10, v8, 4
; CHECK-NEXT: vadd.vi v12, v10, 4 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vrgather.vv v14, v8, v12 ; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v14 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vadd.vi v10, v10, 2
; CHECK-NEXT: vrgather.vv v12, v8, v10
; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vrgather.vi v10, v8, 1 ; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: vmul.vv v8, v8, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x i32>, <8 x i32>* %x %v = load <8 x i32>, <8 x i32>* %x
%red = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %v) %red = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %v)
ret i32 %red ret i32 %red
} }
declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>) declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>)
define i32 @vreduce_mul_v16i32(<16 x i32>* %x) { define i32 @vreduce_mul_v16i32(<16 x i32>* %x) {
; CHECK-LABEL: vreduce_mul_v16i32: ; CHECK-LABEL: vreduce_mul_v16i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vid.v v12 ; CHECK-NEXT: vslidedown.vi v12, v8, 8
; CHECK-NEXT: vadd.vi v16, v12, 8 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vrgather.vv v20, v8, v16 ; CHECK-NEXT: vslidedown.vi v12, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v20 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vadd.vi v16, v12, 4 ; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vrgather.vv v20, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v20
; CHECK-NEXT: vadd.vi v12, v12, 2
; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vi v12, v8, 1 ; CHECK-NEXT: vrgather.vi v12, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: vmul.vv v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x i32>, <16 x i32>* %x %v = load <16 x i32>, <16 x i32>* %x
%red = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v) %red = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %v)
ret i32 %red ret i32 %red
} }
declare i32 @llvm.vector.reduce.mul.v32i32(<32 x i32>) declare i32 @llvm.vector.reduce.mul.v32i32(<32 x i32>)
define i32 @vreduce_mul_v32i32(<32 x i32>* %x) { define i32 @vreduce_mul_v32i32(<32 x i32>* %x) {
; CHECK-LABEL: vreduce_mul_v32i32: ; CHECK-LABEL: vreduce_mul_v32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI270_0) ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: addi a0, a0, %lo(.LCPI270_0) ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vrgather.vv v24, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24 ; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vid.v v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vadd.vi v24, v16, 8 ; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vrgather.vv v0, v8, v24 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x i32>, <32 x i32>* %x %v = load <32 x i32>, <32 x i32>* %x
%red = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> %v) %red = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> %v)
ret i32 %red ret i32 %red
} }
declare i32 @llvm.vector.reduce.mul.v64i32(<64 x i32>) declare i32 @llvm.vector.reduce.mul.v64i32(<64 x i32>)
define i32 @vreduce_mul_v64i32(<64 x i32>* %x) { define i32 @vreduce_mul_v64i32(<64 x i32>* %x) {
; CHECK-LABEL: vreduce_mul_v64i32: ; CHECK-LABEL: vreduce_mul_v64i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI271_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI271_0)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vslidedown.vi v16, v8, 16
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 4
; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vslidedown.vi v16, v8, 2
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vadd.vi v24, v16, 8
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v24, v16, 4
; CHECK-NEXT: vrgather.vv v0, v8, v24
; CHECK-NEXT: vmul.vv v8, v8, v0
; CHECK-NEXT: vadd.vi v16, v16, 2
; CHECK-NEXT: vrgather.vv v24, v8, v16
; CHECK-NEXT: vmul.vv v8, v8, v24
; CHECK-NEXT: vrgather.vi v16, v8, 1 ; CHECK-NEXT: vrgather.vi v16, v8, 1
; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: vmul.vv v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x i32>, <64 x i32>* %x %v = load <64 x i32>, <64 x i32>* %x
%red = call i32 @llvm.vector.reduce.mul.v64i32(<64 x i32> %v) %red = call i32 @llvm.vector.reduce.mul.v64i32(<64 x i32> %v)
ret i32 %red ret i32 %red
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>) declare i64 @llvm.vector.reduce.mul.v4i64(<4 x i64>)
define i64 @vreduce_mul_v4i64(<4 x i64>* %x) { define i64 @vreduce_mul_v4i64(<4 x i64>* %x) {
; RV32-LABEL: vreduce_mul_v4i64: ; RV32-LABEL: vreduce_mul_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; RV32-NEXT: vslidedown.vi v10, v8, 2
; RV32-NEXT: vid.v v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: vadd.vi v10, v10, 2
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v8, v10
; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vrgather.vi v10, v8, 1 ; RV32-NEXT: vrgather.vi v10, v8, 1
; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: vmul.vv v8, v8, v10
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v4i64: ; RV64-LABEL: vreduce_mul_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vid.v v10 ; RV64-NEXT: vslidedown.vi v10, v8, 2
; RV64-NEXT: vadd.vi v10, v10, 2 ; RV64-NEXT: vmul.vv v8, v8, v10
; RV64-NEXT: vrgather.vv v12, v8, v10
; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vrgather.vi v10, v8, 1 ; RV64-NEXT: vrgather.vi v10, v8, 1
; RV64-NEXT: vmul.vv v8, v8, v10 ; RV64-NEXT: vmul.vv v8, v8, v10
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <4 x i64>, <4 x i64>* %x %v = load <4 x i64>, <4 x i64>* %x
%red = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> %v) %red = call i64 @llvm.vector.reduce.mul.v4i64(<4 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64>) declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64>)
define i64 @vreduce_mul_v8i64(<8 x i64>* %x) { define i64 @vreduce_mul_v8i64(<8 x i64>* %x) {
; RV32-LABEL: vreduce_mul_v8i64: ; RV32-LABEL: vreduce_mul_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; RV32-NEXT: vslidedown.vi v12, v8, 4
; RV32-NEXT: vid.v v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vadd.vi v13, v12, 4 ; RV32-NEXT: vslidedown.vi v12, v8, 2
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vrgatherei16.vv v16, v8, v13
; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; RV32-NEXT: vadd.vi v12, v12, 2
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v8, v12
; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vrgather.vi v12, v8, 1 ; RV32-NEXT: vrgather.vi v12, v8, 1
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v8i64: ; RV64-LABEL: vreduce_mul_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vid.v v12 ; RV64-NEXT: vslidedown.vi v12, v8, 4
; RV64-NEXT: vadd.vi v16, v12, 4 ; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vrgather.vv v20, v8, v16 ; RV64-NEXT: vslidedown.vi v12, v8, 2
; RV64-NEXT: vmul.vv v8, v8, v20 ; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vadd.vi v12, v12, 2
; RV64-NEXT: vrgather.vv v16, v8, v12
; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vrgather.vi v12, v8, 1 ; RV64-NEXT: vrgather.vi v12, v8, 1
; RV64-NEXT: vmul.vv v8, v8, v12 ; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <8 x i64>, <8 x i64>* %x %v = load <8 x i64>, <8 x i64>* %x
%red = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %v) %red = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.mul.v16i64(<16 x i64>) declare i64 @llvm.vector.reduce.mul.v16i64(<16 x i64>)
define i64 @vreduce_mul_v16i64(<16 x i64>* %x) { define i64 @vreduce_mul_v16i64(<16 x i64>* %x) {
; RV32-LABEL: vreduce_mul_v16i64: ; RV32-LABEL: vreduce_mul_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32-NEXT: vslidedown.vi v16, v8, 8
; RV32-NEXT: vid.v v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vadd.vi v18, v16, 8 ; RV32-NEXT: vslidedown.vi v16, v8, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vrgatherei16.vv v24, v8, v18 ; RV32-NEXT: vslidedown.vi v16, v8, 2
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v18, v16, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v18
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v16, v16, 2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vrgather.vi v16, v8, 1 ; RV32-NEXT: vrgather.vi v16, v8, 1
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, mu
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v16i64: ; RV64-LABEL: vreduce_mul_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vid.v v16 ; RV64-NEXT: vslidedown.vi v16, v8, 8
; RV64-NEXT: vadd.vi v24, v16, 8 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vslidedown.vi v16, v8, 4
; RV64-NEXT: vmul.vv v8, v8, v0 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vadd.vi v24, v16, 4 ; RV64-NEXT: vslidedown.vi v16, v8, 2
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v0
; RV64-NEXT: vadd.vi v16, v16, 2
; RV64-NEXT: vrgather.vv v24, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v24
; RV64-NEXT: vrgather.vi v16, v8, 1 ; RV64-NEXT: vrgather.vi v16, v8, 1
; RV64-NEXT: vmul.vv v8, v8, v16 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <16 x i64>, <16 x i64>* %x %v = load <16 x i64>, <16 x i64>* %x
%red = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> %v) %red = call i64 @llvm.vector.reduce.mul.v16i64(<16 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.mul.v32i64(<32 x i64>) declare i64 @llvm.vector.reduce.mul.v32i64(<32 x i64>)
define i64 @vreduce_mul_v32i64(<32 x i64>* %x) { define i64 @vreduce_mul_v32i64(<32 x i64>* %x) {
; RV32-LABEL: vreduce_mul_v32i64: ; RV32-LABEL: vreduce_mul_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v16, (a0) ; RV32-NEXT: vle64.v v16, (a0)
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32-NEXT: vslidedown.vi v16, v8, 8
; RV32-NEXT: vid.v v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vadd.vi v18, v16, 8 ; RV32-NEXT: vslidedown.vi v16, v8, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vrgatherei16.vv v24, v8, v18 ; RV32-NEXT: vslidedown.vi v16, v8, 2
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v18, v16, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v18
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v16, v16, 2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vrgather.vi v16, v8, 1 ; RV32-NEXT: vrgather.vi v16, v8, 1
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; RV32-NEXT: vsetivli zero, 0, e32, m8, ta, mu
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e32, m8, ta, mu
; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v32i64: ; RV64-LABEL: vreduce_mul_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: vmul.vv v8, v8, v16 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vid.v v16 ; RV64-NEXT: vslidedown.vi v16, v8, 8
; RV64-NEXT: vadd.vi v24, v16, 8 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vslidedown.vi v16, v8, 4
; RV64-NEXT: vmul.vv v8, v8, v0 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vadd.vi v24, v16, 4 ; RV64-NEXT: vslidedown.vi v16, v8, 2
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v0
; RV64-NEXT: vadd.vi v16, v16, 2
; RV64-NEXT: vrgather.vv v24, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v24
; RV64-NEXT: vrgather.vi v16, v8, 1 ; RV64-NEXT: vrgather.vi v16, v8, 1
; RV64-NEXT: vmul.vv v8, v8, v16 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <32 x i64>, <32 x i64>* %x %v = load <32 x i64>, <32 x i64>* %x
%red = call i64 @llvm.vector.reduce.mul.v32i64(<32 x i64> %v) %red = call i64 @llvm.vector.reduce.mul.v32i64(<32 x i64> %v)
ret i64 %red ret i64 %red
} }
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; RV32-NEXT: vle64.v v16, (a1) ; RV32-NEXT: vle64.v v16, (a1)
; RV32-NEXT: addi a1, a0, 256 ; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: addi a0, a0, 128 ; RV32-NEXT: addi a0, a0, 128
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: vle64.v v0, (a1) ; RV32-NEXT: vle64.v v0, (a1)
; RV32-NEXT: vmul.vv v16, v24, v16 ; RV32-NEXT: vmul.vv v16, v24, v16
; RV32-NEXT: vmul.vv v8, v8, v0 ; RV32-NEXT: vmul.vv v8, v8, v0
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; RV32-NEXT: vslidedown.vi v16, v8, 8
; RV32-NEXT: vid.v v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vadd.vi v18, v16, 8 ; RV32-NEXT: vslidedown.vi v16, v8, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vrgatherei16.vv v24, v8, v18 ; RV32-NEXT: vslidedown.vi v16, v8, 2
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v18, v16, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v18
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, mu
; RV32-NEXT: vadd.vi v16, v16, 2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vrgatherei16.vv v24, v8, v16
; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: vrgather.vi v16, v8, 1 ; RV32-NEXT: vrgather.vi v16, v8, 1
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsetivli zero, 0, e32, m8, ta, mu ; RV32-NEXT: vsetivli zero, 0, e32, m8, ta, mu
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vsetivli zero, 1, e32, m8, ta, mu ; RV32-NEXT: vsetivli zero, 1, e32, m8, ta, mu
; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v64i64: ; RV64-LABEL: vreduce_mul_v64i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: addi a1, a0, 384 ; RV64-NEXT: addi a1, a0, 384
; RV64-NEXT: vle64.v v16, (a1) ; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: addi a1, a0, 256 ; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: addi a0, a0, 128 ; RV64-NEXT: addi a0, a0, 128
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: vle64.v v0, (a1) ; RV64-NEXT: vle64.v v0, (a1)
; RV64-NEXT: vmul.vv v16, v24, v16 ; RV64-NEXT: vmul.vv v16, v24, v16
; RV64-NEXT: vmul.vv v8, v8, v0 ; RV64-NEXT: vmul.vv v8, v8, v0
; RV64-NEXT: vmul.vv v8, v8, v16 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vid.v v16 ; RV64-NEXT: vslidedown.vi v16, v8, 8
; RV64-NEXT: vadd.vi v24, v16, 8 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vslidedown.vi v16, v8, 4
; RV64-NEXT: vmul.vv v8, v8, v0 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vadd.vi v24, v16, 4 ; RV64-NEXT: vslidedown.vi v16, v8, 2
; RV64-NEXT: vrgather.vv v0, v8, v24 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v0
; RV64-NEXT: vadd.vi v16, v16, 2
; RV64-NEXT: vrgather.vv v24, v8, v16
; RV64-NEXT: vmul.vv v8, v8, v24
; RV64-NEXT: vrgather.vi v16, v8, 1 ; RV64-NEXT: vrgather.vi v16, v8, 1
; RV64-NEXT: vmul.vv v8, v8, v16 ; RV64-NEXT: vmul.vv v8, v8, v16
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <64 x i64>, <64 x i64>* %x %v = load <64 x i64>, <64 x i64>* %x
%red = call i64 @llvm.vector.reduce.mul.v64i64(<64 x i64> %v) %red = call i64 @llvm.vector.reduce.mul.v64i64(<64 x i64> %v)
ret i64 %red ret i64 %red
} }