[RISCV] Initial support for scalable vectorization

[alextsao1999]

Summary

Initial support for scalable vectorization.
This patch add some basic implements of TTI for scalable vectorization.

[alextsao1999]

fix CI

[alextsao1999]

update

[jrtc27]

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vectorization.ll

2 ↗

(On Diff #396415)

Use update_test_checks.py, and preferably show the changes to the test case with this patch, not the whole test case, so it's clear what's been improved.

2 ↗

(On Diff #396415)

Don't use -linux-gnu targets when it's not OS-specific, just use riscv64 (aka riscv64-unknown-elf)

10 ↗

(On Diff #396415)

Not actually showing the code generated? Debug output is generally not great for testing, it's often unclear what's actually going on, it can only run in builds that have debugging built in and you have to write the CHECK lines by hand.

[craig.topper]

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vectorization.ll

7 ↗

(On Diff #396415)

This says SVE and the numbers weren't updated to match what is shown on the CHECK lines.

[alextsao1999]

update test case

[sdesmalen]

The commit message seems wrong, because this patch is about tuning the cost-model, not about enabling scalable vectorization.

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

166

You may want to add some unit tests to llvm/test/Analysis/CostModel/ for this change.

[alextsao1999]

In D116333#3219308, @sdesmalen wrote:

The commit message seems wrong, because this patch is about tuning the cost-model, not about enabling scalable vectorization.

That's because if you can't get the cost of some cast instructions, you will not force some instructions a specific cost...Maybe a better way is to make the cast instruction legal...

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vectorization.ll

2 ↗

(On Diff #396415)

thx, I will fix it

7 ↗

(On Diff #396415)

Thx...I have fixed it

10 ↗

(On Diff #396415)

The test case is from sve, so I think it's better to be consistent with sve...

[jrtc27]

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vectorization.ll

10 ↗

(On Diff #396415)

I disagree. Some other targets have some utterly crap tests, we don't need to copy them.

[sdesmalen]

In D116333#3219958, @alextsao1999 wrote:

In D116333#3219308, @sdesmalen wrote:

The commit message seems wrong, because this patch is about tuning the cost-model, not about enabling scalable vectorization.

That's because if you can't get the cost of some cast instructions, you will not force some instructions a specific cost...Maybe a better way is to make the cast instruction legal...

I see this as a separate concern, since scalable vectorization is already supported if the loop has no cast instructions.

llvm/test/Transforms/LoopVectorize/RISCV/scalable-vectorization.ll

10 ↗

(On Diff #396415)

It depends on what you want to test. For SVE we added this test purely to check which VF gets selected, since there are other tests for testing code-gen itself (because the loop itself is trivial for vectorization). That of course doesn't mean you have to follow the same approach for this test, you can do whatever has your preference.

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

public:
   InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                       const APInt &Imm, Type *Ty,
                                       TTI::TargetCostKind CostKind);
 
   TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
 
   bool shouldExpandReduction(const IntrinsicInst *II) const;
   bool supportsScalableVectors() const { return ST->hasVInstructions(); }
-  bool enableScalableVectorization() const { return ST->hasVInstructions(); }
   Optional<unsigned> getMaxVScale() const;
 
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
     switch (K) {
     case TargetTransformInfo::RGK_Scalar:
       return TypeSize::getFixed(ST->getXLen());
     case TargetTransformInfo::RGK_FixedWidthVector:
       return TypeSize::getFixed(

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

InstructionCost RISCVTTIImpl::getGatherScatterOpCost(
 
   auto *VTy = cast<FixedVectorType>(DataTy);
   unsigned NumLoads = VTy->getNumElements();
   InstructionCost MemOpCost =
       getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
   return NumLoads * MemOpCost;
 }
 
 InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
-                                                 Type *Src,
-                                                 TTI::CastContextHint CCH,
-                                                 TTI::TargetCostKind CostKind,
-                                                 const Instruction *I) {
   int ISD = TLI->InstructionOpcodeToISD(Opcode);
   assert(ISD && "Invalid opcode");
 
   // TODO: Allow non-throughput costs that aren't binary.
   auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost {
     if (CostKind != TTI::TCK_RecipThroughput)
       return Cost == 0 ? 0 : 1;
     return Cost;
   };
 
   EVT SrcTy = TLI->getValueType(DL, Src);
   EVT DstTy = TLI->getValueType(DL, Dst);
 
   if (!SrcTy.isSimple() || !DstTy.isSimple())
     return AdjustCost(
         BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
 
   if (ISD == ISD::ZERO_EXTEND && SrcTy.isScalableVector() &&
       DstTy.isScalableVector()) {
-    if (SrcTy.isInteger() && DstTy.isInteger()) {
+    if (SrcTy.isInteger() && DstTy.isInteger() &&
+        SrcTy.getVectorElementCount() == DstTy.getVectorElementCount()) {
       if (SrcTy.getScalarSizeInBits() <= DstTy.getScalarSizeInBits()) {
         return 0;
       }
     }
   }
 
   return AdjustCost(
       BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
-
 }
 
 void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                            TTI::UnrollingPreferences &UP,
                                            OptimizationRemarkEmitter *ORE) {
   // TODO: More tuning on benchmarks and metrics with changes as needed
   //       would apply to all settings below to enable performance.