[RISCV] Don't allow vector types to be used with inline asm 'r' constraint

[craig.topper]

Summary

The 'r' constraint uses the GPR class. There is generic support
for bitcasting and extending/truncating non-integer VTs to the
required integer VT. This doesn't work for scalable vectors and
instead crashes.

To prevent this, explicitly reject vectors. Fixed vectors might
work without crashing, but it doesn't seem worthwhile to allow.

While there remove an unnecessary level of indentation in the
"vr" and "vm" constraint handling.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9663

if (VT.isVector())
  break;

is a bit more extensible in that line lengths don't get stupidly long as the list grows; we exclude our own register class from r downstream like that.

[jrtc27]

I imagine fixed vectors will need to be allowed for P here, FWIW

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9665

While I'm here. This should be Zfhmin right?

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9665

Yeah

[craig.topper]

Address @jrtc's feedback. Add FIXME for P extension.

I thought about allowing fixed vectors, but if it is larger than XLen it creates multiple registers. So needs more care.

[craig.topper]

Ping

[jrtc27]

Though please alter the commit message to mention that the vr/vm changes are NFC cleanup to remove an unnecessary level of indentation, or words to that effect (assuming my understanding is correct)

[jrtc27]

llvm/test/CodeGen/RISCV/inline-asm-invalid.ll

39

Something weird happened here

[craig.topper]

Yeah I saw it when I reapplied the patch to test before committing. I’ll fix.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,
                                                   MVT VT) const {
   // First, see if this is a constraint that directly corresponds to a
   // RISCV register class.
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
+      // TODO: Support fixed vectors up to XLen for P extension?
+      if (VT.isVector())
+        break;
       return std::make_pair(0U, &RISCV::GPRRegClass);
     case 'f':
       if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
         return std::make_pair(0U, &RISCV::FPR16RegClass);
       if (Subtarget.hasStdExtF() && VT == MVT::f32)
         return std::make_pair(0U, &RISCV::FPR32RegClass);
       if (Subtarget.hasStdExtD() && VT == MVT::f64)
         return std::make_pair(0U, &RISCV::FPR64RegClass);
       break;
     default:
       break;
     }
-  } else {
-    if (Constraint == "vr") {
-      for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
-                             &RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) {
-        if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
-          return std::make_pair(0U, RC);
-      }
-    } else if (Constraint == "vm") {
-      if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
-        return std::make_pair(0U, &RISCV::VMV0RegClass);
-    }
-  }
+  } else if (Constraint == "vr") {
 
   // Clang will correctly decode the usage of register name aliases into their
   // official names. However, other frontends like `rustc` do not. This allows
   // users of these frontends to use the ABI names for registers in LLVM-style
   // register constraints.
   unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
                                .Case("{zero}", RISCV::X0)
                                .Case("{ra}", RISCV::X1)

llvm/test/CodeGen/RISCV/inline-asm-invalid.ll

 
 define void @constraint_f() nounwind {
 ; CHECK: error: couldn't allocate input reg for constraint 'f'
   tail call void asm "fadd.s fa0, fa0, $0", "f"(float 0.0)
 ; CHECK: error: couldn't allocate input reg for constraint 'f'
   tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
   ret void
 }
+
+define void @constraint_r_fixed_vec() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'r'
+  tail call void asm "add a0, a0, $0", "r"(<4 x i32> zeroinitializer)
+  ret void
+}
+
+define void @constraint_r_scalable_vec() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'r'
+  tail call void asm "add a0, a0, $0", "r"(<vscale x 4 x i32> zeroinitializer)
+  ret void
+}